Cascaded enhanced gallium nitride high-mobility transistor structure and packaging method

Abstract

The invention relates to a cascaded enhanced gallium nitride high-mobility transistor structure and a packaging method. The cascaded enhanced gallium nitride high-mobility transistor structure is obtained by packaging a low-voltage enhanced gallium nitride high-mobility transistor and a high-voltage depletion type gallium nitride high-mobility transistor through 3D stacking. Compared with a silicon device, the low-voltage enhanced gallium nitride high-electron-mobility transistor has the characteristics of no reverse recovery charge and high switching speed, the intrinsic performance advantages of the depletion type gallium nitride high-electron-mobility transistor are fully exerted, and the negative influence on the switching speed caused by a cascaded silicon device is avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a cascade enhanced gallium nitride high mobility transistor structure and a packaging method. Background Art

[0002] GaN-based high electron mobility transistors (HEMTs) combine the advantages of wide bandgap semiconductors and two-dimensional electron gas channels, and have advantages such as high breakdown electric field and high electron saturation drift velocity. They are ideal for high-frequency and high-efficiency power switches. As a power switching device, the device is required to be normally off, that is, an enhancement-type device to improve system safety, reduce device losses and simplify circuit design. However, depletion-type devices have inherent advantages over internal enhancement-type devices in terms of power density and reliability. Therefore, in order to maximize the performance advantages of the device itself, the depletion-type device can be converted into an enhancement-type device through an external cascade. At present, the most common method for realizing external enhancement-type GaN devices is to use a cascode structure composed of a low-voltage enhancement-type SiMOSFET and a high-voltage depletion-type GaN HEMT. This cascode structure is compatible with the Si-CMOS platform and has the advantages of low cost and low complexity. However, the SiMOS device used is usually a vertical structure, and the two tubes are generally interconnected by wire bonding, which has a large parasitic inductance, which will offset the switching speed advantage of the device itself. In order to give full play to the characteristics of the fast switching speed of the device, it is necessary to propose a cascade structure and packaging method with low parasitic effects. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a cascade enhancement-type gallium nitride high-mobility transistor structure and a packaging method, using a low-voltage enhancement-type gallium nitride high-mobility transistor (planar device) to replace the traditional low-voltage Si MOSFET (vertical device), so that it forms a cascade structure with a high-voltage depletion-type gallium nitride high-mobility transistor to achieve external enhancement.

[0004] The present invention provides a cascade enhancement-type gallium nitride high-mobility transistor structure, which is obtained by packaging a low-voltage enhancement-type gallium nitride high-mobility transistor and a high-voltage depletion-type gallium nitride high-mobility transistor through 3D stacking.

[0005] The present invention also provides a method for preparing a cascade enhanced gallium nitride high mobility transistor structure, comprising the following steps:

[0006] First, a low-voltage enhancement-mode GaN high-mobility transistor and a high-voltage depletion-mode GaN high-mobility transistor are packaged with low parasitics, and then the packaged low-voltage enhancement-mode GaN high-mobility transistor and the high-voltage depletion-mode GaN high-mobility transistor are three-dimensionally integrated by bonding with a carrier to obtain a cascade enhancement-mode GaN high-mobility transistor structure.

[0007] Preferably, the packaging method is FP-QFN or WLCSP.

[0008] Preferably, the carrier is a DBC or a ceramic substrate.

[0009] Beneficial Effects

[0010] (1) The present invention utilizes the characteristics of low-voltage enhancement-mode GaN high-mobility transistors, which have no reverse recovery charge and fast switching compared to silicon devices, to give full play to the intrinsic performance advantages of depletion-mode GaN high-electron-mobility transistors and avoid the negative impact of switching speed caused by cascaded silicon devices.

[0011] (2) Compared with the traditional wire bonding method, the packaging method of the transistor of the present invention further reduces parasitic inductance, improves switching speed, and reduces signal oscillation, and has good application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a structural schematic diagram of the present invention.

[0013] Figure 2 It is a schematic diagram of the 3D packaging structure of the present invention. DETAILED DESCRIPTION

[0014] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0015] Example 1

[0016] like Figure 1 As shown, this embodiment provides a cascade enhancement-type GaN high-mobility transistor structure, which is obtained by 3D stacking and packaging a low-voltage enhancement-type GaN high-mobility transistor and a high-voltage depletion-type GaN high-mobility transistor. This structure utilizes the characteristics of low-voltage enhancement-type GaN high-mobility transistors, which have no reverse recovery charge and fast switching compared to silicon devices, and gives full play to the intrinsic performance advantages of depletion-type GaN high electron mobility transistors, avoiding the negative impact of switching speed caused by cascade silicon devices. At the same time, this embodiment proposes a 3D packaging form for this cascade device structure, further reducing the parasitic inductance between the two cascade devices and improving the overall switching speed and device stability. The specific implementation method is as follows: Figure 2As shown. First, FP-QFN is used for low parasitic packaging of high-voltage depletion-mode GaN power devices and low-voltage enhancement-mode power devices. Then, DBC is used as a carrier to realize three-dimensional integration of the packaged high-voltage depletion-mode GaN power devices and low-voltage enhancement-mode power devices through bonding. Compared with the traditional wire bonding method, this packaging method can further reduce parasitic inductance, increase switching speed, and reduce signal oscillation, and has good application prospects.

Claims

1. A cascade enhancement mode gallium nitride high mobility transistor structure, characterized in that: The low-voltage enhancement-mode GaN high-mobility transistor and the high-voltage depletion-mode GaN high-mobility transistor are obtained by 3D stacking and packaging.

2. A method for preparing a cascade enhanced gallium nitride high mobility transistor structure, comprising the following steps: First, a low-voltage enhancement-mode GaN high-mobility transistor and a high-voltage depletion-mode GaN high-mobility transistor are packaged with low parasitics, and then the packaged low-voltage enhancement-mode GaN high-mobility transistor and the high-voltage depletion-mode GaN high-mobility transistor are three-dimensionally integrated by bonding with a carrier to obtain a cascade enhancement-mode GaN high-mobility transistor structure.

3. The preparation method according to claim 2, characterized in that: The packaging method is FP-QFN or WLCSP.

4. The preparation method according to claim 2, characterized in that: The carrier is a DBC or a ceramic substrate.

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