Metal-oxide-metal capacitor and manufacturing method thereof

Abstract

The invention provides a metal-oxide-metal capacitor and a manufacturing method thereof. The metal-oxide-metal capacitor comprises a semiconductor substrate; the bottom metal layer is arranged on the surface of the semiconductor substrate, and the bottom metal layer comprises a metal connecting wire; the interlayer dielectric layer is arranged on the surface of the bottom metal layer, at least one of a bottom groove and a top groove is formed in the interlayer dielectric layer, metal plugs are arranged in the bottom groove and the top groove, the bottom groove is communicated with the metal connecting line of the bottom metal layer, and / or the top groove is separated from the bottom metal layer; the top metal layer is arranged on the surface of the interlayer dielectric layer, the top metal layer comprises a metal connecting wire, the bottom groove is separated from the top metal layer, and / or the top groove is communicated with the metal connecting wire of the top metal layer; and the metal connecting wires of the bottom metal layer correspond to the metal connecting wires of the top metal layer. According to the invention, the effective parasitic area of the capacitor can be increased between two adjacent metal layers.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a metal-oxide-metal capacitor and a manufacturing method thereof. Background Art

[0002] Capacitors are important components in integrated circuits, among which metal-oxide-metal (MOM) capacitors are parasitic and generated by the back-end metal wiring process, and do not increase the cost and difficulty of process manufacturing. They are the most common capacitor structure in the integrated circuit manufacturing process. With the evolution and development of integrated circuit manufacturing processes, the process size continues to shrink, and the area of ​​metal-oxide-metal capacitors will also shrink. This requires that the capacitance density of metal-oxide-metal capacitors needs to be continuously improved. Therefore, it is an urgent problem to improve the capacitance density of metal-oxide-metal capacitors by improving the structure and manufacturing process of metal-oxide-metal capacitors. Summary of the invention

[0003] The present invention provides a metal-oxide-metal capacitor and a manufacturing method thereof, so as to solve the technical problem in the prior art that the capacitance density of the metal-oxide-metal capacitor needs to be continuously improved.

[0004] The present invention provides a metal-oxide-metal capacitor, comprising:

[0005] Semiconductor substrate;

[0006] A bottom metal layer, disposed on the surface of the semiconductor substrate, the bottom metal layer comprising metal wiring;

[0007] an interlayer dielectric layer, disposed on the surface of the bottom metal layer, wherein at least one of a bottom trench and a top trench is formed on the interlayer dielectric layer, wherein metal plugs are disposed in the bottom trench and the top trench, wherein the bottom trench is connected to a metal connection line of the bottom metal layer, and / or the top trench is separated from the bottom metal layer; and

[0008] A top metal layer, disposed on the surface of the interlayer dielectric layer, the top metal layer comprising metal wiring, wherein the bottom trench is separated from the top metal layer, and / or the top trench is connected to the metal wiring of the top metal layer;

[0009] The metal wiring of the bottom metal layer corresponds to the metal wiring of the top metal layer.

[0010] In one embodiment of the present invention, the metal wiring of the bottom metal layer is divided into a first type of metal wiring and a second type of metal wiring, and the first type of metal wiring and the second type of metal wiring are interlaced in a finger-like manner;

[0011] The metal connections of the top metal layer are divided into a first type of metal connections and a second type of metal connections, and the first type of metal connections and the second type of metal connections are interlaced in a finger-like manner;

[0012] The first type of metal connection line of the bottom metal layer and the first type of metal connection line of the top metal layer are located on the same side and electrically connected, and the second type of metal connection line of the bottom metal layer and the second type of metal connection line of the top metal layer are located on the same side and electrically connected.

[0013] In one embodiment of the present invention, the first type of metal wiring of the bottom metal layer corresponds to the second type of metal wiring of the top metal layer, and the second type of metal wiring of the bottom metal layer corresponds to the first type of metal wiring of the top metal layer.

[0014] In one embodiment of the present invention, the metal-oxide-metal capacitor further comprises:

[0015] A first buffer layer is arranged on the surface of the interlayer dielectric layer, the first buffer layer separates the bottom trench from the top metal layer, the top trench penetrates the first buffer layer, and the top trench is connected to the top metal layer.

[0016] In one embodiment of the present invention, the metal-oxide-metal capacitor further comprises:

[0017] The second buffer layer is arranged on the surface of the bottom metal layer, the second buffer layer separates the top groove from the bottom metal layer, the bottom groove penetrates the buffer layer, and the bottom groove is connected with the bottom metal layer.

[0018] In one embodiment of the present invention, the metal connection line includes:

[0019] Edge segment;

[0020] A plurality of line segments are electrically connected to the edge segments, the plurality of line segments are arranged in parallel, and there is a gap between two adjacent line segments;

[0021] Wherein, the metal connection line of the bottom metal layer and the metal connection line of the top metal layer are electrically connected through the edge segment.

[0022] In one embodiment of the present invention, in the top metal layer or the bottom metal layer, the line segments of the first type of metal lines and the line segments of the second type of metal lines are alternately distributed.

[0023] The present invention also provides a method for manufacturing a metal-oxide-metal capacitor, comprising:

[0024] Providing a semiconductor substrate;

[0025] forming a bottom metal layer on the surface of the semiconductor substrate, and forming metal wiring on the bottom metal layer;

[0026] An interlayer dielectric layer is formed on the surface of the bottom metal layer, at least one of a bottom trench and a top trench is formed on the interlayer dielectric layer, and metal plugs are arranged in the bottom trench and the top trench, wherein the bottom trench is connected to the metal wiring of the bottom metal layer, and / or the top trench is separated from the bottom metal layer;

[0027] Forming a top metal layer on the surface of the interlayer dielectric layer, and forming a metal connection line on the top metal layer, wherein the bottom trench is separated from the top metal layer, and / or the top trench is connected to the metal connection line of the top metal layer;

[0028] The metal wiring of the top metal layer is matched with the metal wiring of the bottom metal layer.

[0029] In one embodiment of the present invention, the step of forming metal wiring on the bottom metal layer includes:

[0030] Dividing the metal connections on the bottom metal layer into first-type metal connections and second-type metal connections;

[0031] The first type of metal connecting wires and the second type of metal connecting wires are staggered and distributed at finger-shaped intervals.

[0032] In one embodiment of the present invention, the step of forming metal wiring on the top metal layer includes:

[0033] Divide the metal connections on the top metal layer into first-type metal connections and second-type metal connections, and distribute the first-type metal connections and the second-type metal connections alternately at finger-shaped intervals;

[0034] The first type of metal connection line of the top metal layer and the first type of metal connection line of the bottom metal layer are arranged on the same side and electrically connected, and the second type of metal connection line of the top metal layer and the second type of metal connection line of the bottom metal layer are arranged on the same side and electrically connected.

[0035] Beneficial effects of the present invention: The present invention proposes a metal-oxide-metal capacitor and a method for manufacturing the same, which utilizes the capacitance effect of metal plugs between two adjacent metal layers to increase the effective parasitic area of ​​the capacitor, thereby achieving the purpose of improving the capacitance density. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 A top view of a metal-oxide-metal capacitor.

[0038] Figure 2 for Figure 1 This is a cross-sectional schematic diagram corresponding to the metal-oxide-metal capacitor EE in the prior art.

[0039] Figure 3 for Figure 1 A schematic cross-sectional view of a metal-oxide-metal capacitor EE according to an embodiment of the present invention.

[0040] Figure 4 A top view of a metal-oxide-metal capacitor provided in accordance with an embodiment of the present invention.

[0041] Figure 5 An embodiment of the present invention provides Figure 4 Schematic cross-section of FF.

[0042] Figure 6 An embodiment of the present invention provides Figure 5 The corresponding stereogram in .

[0043] Figure 7 A schematic structural diagram of a first metal layer provided in one embodiment of the present invention.

[0044] Figure 8 A schematic diagram of the structure of an interlayer dielectric layer provided in one embodiment of the present invention.

[0045] Fig. 9 A schematic diagram of the structure of a bottom groove provided in one embodiment of the present invention.

[0046] Fig.10 A schematic structural diagram of a buffer layer provided in one embodiment of the present invention.

[0047] Fig.11A schematic diagram of the structure of a top trench provided in one embodiment of the present invention.

[0048] Fig.12 An embodiment of the present invention provides Fig.11 Schematic diagram of the structure after removing the buffer layer.

[0049] Fig.13 A schematic structural diagram of a second metal layer provided in one embodiment of the present invention.

[0050] Fig.14 Another embodiment of the present invention provides Figure 4 Schematic cross-section of FF.

[0051] Fig.15 Another embodiment of the present invention provides Figure 4 Schematic cross-section of FF.

[0052] Fig.16 Another embodiment of the present invention provides Figure 4 Schematic cross-section of FF.

[0053] Fig.17 Another embodiment of the present invention provides Figure 4 Schematic cross-section of FF.

[0054] Fig.18 A schematic diagram of the structure of a metal connection provided in one embodiment of the present invention.

[0055] Fig.19 An embodiment of the present invention provides Fig.18 The corresponding stereogram.

[0056] Fig. 20 A schematic structural diagram of a metal connection provided in yet another embodiment of the present invention.

[0057] Fig.21 An embodiment of the present invention provides Fig. 20 The corresponding stereogram.

[0058] Fig. 22 An embodiment of the present invention provides Fig. 20 Schematic diagram of the structure of the bottom metal connection.

[0059] Fig.23 An embodiment of the present invention provides Fig. 22 The corresponding stereogram.

[0060] Fig.24 A schematic structural diagram of a metal connection provided in yet another embodiment of the present invention.

[0061] Fig.25A schematic diagram of the steps of a method for manufacturing a metal-oxide-metal capacitor provided by an embodiment of the present invention.

[0062] Fig.26 An embodiment of the present invention provides Fig.25 Schematic diagram of step S20 in FIG.

[0063] Fig. 27 An embodiment of the present invention provides Fig.25 Schematic diagram of step S40 in FIG.

[0064] Description of Figure Numbers

[0065] 10. Capacitor region; 110. Semiconductor substrate; 120. Bottom metal layer; 130. Interlayer dielectric layer; 140. Bottom trench; 150. Buffer layer; 160. Top trench; 170. Through hole; 180. Top metal layer; 190. Metal plug; 20. Circuit region; 30. Metal connection; 310. Edge segment; 320. Connection segment; 330. Connecting segment. DETAILED DESCRIPTION

[0066] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0067] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0068] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0069] See also Figures 1 to 25The present invention provides a metal-oxide-metal capacitor (MOM) and a manufacturing method thereof, which can be applied in the field of integrated circuit manufacturing processes, such as capacitors in complementary metal oxide semiconductor (CMOS) image sensors. In the metal-oxide-metal capacitor of the present invention, metal plugs are connected on different metal layers so that the metal plugs between two adjacent metal layers correspond to each other. The capacitance effect of the metal plugs between different metal layers is utilized to increase the effective parasitic area of ​​the metal-oxide-metal capacitor, thereby achieving the purpose of improving the capacitance density.

[0070] See also Figure 1 and Figure 3 In one embodiment of the present invention, the metal-oxide-metal capacitor may include a semiconductor substrate 110 , a bottom metal layer 120 , an interlayer dielectric layer 130 , and a top metal layer 180 .

[0071] Specifically, the semiconductor substrate 110 refers to a thin conductive layer made on a semiconductor material such as silicon or germanium, and the conductive layer may be doped or undoped. The semiconductor substrate 110 is the basis of the semiconductor device and is used to carry and support the electronic components and circuits thereon. In this embodiment, the semiconductor substrate 110 serves as a supporting substrate for the bottom metal layer 120, the interlayer dielectric layer 130, and the top metal layer 180.

[0072] Specifically, the metal layer refers to a conductive metal layer deposited on the semiconductor substrate 110 during the semiconductor and integrated circuit manufacturing process, which can be used to construct the interconnection structure inside the semiconductor device and realize the electrical connection between different components. In this embodiment, the bottom metal layer 120 and the top metal layer 180 are located on different planes. For example, the bottom metal layer 120 is arranged on the surface of the semiconductor substrate 110, an interlayer dielectric layer 130 is arranged between the bottom metal layer 120 and the top metal layer 180, and the top metal layer 180 is arranged on the surface of the interlayer dielectric layer 130. The bottom metal layer 120 and the top metal layer 180 can be used to realize the electrical connection of different components respectively. On the bottom metal layer 120 and the top metal layer 180, a metal connection 30 can be formed by a metal conductive path.

[0073] Specifically, the dielectric layer refers to a non-conductive material layer used in the semiconductor and integrated circuit manufacturing process. The dielectric layer can be used to isolate different metal layers to achieve electrical isolation. Proper selection of the material and process of the dielectric layer can meet the requirements of smaller size, lower power consumption and higher integration of semiconductor devices to ensure precise thickness control and excellent film quality. In this embodiment, the interlayer dielectric layer 130 is disposed on the surface of the bottom metal layer 120.

[0074] See also Figure 1 and Figure 3 In one embodiment of the present invention, at least one of a bottom trench 140 and a top trench 160 may be formed on the interlayer dielectric layer 130 , and metal plugs 190 are disposed in the bottom trench 140 and the top trench 160 .

[0075] Specifically, Fig.14 As shown, when only the bottom trench 140 is formed on the interlayer dielectric layer 130 , a metal plug 190 is disposed in the bottom trench 140 , and the bottom trench 140 is electrically connected to the metal connection line 30 of the bottom metal layer 120 .

[0076] Specifically, Fig.15 As shown, when only the top trench 160 is formed on the interlayer dielectric layer 130 , a metal plug 190 is disposed in the top trench 160 , and the top trench 160 is electrically connected to the metal connection line 30 of the top metal layer 180 .

[0077] Specifically, Fig.13 , Fig.16 and Fig.17 As shown, when the bottom trench 140 and the top trench 160 are formed on the interlayer dielectric layer 130, metal plugs 190 are provided in the bottom trench 140 and the top trench 160. The bottom trench 140 is connected to the metal wiring 30 of the bottom metal layer 120, that is, the metal plug 190 in the bottom trench 140 is electrically connected to the metal wiring 30 of the bottom metal layer 120, and the top trench 160 is separated from the bottom metal layer 120. The bottom trench 140 is separated from the top metal layer 180, and the top trench 160 is connected to the metal wiring 30 of the top metal layer 180, that is, the metal plug 190 in the top trench 160 is electrically connected to the metal wiring 30 of the top metal layer 180.

[0078] See also Figure 1 , Figure 3 , Figure 4 , Figure 5 and Figure 6 In one embodiment of the present invention, the metal connection line 30 of the bottom metal layer 120 corresponds to the metal connection line 30 of the top metal layer 180. The metal plug 190 connected to the metal connection line 30 of the bottom metal layer 120 corresponds to the metal plug 190 connected to the metal connection line 30 of the top metal layer 180.

[0079] Specifically, Figure 3 , Figure 5 and Figure 6As shown, the metal wiring 30 of the bottom metal layer 120 corresponds to the metal wiring 30 of the top metal layer 180, the metal wiring 30 of the bottom metal layer 120 can be used as the first electrode plate of the metal-oxide-metal capacitor, and the metal wiring 30 of the top metal layer 180 can be used as the second electrode plate of the metal wiring 30 of the top metal layer 180. Since an interlayer dielectric layer 130 is provided between the metal wiring 30 of the bottom metal layer 120 and the metal wiring 30 of the top metal layer 180, the bottom metal layer 120, the interlayer dielectric layer 130 and the top metal layer 180 together form a metal-oxide-metal capacitor.

[0080] Specifically, Figure 3 , Figure 5 and Figure 6 As shown, between two adjacent metal layers, the metal plug 190 on the metal connection line 30 of the bottom metal layer 120 corresponds to the metal plug 190 on the metal connection line 30 of the top metal layer 180. In this embodiment, the capacitance effect of the metal plug 190 between different metal layers can be used to increase the effective parasitic area of ​​the capacitor, thereby achieving the purpose of improving the capacitance density.

[0081] It is worth mentioning that Figure 1 Figure 4 As shown, the metal connection line 30 of the bottom metal layer 120 corresponds to the metal connection line 30 of the top metal layer 180, which may mean that the metal connection line 30 of the bottom metal layer 120 and the metal connection line 30 of the top metal layer 180 are opposite to each other in position, or there is a certain offset in position.

[0082] like Figure 3 , Figure 5 and Figure 6 As shown, the metal plug 190 connected to the metal connection 30 of the bottom metal layer 120 corresponds to the metal plug 190 connected to the metal connection 30 of the top metal layer 180, which may mean that the metal plug 190 connected to the metal connection 30 of the bottom metal layer 120 and the metal plug 190 connected to the metal connection 30 of the top metal layer 180 are opposite to each other in position, or there is a certain offset in position.

[0083] For example, the metal plugs 190 connected to the metal wires 30 of the bottom metal layer 120 and the metal plugs 190 connected to the metal wires 30 of the top metal layer 180 are alternately distributed, and the top height of the metal plugs 190 corresponding to the bottom metal layer 120 is higher than the bottom height of the metal plugs 190 corresponding to the top metal layer 180. In other embodiments, the top of the metal plugs 190 corresponding to the bottom metal layer 120 may be opposite to the bottom of the metal plugs 190 corresponding to the top metal layer 180.

[0084] See also Figure 1 , Figure 2 and Figure 3 ,exist Figure 2 In the prior art, different metal lines 30 are alternately distributed on the same metal layer to increase the effective parasitic area of ​​the capacitor, so as to achieve the purpose of improving the capacitance density. However, in the prior art metal-oxide-metal capacitor, the effective parasitic area of ​​the capacitor on different metal layers is not considered, so the degree of improvement of the capacitance density has a certain upper limit. Figure 3 In the embodiment, between two adjacent metal layers, the capacitance effect of the metal plug 190 between different metal layers can be used to increase the effective parasitic area of ​​the capacitor, thereby achieving the purpose of improving the capacitance density.

[0085] Above Figure 1 , Figure 3 , Figure 4 , Figure 5 and Figure 6 The corresponding metal-oxide-metal capacitor can be Figures 7 to 13 The device is processed by a complementary metal oxide semiconductor (CMOS) process and may include a capacitor region 10 and a circuit region 20 .

[0086] See also Figure 7 In one embodiment of the present invention, in the capacitor region 10 and the circuit region 20 , an underlying metal layer 120 may be formed on the surface of the semiconductor substrate 110 .

[0087] See also Figure 8 In one embodiment of the present invention, after forming the bottom metal layer 120 on the surface of the semiconductor substrate 110 , an interlayer dielectric layer 130 may be formed on the surface of the bottom metal layer 120 in the capacitor region 10 and the circuit region 20 .

[0088] See also Fig. 9 In one embodiment of the present invention, after forming an interlayer dielectric layer 130 on the surface of the bottom metal layer 120 by chemical vapor deposition (CVD), a photoresist (PR) can be formed on the surface of the interlayer dielectric layer 130 in the capacitor region 10, and the photoresist is subjected to photolithography and development. Then, the interlayer dielectric layer 130 is etched to form a bottom trench 140 on the interlayer dielectric layer 130, and a filling material is deposited inside the bottom trench 140 to form a metal plug 190.

[0089] First, a mask plate can be set above the photoresist on the surface of the interlayer dielectric layer 130, and there is a gap between the mask plate and the photoresist. The photoresist is subjected to photolithography and development processing, so that a portion of the photoresist is retained on the surface of the interlayer dielectric layer 130. Secondly, the interlayer dielectric layer 130 is etched. Since the remaining portion of the photoresist on the surface of the interlayer dielectric layer 130 will not be etched, a plurality of bottom grooves 140 can be formed on the interlayer dielectric layer 130, and the bottom grooves 140 can be connected to the upper surface of the bottom metal layer 120.

[0090] Then, the remaining part of the photoresist on the surface of the interlayer dielectric layer 130 can be removed, and a filling material layer can be formed on the surface of the bottom trench 140 and the interlayer dielectric layer 130 by chemical vapor deposition (CVD) again. The filling material layer can be tungsten, and the filling material can fill the bottom trench 140 and cover the surface of the interlayer dielectric layer 130. Afterwards, a chemical mechanical polishing (CMP) process is used to polish the filling material on the surface of the interlayer dielectric layer 130. When the polishing contacts the surface of the interlayer dielectric layer 130, the polishing process is stopped, so that the metal plug 190 (not shown in the figure) can be retained inside the bottom trench 140.

[0091] See also Fig.10 In one embodiment of the present invention, after a bottom trench 140 is formed on the interlayer dielectric layer 130 and a metal plug 190 is formed inside the bottom trench 140, a buffer layer 150 can be formed on the interlayer dielectric layer 130 and the surface of the metal plug 190 in the bottom trench 140 in the capacitor region 10 and the circuit region 20 by chemical vapor deposition (CVD).

[0092] Then, a photoresist may be formed on the surface of the buffer layer 150, and the photoresist of the circuit region 20 may be removed by photolithography and development processes, and the buffer layer 150 of the circuit region 20 may be etched and removed. The photoresist of the capacitor region 10 may be removed, and the buffer layer 150 on the surface of the interlayer dielectric layer 130 and the metal plug 190 of the bottom trench 140 may be retained in the capacitor region 10.

[0093] See also Fig.11 In one embodiment of the present invention, after retaining the buffer layer 150 on the surface of the interlayer dielectric layer 130 in the capacitor region 10, Fig. 9In a similar process flow, in the capacitor region 10, a photoresist (PR, PhotoResist) can be formed on the surface of the buffer layer 150, and the photoresist is subjected to photolithography and development, and a region where the top groove 160 needs to be etched can be formed. Then, the buffer layer 150, the interlayer dielectric layer 130 of the capacitor region 10, and the interlayer dielectric layer 130 of the circuit region 20 are etched. The top groove 160 can be formed on the interlayer dielectric layer 130 of the capacitor region 10, and the through hole 170 can be formed on the interlayer dielectric layer 130 of the circuit region 20. Afterwards, a filling material is deposited inside the top groove 160 and the through hole 170 to form a metal plug 190.

[0094] First, a mask can be set above the photoresist on the surface of the buffer layer 150, and there is a gap between the mask and the photoresist. The photoresist is subjected to photolithography and development treatment so that part of the photoresist is retained on the surface of the buffer layer 150, and the gap between the photoresists can be defined as the area where the top groove 160 needs to be etched. Secondly, in the capacitor area 10, along the area where the top groove 160 needs to be etched, the buffer layer 150 and the interlayer dielectric layer 130 are etched. In the circuit area 20, the interlayer dielectric layer 130 is etched. In the capacitor area 10 and the circuit area 20, the above-mentioned etching process is carried out simultaneously. Since the capacitor area 10 needs to etch the buffer layer 150 and the interlayer dielectric layer 130 successively, the circuit area 20 can directly etch the interlayer dielectric layer 130. Therefore, on the interlayer dielectric layer 130, the depth of the top groove 160 is smaller than the depth of the through hole 170. By adjusting the thickness of the buffer layer 150, it can be ensured that the bottom of the top groove 160 will not be connected to the surface of the bottom metal layer 120, and the bottom of the through hole 170 is connected to the surface of the bottom metal layer 120.

[0095] Then, the remaining part of the photoresist on the surface of the buffer layer 150 can be removed, and a filling material layer can be formed on the surface of the top groove 160, the buffer layer 150 and the interlayer dielectric layer 130 by chemical vapor deposition (CVD) again. The filling material can fill the top groove 160 and the through hole 170, and cover the surface of the interlayer dielectric layer 130 and the buffer layer 150. Secondly, the filling material on the surface of the interlayer dielectric layer 130 and the buffer layer 150 is polished using a chemical mechanical polishing (CMP) process. When the polishing contacts the surface of the interlayer dielectric layer 130 and the buffer layer 150, the polishing process is stopped, so that the metal plug 190 (not shown in the figure) can be retained inside the top groove 160 and the through hole 170.

[0096] See also Fig.12In one embodiment of the present invention, after forming the top trench 160 on the interlayer dielectric layer 130 and forming the metal plug 190 inside the top trench 160, the remaining buffer layer 150 on the surface of the interlayer dielectric layer 130 can be removed by a wet etching process. Afterwards, the interlayer dielectric layer 130 can be formed again on the surface of the interlayer dielectric layer 130 and the top trench 160 by chemical vapor deposition (CVD), and the interlayer dielectric layer 130 can be polished by chemical mechanical polishing (CMP), and the polishing process is stopped when the metal plug 190 of the top trench 160 is polished. The bottom of the bottom trench 140 is connected to the bottom metal layer 120, and the top of the bottom trench 140 is separated by the interlayer dielectric layer 130. The bottom of the top trench 160 is separated from the bottom metal layer 120 by the interlayer dielectric layer 130, and the top of the top trench 160 is connected to the upper surface of the interlayer dielectric layer 130.

[0097] See also Fig.13 In one embodiment of the present invention, after removing the remaining buffer layer 150 on the surface of the interlayer dielectric layer 130 , a top metal layer 180 may be formed on the surface of the interlayer dielectric layer 130 .

[0098] Specifically, the bottom of the bottom trench 140 is connected to the bottom metal layer 120, and the top of the bottom trench 140 is separated from the top metal layer 180 by the interlayer dielectric layer 130. The bottom of the top trench 160 is separated from the bottom metal layer 120 by the interlayer dielectric layer 130, and the top of the top trench 160 is connected to the top metal layer 180.

[0099] It can be seen from this that Figures 7 to 13 As shown in the process technology of the metal-oxide-metal capacitor, between two adjacent metal layers, the metal plug 190 corresponding to the bottom metal layer 120 corresponds to the metal plug 190 corresponding to the top metal layer 180, and the capacitance effect of the metal plug 190 between different metal layers can be used to increase the effective parasitic area of ​​the capacitor, thereby achieving the purpose of improving the capacitance density.

[0100] See also Fig.13 and Fig.14 As shown, in one embodiment of the present invention, Fig.13 Compared with the metal-oxide-metal capacitor, Fig.14 In the metal-oxide-metal capacitor, only a bottom trench 140 is formed on the interlayer dielectric layer 130 , and no top trench 160 is formed. A metal plug 190 is disposed in the bottom trench 140 .

[0101] Specifically, the bottom of the bottom trench 140 is connected to the bottom metal layer 120, and the top of the bottom trench 140 is separated from the top metal layer 180 by the interlayer dielectric layer 130. By utilizing the capacitance effect of the metal plug 190 between different metal layers, the effective parasitic area of ​​the capacitor can be increased, thereby achieving the purpose of improving the capacitance density.

[0102] See also Fig.13 and Fig.15 As shown, in one embodiment of the present invention, Fig.13 Compared with the metal-oxide-metal capacitor, Fig.15 In the metal-oxide-metal capacitor, only a top trench 160 is formed on the interlayer dielectric layer 130 , and the bottom trench 140 is not formed. A metal plug 190 is disposed in the top trench 160 .

[0103] Specifically, the bottom of the top trench 160 is separated from the bottom metal layer 120 by the interlayer dielectric layer 130, and the top of the top trench 160 is connected to the top metal layer 180. By utilizing the capacitance effect of the metal plug 190 between different metal layers, the effective parasitic area of ​​the capacitor can be increased, thereby achieving the purpose of improving the capacitance density.

[0104] See also Fig.13 and Fig.16 As shown, in one embodiment of the present invention, Fig.13 Compared with the metal-oxide-metal capacitor, Fig.16 In the metal-oxide-metal capacitor, a bottom trench 140 and a top trench 160 may be formed on the interlayer dielectric layer 130 .

[0105] Specifically, the buffer layer 150 on the surface of the interlayer dielectric layer 130 is retained, the top of the bottom trench 140 is separated from the top metal layer 180 by the buffer layer 150 , and the bottom of the bottom trench 140 is connected to the bottom metal layer 120 .

[0106] See also Fig.13 and Fig.17 As shown, in one embodiment of the present invention, Fig.13 Compared with the metal-oxide-metal capacitor, Fig.17 In the metal-oxide-metal capacitor, the bottom of the interlayer dielectric layer 130 forms a bottom buffer layer 150 , and the top of the interlayer dielectric layer 130 forms a top buffer layer 150 .

[0107] Specifically, the top of the bottom trench 140 is separated from the top metal layer 180 by the top buffer layer 150, the bottom of the bottom trench 140 is connected to the bottom buffer layer 150, and the bottom of the bottom trench 140 is connected to the bottom metal layer 120. The bottom of the top trench 160 is separated from the bottom metal layer 120 by the bottom buffer layer 150, the top of the top trench 160 is connected to the top buffer layer 150, and the top of the top trench 160 is connected to the top metal layer 180.

[0108] See also Fig.18 and Fig. 20 As shown, in one embodiment of the present invention, the metal wiring 30 of the bottom metal layer 120 can be divided into a first type of metal wiring 30 and a second type of metal wiring 30, and the first type of metal wiring 30 and the second type of metal wiring 30 are interlaced in a finger-like manner. The metal wiring 30 of the top metal layer 180 can be divided into a first type of metal wiring 30 and a second type of metal wiring 30, and the first type of metal wiring 30 and the second type of metal wiring 30 are interlaced in a finger-like manner. The first type of metal wiring 30 of the bottom metal layer 120 and the first type of metal wiring 30 of the top metal layer 180 are located on the same side and are electrically connected to each other, and the second type of metal wiring 30 of the bottom metal layer 120 and the second type of metal wiring 30 of the top metal layer 180 are located on the same side and are electrically connected to each other.

[0109] Specifically, Fig.19 Only the schematic diagram of the structure of the bottom metal layer 120 is given. Fig.21 A schematic diagram of the structure of the bottom metal layer 120 and the top metal layer 180 is given. Fig.19 As shown, on the bottom metal layer 120, the metal wiring 30 of the bottom metal layer 120 can be divided into two types of metal wiring 30, for example, the metal wiring 30 on one side is recorded as the first type of metal wiring 30, and the metal wiring corresponding to the first type of metal wiring 30 is recorded as the second type of metal wiring 30. The first type of metal wiring 30 and the second type of metal wiring 30 are interlaced in a finger-like manner, and the finger-like structure of the same metal layer is used to construct a capacitor.

[0110] Specifically, Fig.21 As shown, on the top metal layer 180, the metal wiring 30 of the top metal layer 180 can be divided into two types of metal wiring 30, for example, the metal wiring 30 on one side is recorded as the first type of metal wiring 30, and the metal wiring corresponding to the first type of metal wiring 30 is recorded as the second type of metal wiring 30. The first type of metal wiring 30 and the second type of metal wiring 30 are interlaced in a finger-like manner, and the capacitance effect of the finger structure of the same metal layer is used to generate parasitic capacitance.

[0111] Specifically, Fig.21As shown, the first type of metal wiring 30 of the bottom metal layer 120 and the first type of metal wiring 30 of the top metal layer 180 are located on the same side and are electrically connected to each other. The second type of metal wiring 30 of the bottom metal layer 120 and the second type of metal wiring 30 of the top metal layer 180 are located on the same side and are electrically connected to each other. By electrically connecting the metal wirings located on the same side of different metal layers, on the basis that the capacitance effect of the finger structure of the same metal layer can generate parasitic capacitance, the metal plugs 190 between different metal layers also form a finger structure, and also generate corresponding parasitic capacitance, so that the capacitance density can be doubled.

[0112] See also Fig.21 and Fig.24 In one embodiment of the present invention, the first type of metal connection 30 of the bottom metal layer 120 corresponds to the second type of metal connection 30 of the top metal layer 180, and the second type of metal connection of the bottom metal layer 120 corresponds to the first type of metal connection 30 of the top metal layer 180.

[0113] Specifically, the first type of metal wiring 30 of the bottom metal layer 120 corresponds to the second type of metal wiring 30 of the top metal layer 180, which may mean that the first type of metal wiring 30 of the bottom metal layer 120 and the second type of metal wiring 30 of the top metal layer 180 are opposite to each other in position, or there is a certain offset in position. The second type of metal wiring of the bottom metal layer 120 corresponds to the first type of metal wiring 30 of the top metal layer 180, which may mean that the second type of metal wiring 30 of the bottom metal layer 120 and the first type of metal wiring 30 of the top metal layer 180 are opposite to each other in position, or there is a certain offset in position.

[0114] See also Fig.18 , Fig. 20 , Fig.21 and Fig.24 In one embodiment of the present invention, the metal connection line 30 includes an edge segment 310, a connection segment 320 and a connection segment 330. The number of edge segments 310 can be one, the number of connection segments 320 can be multiple, and multiple connection segments 320 can be electrically connected to the edge segment 310. Multiple connection segments 320 are arranged in parallel, and there is a gap between two adjacent connection segments 320. The first type of metal connection line 30 of the bottom metal layer 120 is electrically connected to the first type of metal connection line 30 of the top metal layer 180 through the edge segment 310, and the second type of metal connection line 30 of the bottom metal layer 120 is electrically connected to the second type of metal connection line 30 of the top metal layer 180 through the edge segment 310.

[0115] Specifically, as shown in the figure Fig. 20 , Fig.21 and Fig.24As shown, the first type of metal connection line 30 of the bottom metal layer 120 and the first type of metal connection line 30 of the top metal layer 180 are located on the same side and can be electrically connected to each other through the connection segment 330. The second type of metal connection line 30 of the bottom metal layer 120 and the second type of metal connection line 30 of the top metal layer 180 are located on the same side and can be electrically connected to each other through the connection segment 330. Fig.21 As shown, in the present embodiment, although only the bottom metal layer 120 and the top metal layer 180 are specified, for more than two metal layers, the number of the bottom metal layer 120 and the top metal layer 180 can be set to at least one respectively, and according to the process technology described above, the metal-oxide-metal capacitors corresponding to the more than two metal layers can be obtained.

[0116] See also Fig.18 , Fig. 20 , Fig.21 and Fig.24 In one embodiment of the present invention, in the top metal layer 120 or the bottom metal layer 180 , the line segments 320 of the first type of metal lines 300 and the line segments 320 of the second type of metal lines 30 are alternately distributed.

[0117] See also Fig.25 The present invention proposes a method for manufacturing a metal-oxide-metal capacitor, which may include the following steps.

[0118] Step S10: providing a semiconductor substrate.

[0119] Step S20: forming a bottom metal layer on the surface of the semiconductor substrate, and forming metal wiring on the bottom metal layer.

[0120] Step S30, forming an interlayer dielectric layer on the surface of the bottom metal layer, forming at least one of a bottom trench and a top trench on the interlayer dielectric layer, and arranging metal plugs in the bottom trench and the top trench, wherein the bottom trench is connected to the metal wiring of the bottom metal layer, and / or the top trench is separated from the bottom metal layer.

[0121] Step S40, forming a top metal layer on the surface of the interlayer dielectric layer, and forming metal wiring on the top metal layer, wherein the bottom trench is separated from the top metal layer, and / or the top trench is connected to the metal wiring of the top metal layer.

[0122] Step S50: Match the metal wiring of the top metal layer with the metal wiring of the bottom metal layer.

[0123] The following is a detailed description through specific embodiments.

[0124] Step S10: providing a semiconductor substrate.

[0125] In one embodiment of the present invention, Figure 7 As shown, the semiconductor substrate 110 refers to a thin conductive layer made on a semiconductor material such as silicon or germanium, and the conductive layer may be doped or undoped. The semiconductor substrate 110 is the basis of the semiconductor device and is used to carry and support the electronic components and circuits thereon.

[0126] Step S20: forming a bottom metal layer on the surface of the semiconductor substrate, and forming metal wiring on the bottom metal layer.

[0127] In one embodiment of the present invention, Figure 7 As shown, the metal layer refers to a conductive metal layer deposited on a semiconductor substrate 110 during the semiconductor and integrated circuit manufacturing process, which can be used to construct an interconnection structure inside a semiconductor device and realize electrical connections between different components. The bottom metal layer 120 is disposed on the surface of the semiconductor substrate 110, and on the bottom metal layer 120, a metal connection 30 can be formed by a metal conductive path.

[0128] Step S30, forming an interlayer dielectric layer on the surface of the bottom metal layer, forming at least one of a bottom trench and a top trench on the interlayer dielectric layer, and arranging metal plugs in the bottom trench and the top trench, wherein the bottom trench is connected to the metal wiring of the bottom metal layer, and / or the top trench is separated from the bottom metal layer.

[0129] In one embodiment of the present invention, Figure 8 As shown, the dielectric layer refers to a non-conductive material layer used in the semiconductor and integrated circuit manufacturing process. The dielectric layer can be used to isolate different metal layers to achieve electrical isolation. Proper selection of the material and process of the dielectric layer can meet the requirements of smaller size, lower power consumption and higher integration of semiconductor devices to ensure precise thickness control and excellent film quality. In this embodiment, the interlayer dielectric layer 130 is disposed on the surface of the bottom metal layer 120.

[0130] Specifically, Fig.14 As shown, when only a bottom trench 140 is formed on the interlayer dielectric layer 130 , a metal plug 190 is disposed in the bottom trench 140 , the bottom of the bottom trench 140 is connected to the metal connection 30 of the underlying metal layer 120 , and the top of the bottom trench 140 is blocked by the interlayer dielectric layer 130 .

[0131] Specifically, Fig.15 As shown, when only the top trench 160 is formed on the interlayer dielectric layer 130 , a metal plug 190 is disposed in the top trench 160 , the top of the top trench 160 is connected to the upper surface of the interlayer dielectric layer 130 , and the bottom of the top trench 160 is blocked by the interlayer dielectric layer 130 .

[0132] Specifically, Fig.13 , Fig.16 and Fig.17 As shown, when the bottom trench 140 and the top trench 160 are formed on the interlayer dielectric layer 130, metal plugs 190 are provided in the bottom trench 140 and the top trench 160. The bottom trench 140 is connected to the metal connection line 30 of the bottom metal layer 120, and the top trench 160 is separated from the bottom metal layer 120 by the interlayer dielectric layer 130. The top of the bottom trench 140 is blocked by the interlayer dielectric layer 130, and the top of the top trench 160 is connected to the upper surface of the interlayer dielectric layer 130.

[0133] Step S40, forming a top metal layer on the surface of the interlayer dielectric layer, and forming a metal connection on the top metal layer, wherein the bottom trench is separated from the top metal layer, and / or the top trench is connected to the metal connection of the top metal layer.

[0134] In one embodiment of the present invention, Fig.14 As shown, when only a bottom trench 140 is formed on the interlayer dielectric layer 130 , a metal plug 190 is disposed in the bottom trench 140 , the bottom trench 140 is connected to the metal connection 30 of the bottom metal layer 120 , and the top of the bottom trench 140 and the top metal layer 180 are blocked by the interlayer dielectric layer 130 .

[0135] Specifically, Fig.15 As shown, when only a top trench 160 is formed on the interlayer dielectric layer 130 , a metal plug 190 is disposed in the top trench 160 , the top trench 160 is connected to the metal connection 30 of the top metal layer 180 , and the top trench 160 and the bottom metal layer 120 are separated by the interlayer dielectric layer 130 .

[0136] Specifically, Fig.13 , Fig.16 and Fig.17 As shown, when the bottom trench 140 and the top trench 160 are formed on the interlayer dielectric layer 130, metal plugs 190 are provided in the bottom trench 140 and the top trench 160. The bottom trench 140 is connected to the metal wiring 30 of the bottom metal layer 120, and the top trench 160 is separated from the bottom metal layer 120 by the interlayer dielectric layer 130. The bottom trench 140 is separated from the top metal layer 180 by the interlayer dielectric layer 130, and the top trench 160 is connected to the metal wiring 30 of the top metal layer 180.

[0137] Step S50: Match the metal wiring of the top metal layer with the metal wiring of the bottom metal layer.

[0138] In one embodiment of the present invention, the metal connection line 30 of the bottom metal layer 120 corresponds to the metal connection line 30 of the top metal layer 180, and the metal connection line 30 of the bottom metal layer 120 can be used as the first electrode plate of the metal-oxide-metal capacitor, and the metal connection line 30 of the top metal layer 180 can be used as the second electrode plate of the metal connection line 30 of the top metal layer 180. Since an interlayer dielectric layer 130 is provided between the metal connection line 30 of the bottom metal layer 120 and the metal connection line 30 of the top metal layer 180, the bottom metal layer 120, the interlayer dielectric layer 130 and the top metal layer 180 form a metal-oxide-metal capacitor together. Between two adjacent metal layers, the capacitance effect of the metal plug 190 between different metal layers can be used to increase the effective parasitic area of ​​the capacitor, thereby achieving the purpose of improving the capacitance density.

[0139] See also Fig.26 In one embodiment of the present invention, step S20 may include step S210 and step S220. Step S210 may be represented by dividing the metal wiring 30 on the bottom metal layer 120 into a first type of metal wiring 30 and a second type of metal wiring 30. Step S220 may be represented by staggering the first type of metal wiring 30 and the second type of metal wiring 30 at finger-shaped intervals.

[0140] like Fig.19 As shown, on the bottom metal layer 120, the metal wiring 30 of the bottom metal layer 120 can be divided into two types of metal wiring 30, and the metal wiring 30 on one side can be recorded as the first type of metal wiring 30, and the metal wiring corresponding to the first type of metal wiring 30 can be recorded as the second type of metal wiring 30. The first type of metal wiring 30 and the second type of metal wiring 30 are interlaced in a finger-like manner, and the finger-like structure of the same metal layer is used to construct a capacitor.

[0141] See also Fig. 27 In one embodiment of the present invention, step S40 may include step S410 and step S420. Step S410 may be represented as dividing the metal wiring 30 on the top metal layer 180 into a first type of metal wiring 30 and a second type of metal wiring 30, and staggering the first type of metal wiring 30 and the second type of metal wiring 30 according to the interdigital spacing.

[0142] Specifically, Fig.21 As shown, on the top metal layer 180, the metal wiring 30 of the top metal layer 180 can be divided into two types of metal wiring 30, and the metal wiring 30 on one side can be recorded as the first type of metal wiring 30, and the metal wiring corresponding to the first type of metal wiring 30 can be recorded as the second type of metal wiring 30. The first type of metal wiring 30 and the second type of metal wiring 30 are interlaced in a finger-like manner, and the capacitance effect of the finger structure of the same metal layer is used to generate parasitic capacitance.

[0143] Step S420 can be represented as arranging the first type of metal connection 30 of the top metal layer 180 and the first type of metal connection 30 of the bottom metal layer 120 on the same side and electrically connecting them, and arranging the second type of metal connection 30 of the top metal layer 180 and the second type of metal connection 30 of the bottom metal layer 120 on the same side and electrically connecting them.

[0144] Specifically, Fig.21 As shown, the first type of metal wiring 30 of the bottom metal layer 120 and the first type of metal wiring 30 of the top metal layer 180 are located on the same side and are electrically connected to each other. The second type of metal wiring 30 of the bottom metal layer 120 and the second type of metal wiring 30 of the top metal layer 180 are located on the same side and are electrically connected to each other. By electrically connecting the metal wirings located on the same side of different metal layers, on the basis that the capacitance effect of the finger structure of the same metal layer can generate parasitic capacitance, the metal plugs 190 between different metal layers also form a finger structure, and also generate corresponding parasitic capacitance, so that the capacitance density can be doubled.

[0145] In summary, the present invention proposes a metal-oxide-metal capacitor and a manufacturing method thereof, which utilizes the capacitance effect of a metal plug between two adjacent metal layers to increase the effective parasitic area of ​​the capacitor, thereby achieving the purpose of improving the capacitance density.

[0146] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the art without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention. As used in the description herein and in the following entire claims, unless otherwise specified, "one", and "the" include plural references. Similarly, as used in the description herein and in the following entire claims, unless otherwise specified, the meaning of "in..." includes "in..." and "on...".

Claims

1. A metal-oxide-metal capacitor, characterized in that: include: Semiconductor substrate; A bottom metal layer, disposed on the surface of the semiconductor substrate, the bottom metal layer comprising metal wiring; an interlayer dielectric layer, disposed on the surface of the bottom metal layer, wherein at least one of a bottom trench and a top trench is formed on the interlayer dielectric layer, wherein metal plugs are disposed in the bottom trench and the top trench, wherein the bottom trench is connected to a metal connection line of the bottom metal layer, and / or the top trench is separated from the bottom metal layer; and A top metal layer, disposed on the surface of the interlayer dielectric layer, the top metal layer comprising metal wiring, wherein the bottom trench is separated from the top metal layer, and / or the top trench is connected to the metal wiring of the top metal layer; The metal wiring of the bottom metal layer corresponds to the metal wiring of the top metal layer.

2. The metal-oxide-metal capacitor according to claim 1, characterized in that: The metal wirings of the bottom metal layer are divided into a first type of metal wiring and a second type of metal wiring, and the first type of metal wiring and the second type of metal wiring are interlaced in a finger-like manner; The metal connections of the top metal layer are divided into a first type of metal connections and a second type of metal connections, and the first type of metal connections and the second type of metal connections are interlaced in a finger-like manner; The first type of metal connection line of the bottom metal layer and the first type of metal connection line of the top metal layer are located on the same side and electrically connected, and the second type of metal connection line of the bottom metal layer and the second type of metal connection line of the top metal layer are located on the same side and electrically connected.

3. The metal-oxide-metal capacitor according to claim 2, characterized in that: The first type of metal wiring of the bottom metal layer corresponds to the second type of metal wiring of the top metal layer, and the second type of metal wiring of the bottom metal layer corresponds to the first type of metal wiring of the top metal layer.

4. The metal-oxide-metal capacitor according to claim 1, characterized in that: Also includes: A first buffer layer is arranged on the surface of the interlayer dielectric layer, the first buffer layer separates the bottom trench from the top metal layer, the top trench penetrates the first buffer layer, and the top trench is connected to the top metal layer.

5. The metal-oxide-metal capacitor according to claim 4, characterized in that: Also includes: The second buffer layer is arranged on the surface of the bottom metal layer, the second buffer layer separates the top groove from the bottom metal layer, the bottom groove penetrates the buffer layer, and the bottom groove is connected with the bottom metal layer.

6. The metal-oxide-metal capacitor according to claim 2 or 3, characterized in that: The metal connection includes: Edge segment; A plurality of line segments are electrically connected to the edge segments, the plurality of line segments are arranged in parallel, and there is a gap between two adjacent line segments; Wherein, the metal connection line of the bottom metal layer and the metal connection line of the top metal layer are electrically connected through the edge segment.

7. The metal-oxide-metal capacitor according to claim 6, characterized in that: In the top metal layer or the bottom metal layer, the line segments of the first type of metal lines and the line segments of the second type of metal lines are alternately distributed.

8. A method for manufacturing a metal-oxide-metal capacitor, characterized in that: include: Providing a semiconductor substrate; forming a bottom metal layer on the surface of the semiconductor substrate, and forming metal wiring on the bottom metal layer; An interlayer dielectric layer is formed on the surface of the bottom metal layer, at least one of a bottom trench and a top trench is formed on the interlayer dielectric layer, and metal plugs are arranged in the bottom trench and the top trench, wherein the bottom trench is connected to the metal wiring of the bottom metal layer, and / or the top trench is separated from the bottom metal layer; Forming a top metal layer on the surface of the interlayer dielectric layer, and forming a metal connection line on the top metal layer, wherein the bottom trench is separated from the top metal layer, and / or the top trench is connected to the metal connection line of the top metal layer; The metal wiring of the top metal layer is matched with the metal wiring of the bottom metal layer.

9. The method for manufacturing a metal-oxide-metal capacitor according to claim 8, characterized in that: The step of forming metal wiring on the bottom metal layer comprises: Dividing the metal connections on the bottom metal layer into first-type metal connections and second-type metal connections; The first type of metal connecting wires and the second type of metal connecting wires are staggered and distributed at finger-shaped intervals.

10. The method for manufacturing a metal-oxide-metal capacitor according to claim 9, characterized in that: The step of forming metal wiring on the top metal layer comprises: Divide the metal connections on the top metal layer into first-type metal connections and second-type metal connections, and distribute the first-type metal connections and the second-type metal connections alternately at finger-shaped intervals; The first type of metal connection line of the top metal layer and the first type of metal connection line of the bottom metal layer are arranged on the same side and electrically connected, and the second type of metal connection line of the top metal layer and the second type of metal connection line of the bottom metal layer are arranged on the same side and electrically connected.

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