Manufacturing method of silicon capacitor

Abstract

The invention belongs to the field of design and manufacturing of semiconductors / integrated circuits, and particularly relates to a manufacturing method of a silicon capacitor. Comprising the following steps: forming an oxide layer on a silicon substrate, photoetching and etching to form a 1 # capacitor groove, generating a field oxide layer in the groove, filling doped polycrystalline silicon, processing the surface, etching a 2 # capacitor groove, depositing a multilayer film in the groove, processing the multilayer film at two ends of the groove, depositing silicon oxide, finally connecting an upper polar plate and a lower polar plate through photoetching and metal deposition, removing redundant substances and detecting. According to the method, the structure size and performance can be accurately controlled, the electrical performance, reliability and stability of the silicon capacitor in the field of integrated circuits and the like are improved, and the circuit integration degree is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor / integrated circuit design and manufacturing, and in particular relates to a method for manufacturing a silicon capacitor. Background Art

[0002] As a passive electronic component based on silicon materials, silicon capacitors play important functions in modern electronic systems, such as signal coupling, filtering, and energy storage. In integrated circuits, they play a key role in stabilizing power supply voltage, reducing noise interference, and improving signal integrity. For example, in high-speed digital circuits, silicon capacitors can be used as bypass capacitors to provide instantaneous current requirements for logic circuits within the chip, ensuring the accuracy and stability of signal transmission. In analog circuits, such as RF front-end circuits, silicon capacitors are used in matching networks, resonant circuits, etc., which directly affect the frequency response and gain performance of the circuit.

[0003] At present, in order to obtain silicon capacitors with large electrode surface area and capacitance density, trench process is often used for preparation, that is, a layer of polysilicon electrode, a layer of dielectric layer, and a layer of metal layer electrode are deposited on the substrate groove to form a silicon capacitor. However, when the trench is deep, polysilicon deposition cannot form a very uniform electrode layer, and the deposited polysilicon layer will occupy part of the space, reducing the dielectric layer space. If the dielectric layer space is to be increased, the trench must be enlarged, which will lead to an increase in chip area. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention proposes a method for manufacturing a silicon capacitor, which can effectively improve the performance of the capacitor, such as the quality factor Q value.

[0005] The technical solution of the present invention is as follows:

[0006] A method for manufacturing a silicon capacitor, comprising:

[0007] S100: forming an oxide layer on the surface of the silicon substrate by thermal oxidation or chemical vapor deposition process, and then etching a No. 1 capacitor groove by photolithography and dry etching process;

[0008] S200: generating a field oxide layer in the 1# capacitor groove;

[0009] S300: filling the 1# capacitor groove with doped polysilicon and sealing it through a deposition process, and then removing the surface doped silicon and oxide layer through an etching process;

[0010] S400: etching a plurality of 2# capacitor grooves on the doped polysilicon by photolithography and dry etching processes;

[0011] S500: Ti / TiN / dielectric layer / TiN / Ti / doped polysilicon are deposited in the 2# capacitor groove respectively;

[0012] S600: etching away the multilayer film at both ends of the overall 2# capacitor slot by photolithography and etching processes, wherein one end of the overall 2# capacitor slot is etched to expose the lower plate polysilicon, and then a layer of silicon oxide is deposited by a deposition process;

[0013] S700: Through the back-end process, the upper and lower plates, that is, the upper and lower layers of doped polysilicon are connected through metal wires.

[0014] Furthermore, in the S100, the oxide layer is formed by thermal oxidation or chemical vapor deposition process, so that the oxide layer thickness reaches 100-10000A.

[0015] Furthermore, in the above S200, the silicon substrate after etching the No. 1 capacitor groove is cleaned before the field oxide layer is deposited; the deposition is carried out by a thermal oxidation process or a chemical vapor deposition process, so that the field oxide layer has a thickness of 100-5000A.

[0016] Furthermore, in the step S300, the doped polysilicon is deposited to fill the capacitor slot 1# using a chemical vapor deposition process, with silane and a doping source gas as raw materials, and the silicon source gas and the doping source gas are decomposed and co-deposited to form doped polysilicon, with a doping concentration of 1E11-1E20cm -3 .

[0017] Furthermore, in S400, the depth-to-width ratio of the 2# capacitor groove is 2:1-50:1.

[0018] Furthermore, in S500, Ti deposition is performed by a sputtering deposition process in physical vapor deposition;

[0019] TiN deposition uses a reactive sputtering process, where the titanium target reacts with nitrogen to deposit a TiN layer on the surface of the metal silicide;

[0020] The dielectric layer deposition process is selected according to the dielectric material. SiO2 is deposited using the PECVD process with silane and oxygen as raw materials.

[0021] TiN / Ti / doped polysilicon upper plate deposition, first reactive sputtering TiN layer, then sputtering deposition of Ti layer, and finally chemical vapor deposition of doped polysilicon upper plate.

[0022] Furthermore, in the S600, when etching the multilayer film at both ends of the 2# capacitor groove, the silicon substrate is placed in a reactive ion etching device, an etching gas combination is selected according to the material characteristics, and the resist is removed after etching; the silicon substrate is cleaned before silicon oxide deposition, and then a PECVD process is used to etch the exposed surface at both ends of the groove using silane and oxygen as raw materials to deposit silicon oxide.

[0023] Furthermore, in the above S700, the metal wires are connected to the upper and lower electrodes by sputtering deposition or electron beam evaporation deposition process, and inert gas is introduced under vacuum to deposit metal atoms in the photoresist pattern definition area to form metal wires.

[0024] The beneficial effects of the present invention are as follows: 1. The present invention forms a large groove on a silicon substrate and fills it with doped polysilicon, directly forms a groove on the doped polysilicon and uses the doped polysilicon as a lower plate electrode. Compared with the traditional trench-type silicon capacitor that deposits polysilicon on the silicon substrate groove as a lower plate electrode, the present invention can reduce the space occupied by the electrode, increase the unit groove density, and have a smaller chip area at the same groove density.

[0025] 2. The bottom plate silicon electrode formed by the present invention will not affect the uniformity of its thickness no matter how deep the groove is or how small the groove spacing is, thus ensuring the stable performance of the silicon capacitor.

[0026] 3. Adding a Ti / TiN layer between the upper and lower plates and the dielectric layer can not only block the diffusion of some oxygen in the dielectric layer from affecting performance, but also form an ohmic contact, reduce resistance, and improve the quality factor Q value of the capacitor. On the other hand, it can also prevent the formation of a depletion layer in the doped polysilicon electrode and improve the capacitor performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The figure is a schematic diagram of the overall process of a method for manufacturing a silicon capacitor;

[0028] Figure 2 A SiO2 layer is formed on P sub and a 1# capacitor groove structure is etched.

[0029] Figure 3 This is the structure after a SiO2 field oxide layer is generated in the P sub trench.

[0030] Figure 4 The structure is to fill the trench with N poly and seal it, and remove the surface N poly and SiO2.

[0031] Figure 5 This is the structure after etching the 2# capacitor groove on the N poly.

[0032] Figure 6 The structure is formed by depositing Ti / TiN / dielectric layer / TiN / Ti / Npoly in the capacitor groove etched on the Npoly.

[0033] Figure 7 The structure is obtained by etching the multilayer films on both sides of the 2# capacitor groove and depositing a layer of silicon oxide.

[0034] Figure 8 It is the structure after the upper and lower plate polysilicon are connected by metal wires. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] See also Figure 1 , which shows a method for manufacturing a silicon capacitor provided by an embodiment of the present invention, comprising:

[0037] S100: forming an oxide layer on the surface of the silicon substrate by thermal oxidation or chemical vapor deposition process, and then etching a No. 1 capacitor groove by photolithography and dry etching process.

[0038] S200: generating a field oxide layer in the 1# capacitor groove.

[0039] S300: Fill the 1# capacitor groove with doped polysilicon and seal it through a deposition process, and then remove the surface doped silicon and oxide layer through an etching process.

[0040] S400: etching a plurality of 2# capacitor grooves on the doped polysilicon through photolithography and dry etching processes.

[0041] S500: Ti / TiN / dielectric layer / TiN / Ti / doped polysilicon are deposited in the 2# capacitor groove respectively.

[0042] S600: etching away the multilayer film at both ends of the overall 2# capacitor slot by photolithography and etching processes, wherein one end of the overall 2# capacitor slot is etched to expose the lower plate polysilicon, and then a layer of silicon oxide is deposited by a deposition process.

[0043] S700: Through the back-end process, the upper and lower plates, that is, the upper and lower layers of doped polysilicon are connected through metal wires.

[0044] S100 forms a 100-10000A oxide layer on the surface of the silicon substrate through thermal oxidation or chemical vapor deposition process, and then etches out the 1# capacitor groove through photolithography and dry etching process. The depth and width of the 1# capacitor groove are determined according to the capacitance requirements. Figure 2 As shown, 100-10000A SiO2 is formed on the surface of Psub by thermal oxidation or chemical vapor deposition process, and then 1# capacitor groove is etched by photolithography and dry etching process.

[0045] The specific contents of S100 include:

[0046] S110: Oxide layer formation

[0047] Select a suitable silicon substrate and place it in a thermal oxidation device or a chemical vapor deposition device.

[0048] If the thermal oxidation process is used, in a high temperature and oxygen atmosphere, silicon atoms on the surface of the silicon substrate react with oxygen to form silicon oxide (SiO2). By precisely controlling parameters such as temperature, time and oxygen flow rate, the thickness of the oxide layer can reach 100-10000A.

[0049] If the chemical vapor deposition process is used, with silicon source gases such as silane (SiH4) and oxygen as raw materials, the silicon source gas decomposes under the action of high temperature and plasma in the reaction chamber, and silicon atoms react with oxygen and are deposited on the surface of the silicon substrate to form an oxide layer. The process parameters also need to be precisely controlled to ensure the thickness of the oxide layer, so that the oxide layer thickness reaches 100-10000A.

[0050] S120: Photolithography defines the pattern of capacitor slot 1#

[0051] The photoresist is coated on the surface of the silicon substrate on which the oxide layer has been formed. The photoresist needs to be uniform and of appropriate thickness.

[0052] Align the designed 1# capacitor groove pattern mask with the silicon substrate, and use ultraviolet light or other light sources for exposure to cause a photochemical reaction in the photoresist, thereby changing the properties of the photoresist in the illuminated area.

[0053] The exposed silicon substrate is developed, and the photoresist in the illuminated area or the unilluminated area is dissolved by a developer, so that a photoresist pattern consistent with the 1# capacitor groove pattern is formed on the surface of the oxide layer.

[0054] S130: Dry etching to form capacitor groove 1#

[0055] The developed silicon substrate is placed in a dry etching device, such as a reactive ion etching (RIE) device.

[0056] A suitable etching gas, such as a fluorine-based gas such as CF4, SF5, etc., is introduced. Under the action of plasma, the etching gas reacts chemically with the oxide layer not protected by the photoresist, and volatile products are generated and extracted from the reaction chamber, thereby etching away the oxide layer in the 1# capacitor groove pattern area. The etching depth and width are determined according to the capacitance requirements. At the same time, the etching rate, selectivity and other parameters are controlled to ensure that the etching process causes minimal damage to the silicon substrate and the size of the 1# capacitor groove is accurate.

[0057] After etching is completed, the residual photoresist on the surface of the silicon substrate is removed.

[0058] S200: Generate a 100-5000A field oxide layer in the 1# capacitor slot to provide stress buffering and isolation for the subsequent filling of doped polysilicon. Figure 3 As shown, a layer of SiO2 is generated in the 1# capacitor groove, namely the Psub groove.

[0059] S200 specific content includes:

[0060] S210: Preparation before field oxide deposition

[0061] The silicon substrate after etching the No. 1 capacitor groove is cleaned to remove impurity particles, etching gas byproducts and other pollutants that may remain on the surface, to ensure that the inner surface of the No. 1 capacitor groove is clean and provide a good substrate for the deposition of the field oxide layer.

[0062] S220: Field oxide deposition

[0063] The thermal oxidation process is used to grow the field oxide layer. The silicon substrate is placed in a high-temperature oxidation environment. The silicon surface in the 1# capacitor groove reacts with oxygen to generate SiO2. The growth rate is related to temperature, oxygen flow rate and time.

[0064] Alternatively, a chemical vapor deposition process is used, with silicon source gas and oxygen as raw materials, to deposit SiO2 on the inner surface of the No. 1 capacitor slot, and the process parameters are precisely controlled to ensure the quality and thickness uniformity of the field oxide layer.

[0065] Using thermal oxidation and chemical vapor deposition processes, the field oxide layer thickness reaches 100-5000A, providing stress buffering and isolation for subsequent doped polysilicon filling.

[0066] S300: Through the deposition process, doped polysilicon is filled into the 1# capacitor groove and sealed. The doping concentration of the doped polysilicon is 1E11-1 E20cm -3 , and then remove the surface doped silicon and oxide layer through etching process. Figure 4 As shown, N poly is filled into the 1# capacitor groove and sealed through a deposition process, and then the surface N poly and SiO2 are removed through an etching process.

[0067] S300 includes:

[0068] S310: Doped polysilicon deposition to fill capacitor slot 1

[0069] Select a suitable deposition process, such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) in chemical vapor deposition (CVD).

[0070] Silane (SiH4) and other silicon source gases and doping source gases are used as raw materials. The doping source gases include phosphine PH3, arsine AsH3, etc. for n-type doping, and borane B2H6, etc. for p-type doping. In the reaction chamber, the silicon source gas decomposes to provide silicon atoms, and the doping source gas decomposes to provide doping atoms. The silicon atoms and doping atoms are deposited together in the 1# capacitor slot to form doped polysilicon. The doping concentration is controlled at 1E11-1E20cm -3 Within the range, the deposition process needs to ensure filling uniformity without holes or gaps until the 1# capacitor slot is filled and sealed.

[0071] S320: Surface doped silicon and oxide layer removal

[0072] After the doped polysilicon is deposited and sealed, the photolithography process is used to define the area to be removed on the surface, apply photoresist, align the mask for exposure, and develop to expose the doped polysilicon and surface oxide layer in the area to be removed.

[0073] The exposed surface doped polysilicon and oxide layer are removed by dry etching or wet etching process. For dry etching, equipment such as reactive ion etching (RIE) and suitable etching gas can be selected. For wet etching, chemical etching liquid that has selective corrosion effect on doped polysilicon and oxide layer can be selected, such as a mixture of hydrofluoric acid (HF) and nitric acid (HNO3). After etching, the photoresist is removed to ensure a smooth surface in preparation for subsequent processes.

[0074] S400: Through photolithography and dry etching processes, 2# capacitor grooves are etched on doped polysilicon. The number of 2# capacitor grooves is determined according to the capacitance requirements. This groove cannot penetrate the polysilicon, and the groove depth-to-width ratio is 2:1-50:1. Figure 5 As shown, a 2# capacitor groove is etched on the N poly by photolithography and dry etching process.

[0075] S400 includes:

[0076] S410: Photolithography defines the 2# capacitor groove pattern

[0077] Photoresist is coated on the surface of doped polysilicon from which the surface doped silicon and oxide layer have been removed, ensuring that the photoresist has uniform thickness and is free of defects such as pinholes.

[0078] The designed 2# capacitor groove pattern mask is precisely aligned with the silicon substrate and exposed using a light source such as ultraviolet light, so that the photoresist undergoes a photochemical reaction in the illuminated area, changing its solubility in the developer.

[0079] Development treatment is performed to dissolve the photoresist in the corresponding area according to the type of photoresist (positive or negative), and a photoresist pattern consistent with the 2# capacitor groove pattern is formed on the surface of the doped polysilicon. The pattern is used to protect the area that does not need to be etched.

[0080] S420: Dry etching to form capacitor groove 2#

[0081] The developed silicon substrate is placed in a dry etching device, such as an ion beam etching (IBE) or inductively coupled plasma etching (ICP) device.

[0082] A suitable etching gas, such as fluorocarbon gas (such as C4F8, etc.) or chlorine-based gas (such as Cl2, etc.), is introduced. Under the action of plasma, the etching gas reacts chemically with the doped polysilicon not protected by the photoresist to generate volatile products that are extracted from the reaction chamber, and 2# capacitor grooves are etched. The number of grooves is determined according to the capacitance requirements, and the groove depth-to-width ratio is controlled within the range of 2:1-50:1. At the same time, the etching rate, etching angle and other parameters are precisely controlled to ensure the dimensional accuracy and side wall verticality of the 2# capacitor groove to avoid damage to the underlying structure. After etching, the residual photoresist is removed.

[0083] S500: Ti / TiN / dielectric layer / TiN / Ti / doped polysilicon are deposited in the 2# capacitor groove respectively, wherein Ti is heat treated after being deposited so that Ti and polysilicon form metal silicide.

[0084] The doped polysilicon is respectively the upper and lower plates, and the upper plate polysilicon can be replaced by metal.

[0085] Ti is a metal layer, and its resistance is much smaller than that of doped polysilicon. After heat treatment with Si, it can form an ohmic contact, reduce the resistance of the capacitor, improve the conductivity of doped polysilicon, reduce losses, and thus improve the quality factor Q value of the capacitor.

[0086] TiN is a barrier layer. Under the action of voltage, some oxygen in the dielectric layer may diffuse into the upper and lower Si plates, thus affecting the capacitor performance. The presence of TiN can prevent the diffusion from occurring.

[0087] The presence of Ti / TiN can prevent the formation of depletion regions on the dielectric layer and the surface of the doped polysilicon electrode, that is, no new capacitor will be formed in series at both ends of the silicon capacitor, resulting in a decrease in capacitance. Figure 6 As shown, Ti / TiN / dielectric layer / TiN / Ti / Npoly are deposited in the 2# capacitor groove etched on the Npoly.

[0088] S500 includes:

[0089] S510: Ti layer deposition and heat treatment

[0090] Using the sputtering deposition process in physical vapor deposition (PVD), a titanium (Ti) target is placed at the cathode of the sputtering equipment, and a silicon substrate is placed at the anode. Inert gases such as argon (Ar) are introduced under a vacuum environment. Under the action of the electric field, the argon gas is ionized to form plasma. Argon ions bombard the Ti target, causing Ti atoms to sputter out and deposit on the surface of the doped polysilicon in the 2# capacitor slot to form a Ti layer. The thickness is determined according to design requirements.

[0091] After depositing the Ti layer, the silicon substrate is placed in a rapid thermal annealing (RTA) device or a conventional annealing furnace for heat treatment. Under a protective atmosphere such as nitrogen (N2), the temperature is raised to a certain temperature and maintained for a certain period of time, so that Ti and polysilicon react chemically to form metal silicide, thereby reducing the resistance of the capacitor, improving conductivity, reducing losses, and thereby improving the quality factor Q value.

[0092] S520: TiN barrier layer deposition

[0093] The reactive sputtering process in physical vapor deposition (PVD) is adopted, with titanium (Ti) target and nitrogen (N2) as reaction gas. During the sputtering process, Ti atoms and N2 molecules react under the action of plasma, and a TiN barrier layer is deposited on the surface of the formed metal silicide. TiN can block the oxygen in the dielectric layer from diffusing into the upper and lower doped polysilicon plates to prevent affecting the capacitor performance. The thickness is determined according to the design requirements. The process parameters are controlled during the deposition process to ensure the density and uniformity of the TiN layer.

[0094] S530: Dielectric layer deposition

[0095] Select suitable dielectric materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4) or high dielectric constant (high-k) materials, such as HfO2, Al2O3, etc., and select corresponding deposition processes according to the characteristics of dielectric materials, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0096] Taking SiO2 as an example, the plasma enhanced chemical vapor deposition (PECVD) process is adopted, with silane (SiH4) and oxygen (O2) as raw materials. Under the action of plasma, a SiO2 dielectric layer is deposited on the surface of the TiN barrier layer. The thickness is determined according to the capacitor design requirements. The process parameters are controlled during the deposition process to ensure the quality of the dielectric layer, such as thickness uniformity, no holes and low defect density. The quality of the dielectric layer directly affects the capacitor performance.

[0097] S540: TiN / Ti / doped polysilicon upper plate deposition

[0098] The TiN layer is deposited by a reactive sputtering process in physical vapor deposition (PVD). Similar to the previous process of depositing the TiN barrier layer, a TiN layer is formed on the surface of the dielectric layer to prevent the formation of a depletion region on the dielectric layer and the surface of the Si electrode.

[0099] The Ti layer is then deposited using a sputtering deposition process. Similar to the previous Ti layer deposition process, the Ti layer forms an ohmic contact with the doped polysilicon of the upper electrode plate to reduce resistance.

[0100] Finally, the chemical vapor deposition (CVD) process is used to deposit doped polysilicon as the upper electrode. The deposition process is similar to the doped polysilicon deposition for filling the 1# capacitor slot. The doping concentration and other parameters are adjusted according to the specific requirements of the upper electrode, and the thickness is determined according to the capacitor design.

[0101] S600: The multilayer films at both ends of the overall 2# capacitor slot are etched away through photolithography and etching processes, wherein one end of the overall 2# capacitor slot is etched to expose the lower plate polysilicon, and then a layer of silicon oxide is deposited through a deposition process to prepare for the subsequent process. Figure 7 shown.

[0102] S600 specific contents include:

[0103] S610: Photolithography defines the etching areas of the multilayer films at both ends

[0104] The surface of the silicon substrate on which the multilayer film deposition in the 2# capacitor groove has been completed is coated with photoresist, which is required to be uniform, defect-free and of appropriate thickness.

[0105] The designed etching area pattern mask is precisely aligned with the silicon substrate and exposed using a light source such as ultraviolet light, causing the photoresist to undergo a photochemical reaction in the illuminated area, changing its solubility.

[0106] Through development processing, the photoresist in the corresponding area is dissolved according to the type of photoresist, and a photoresist pattern for etching is formed on the surface of the multilayer film at both ends of the 2# capacitor groove. The pattern defines the area that needs to be etched to expose one end of the lower electrode polysilicon and prepare a suitable surface structure for subsequent processes.

[0107] S620: Etching the multilayer film at both ends of the 2# capacitor slot

[0108] The developed silicon substrate is placed in a dry etching device, such as a reactive ion etching (RIE) device, and a suitable etching gas combination is selected according to the material characteristics of each layer in the multilayer film, such as a fluorine-based gas, a chlorine-based gas, etc. Under the action of plasma, the Ti, TiN, dielectric layer and other materials not protected by the photoresist in the multilayer films at both ends are etched away in turn, and the etching rate, selectivity, etching depth and other parameters are precisely controlled to ensure that the underlying structure is not damaged during the etching process and that the etching area has clear boundaries and precise dimensions. After the etching is completed, the residual photoresist is removed.

[0109] S630: Silicon oxide deposition preparation and deposition

[0110] After etching is completed, the silicon substrate is cleaned to remove impurities such as etching byproducts, particulate contaminants, etc. that may remain on the surface, to ensure the surface is clean and provide a good substrate for silicon oxide deposition.

[0111] A chemical vapor deposition (CVD) process, such as plasma enhanced chemical vapor deposition (PECVD), is used with silane (SiH4) and oxygen (O2) as raw materials. In the reaction chamber, silane decomposes to provide silicon atoms and oxygen provides oxygen atoms. A layer of silicon oxide is deposited on the surface exposed by etching at both ends of the 2# capacitor groove. The thickness is determined according to the requirements of the subsequent process. The silicon oxide layer can provide a good interface and insulation protection for subsequent processes such as metal wire connection.

[0112] S700 coats high-quality photoresist on the surface of the silicon substrate where the silicon oxide layer is deposited, uses a mask to align the exposure, and develops to form a photoresist pattern in the metal wire connection area. Using sputtering deposition or electron beam evaporation deposition technology, select a suitable metal, and introduce an inert gas under vacuum to deposit metal atoms in the area defined by the photoresist pattern to form a metal wire connecting the upper and lower plates. Control parameters to ensure good ohmic contact. Finally, using a stripping process, place the silicon substrate in a solvent to remove the photoresist and excess metal, completing the manufacture of the silicon capacitor, and then conduct electrical performance and reliability tests to ensure that the performance meets the standards. Formation such as Figure 8 The silicon capacitor shown.

[0113] S700 includes:

[0114] S710: Photolithography defines metal line connection areas

[0115] Coat photoresist on the surface of the silicon substrate on which the silicon oxide layer has been deposited to ensure that the quality of the photoresist meets the requirements, such as good uniformity and no pinholes.

[0116] The designed metal wire connection area pattern mask is precisely aligned with the silicon substrate and exposed using a light source such as ultraviolet light, causing the photoresist to undergo a photochemical reaction in the illuminated area, changing its solubility in the developer.

[0117] Development treatment is performed to dissolve the photoresist in the corresponding area according to the type of photoresist, and a photoresist pattern corresponding to the metal wire connection area of ​​the upper and lower plates is formed on the surface of the silicon oxide layer. This pattern is used to protect the area where metal wire connection is not required, and at the same time provides a template for subsequent metal deposition.

[0118] S720: Metal wire deposition connects the upper and lower plates

[0119] Using the sputtering deposition or electron beam evaporation deposition process in physical vapor deposition (PVD), select suitable metal materials, such as aluminum (Al), copper (Cu), etc., place the metal target in the deposition equipment, and introduce inert gases such as argon (Ar) in a vacuum environment. Under the action of the electric field or electron beam, metal atoms are sputtered or evaporated and deposited in the area defined by the photoresist pattern to form a metal wire connecting the upper and lower plates. The thickness of the metal wire is determined according to the design requirements such as current carrying capacity. During the deposition process, it is necessary to control the process parameters, such as deposition rate and uniformity, to ensure that the metal wire forms a good ohmic contact with the upper and lower plates, without defects such as holes and cracks, to ensure the reliability of electrical connection.

[0120] S730: Photoresist and excess metal removal

[0121] After the metal wire deposition is completed, the stripping process is used to remove the surface photoresist and the excess metal attached to the photoresist. The silicon substrate is placed in a suitable solvent, such as acetone, N-methylpyrrolidone (NMP), etc. The photoresist is dissolved in the solvent, and the excess metal on the photoresist falls off, thereby obtaining a silicon capacitor structure that retains the metal wire only in the upper and lower plate connection area, completing the manufacturing process of the silicon capacitor. Finally, the silicon capacitor is subjected to electrical performance testing, reliability testing and other testing steps to ensure that its performance meets the design requirements, such as capacitance value, quality factor Q value, leakage current and other parameters are within the specified range, and the product is reliable and stable.

[0122] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0123] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0124] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0125] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features of the present invention.

[0126] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for manufacturing a silicon capacitor, characterized in that: include: S100: forming an oxide layer on the surface of the silicon substrate by thermal oxidation or chemical vapor deposition process, and then etching a No. 1 capacitor groove by photolithography and dry etching process; S200: generating a field oxide layer in the 1# capacitor groove; S300: filling the 1# capacitor groove with doped polysilicon and sealing it through a deposition process, and then removing the surface doped silicon and oxide layer through an etching process; S400: etching a plurality of 2# capacitor grooves on the doped polysilicon by photolithography and dry etching processes; S500: Ti / TiN / dielectric layer / TiN / Ti / doped polysilicon are deposited in the 2# capacitor groove respectively; S600: etching away the multilayer film at both ends of the overall 2# capacitor slot by photolithography and etching processes, wherein one end of the overall 2# capacitor slot is etched to expose the lower plate polysilicon, and then a layer of silicon oxide is deposited by a deposition process; S700: Through the back-end process, the upper and lower plates, that is, the upper and lower layers of doped polysilicon are connected through metal wires.

2. The method for manufacturing a silicon capacitor according to claim 1, characterized in that: In the S100, the oxide layer is formed by thermal oxidation or chemical vapor deposition process, so that the oxide layer thickness reaches 100-10000 Å.

3. The method for manufacturing a silicon capacitor according to claim 1, characterized in that: In the above S200, before the field oxide layer is deposited, the silicon substrate after etching the No. 1 capacitor groove is cleaned; the deposition is carried out by using a thermal oxidation process or a chemical vapor deposition process, so that the field oxide layer has a thickness of 100-5000A.

4. The method for manufacturing a silicon capacitor according to claim 1, characterized in that: In the step S300, the doped polysilicon is deposited to fill the capacitor slot 1# using a chemical vapor deposition process, with silane and a doping source gas as raw materials, and the silicon source gas and the doping source gas are decomposed and co-deposited to form doped polysilicon, with a doping concentration of 1E11-1E20cm -3 .

5. The method for manufacturing a silicon capacitor according to claim 1, characterized in that: In the S400, the depth-to-width ratio of the 2# capacitor groove is 2:1-50:

1.

6. The method for manufacturing a silicon capacitor according to claim 1, characterized in that: In S500, Ti deposition is performed by a sputtering deposition process in physical vapor deposition; TiN deposition uses a reactive sputtering process, where the titanium target reacts with nitrogen to deposit a TiN layer on the surface of the metal silicide; The dielectric layer deposition process is selected according to the dielectric material. SiO2 is deposited using the PECVD process with silane and oxygen as raw materials. TiN / Ti / doped polysilicon upper plate deposition, first reactive sputtering TiN layer, then sputtering deposition of Ti layer, and finally chemical vapor deposition of doped polysilicon upper plate.

7. The method for manufacturing a silicon capacitor according to claim 1, characterized in that: In the S600, when etching the multilayer film at both ends of the 2# capacitor groove, the silicon substrate is placed in a reactive ion etching device, an etching gas combination is selected according to the material characteristics, and the resist is removed after etching; the silicon substrate is cleaned before silicon oxide deposition, and then a PECVD process is used to etch the exposed surface at both ends of the groove using silane and oxygen as raw materials to deposit silicon oxide.

8. The method for manufacturing a silicon capacitor according to claim 1, characterized in that: In the above S700, the metal wires are connected to the upper and lower electrodes by sputtering deposition or electron beam evaporation deposition process, and inert gas is introduced under vacuum to deposit metal atoms in the photoresist pattern definition area to form metal wires.

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