Phase shifting circuit, step-down switching converter group, and converter chip

Abstract

The present application relates to the technical field of electronic circuit, and discloses a phase-shifting circuit, a step-down switching converter group and a converter chip.The phase-shifting circuit comprises: a delay phase-shifting module, comprising a plurality of delay phase-shifting units; a decoder, an input end of which is connected with different input voltage signals, and a plurality of output ends of which are connected with control ends of the plurality of delay phase-shifting units respectively; a comparator, positive and negative input ends of which are connected with an output end of the delay phase-shifting module and a reference voltage respectively; and a flip-flop, an R end of which is connected with a clock signal, an output end of which is connected with an input end of the delay phase-shifting module, and an S end of which is connected with an output end of the comparator.The decoder is used for controlling the corresponding delay phase-shifting unit to be turned on in response to a specific input voltage signal, so as to output a phase-shifted clock signal through the comparator.The present application can effectively perform phase shift on the clock, perform multi-phase operation in multiple phases, can provide sufficient load current required by engineering application, and the inductance current ripple can be offset, and the output voltage ripple is smaller.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to a phase-shifting circuit, a buck converter group, and a converter chip. Background Technology

[0002] Since the advent of electronic products, buck converters have been widely used in battery-powered applications such as various communication devices, portable electronic devices, microprocessors, and automotive electronics. This has led to newer and more diverse design requirements for buck converters, one of which is the power supply for autonomous vehicles. The processors inside autonomous vehicles need to perform a large amount of computation and processing on driving environment information in a short period of time to ensure safe driving. This requires the power supply system to provide a large current and respond quickly to changes in load current.

[0003] However, in existing buck switching converter chips, in-phase operation with a single phase can lead to insufficient load current supply. Summary of the Invention

[0004] The purpose of this invention is to provide a phase-shifting circuit, a buck switching converter group, and a converter chip, which can effectively shift the phase of the clock to perform multi-phase operation, provide sufficient load current required for engineering applications, and cancel out inductor current ripple, resulting in smaller output voltage ripple.

[0005] To achieve the above objectives, a first aspect of the present invention provides a phase-shifting circuit, comprising: a delay phase-shifting module including a plurality of delay phase-shifting units; a decoder, wherein the input terminal of the decoder is connected to different input voltage signals, and the plurality of output terminals of the decoder are respectively connected to the control terminals of the plurality of delay phase-shifting units; a first comparator, wherein the positive input terminal of the first comparator is connected to the output terminal of the delay phase-shifting module, and the negative input terminal of the first comparator is connected to a first reference voltage; and a first flip-flop, wherein the R input terminal of the first flip-flop is connected to a clock signal, the output terminal of the first flip-flop is connected to the input terminal of the delay phase-shifting module, and the S input terminal of the first flip-flop is connected to the output terminal of the first comparator, wherein the decoder is used to control the corresponding delay phase-shifting unit among the plurality of delay phase-shifting units to conduct in response to a specific input voltage signal, so as to output a phase-shifted clock signal through the first comparator.

[0006] Preferably, the plurality of delay phase-shifting units include: a shared complementary MOSFET; a plurality of parallel capacitor circuits, each capacitor circuit including a capacitor and a switching unit, and one end of the capacitor circuit being connected to the drain of the complementary MOSFET; a plurality of output terminals of the decoder being respectively connected to the control terminals of the switching units in the plurality of parallel capacitor circuits; the positive input terminal of the first comparator being connected to the drain of the complementary MOSFET; and the output terminal of the first flip-flop being connected to the gate of the complementary MOSFET, wherein the decoder is used to control the switching unit on one of the capacitor circuits in the plurality of parallel capacitor circuits to close in response to the specific input voltage signal, thereby turning on the corresponding capacitor circuit.

[0007] Preferably, the complementary MOS transistor includes a PMOS transistor and an NMOS transistor, and the plurality of delay phase shift units further include: a common current source, the current source being connected to the source of the PMOS transistor, and the source of the NMOS transistor being grounded.

[0008] Preferably, the decoder includes: n second comparators, the negative input terminals of the n second comparators being connected to n input voltage signals respectively, and the positive input terminals of the n second comparators being connected to each other; and n logic gate combinations, wherein the i-th logic gate combination includes ni NOT gates and 1 AND gate, wherein the number of input terminals of the AND gate is n, the output terminals of the 1st to i-th second comparators are directly connected to the 1st to i-th input terminals of the AND gate, and the (i+1)th to nth input terminals are connected to the (i+1)th to nth input terminals of the AND gate through corresponding NOT gates.

[0009] Through the above technical solution, this invention creatively incorporates a delay phase-shifting module, a decoder, a first comparator, and a first flip-flop into the phase-shifting circuit. The decoder's input terminals are connected to different input voltage signals, and its multiple output terminals are respectively connected to the control terminals of multiple delay phase-shifting units within the delay phase-shifting module. The positive input terminal of the first comparator is connected to the output terminal of the delay phase-shifting module, and its negative input terminal is connected to a first reference voltage. The R input terminal of the first flip-flop is connected to a clock signal, its output terminal is connected to the input terminal of the delay phase-shifting module, and its S input terminal is connected to the output terminal of the first comparator. The decoder is used to control the corresponding delay phase-shifting unit among the multiple delay phase-shifting units to conduct in response to a specific input voltage signal, thereby outputting a phase-shifted clock signal through the first comparator. Thus, this invention can effectively shift the phase of a clock signal through a simple circuit design.

[0010] A second aspect of the present invention provides a buck switching converter group in peak current mode, the buck switching converter group comprising: N buck switching converters connected in parallel, where N is an integer greater than 1, wherein each buck switching converter comprises: a main circuit; a pulse modulation control circuit, one input terminal of which is connected to a voltage feedback point external to the output terminal of the main circuit; a loop control circuit, the output terminal of which is connected to the gates of the upper and lower power transistors of the main circuit; and the phase shifting circuit, wherein the clock input of the phase shifting circuit is... The input terminal is connected to the first input terminal of the loop control circuit, and the output terminal of the pulse modulation control circuit is connected to the second input terminal of the loop control circuit. The phase shift angle of the phase shift circuit is 360° / N. The clock output terminal of the phase shift circuit in any two adjacent buck switching converters is connected to the clock input terminal of the phase shift circuit in the second converter. The first buck switching converter further includes an oscillator circuit, the clock signal output terminal of which is connected to the first input terminal of the loop control circuit to generate the initial clock signal.

[0011] Preferably, the pulse modulation control circuit includes: an error amplifier, the negative input terminal of which is connected to the voltage feedback point, and the positive input terminal of which is connected to the target feedback voltage; and a PWM comparator, one positive input terminal of which is connected to the output terminal of the CCVS of the main circuit, and the output terminal of which is connected to the second input terminal of the loop control circuit.

[0012] Preferably, the other positive input terminal of the PWM comparator is connected to the ramp signal output terminal of the oscillator circuit.

[0013] Preferably, the N parallel-connected buck switching converters have the same structure. The buck switching converter further includes a switching module, which includes a switching unit and a switching control circuit. The clock output terminal of the oscillator circuit is connected to the first input terminal of the loop control circuit via the switching unit. The corresponding switching unit is closed by the switching control circuit in the first buck switching converter, and the corresponding switching unit is opened by the switching control circuit in the other buck switching converters.

[0014] Preferably, the switch control circuit includes: a third comparator, the positive input terminal of the third comparator being connected to a selection signal, the negative input terminal of the third comparator being connected to a second reference voltage, and the output terminal of the third comparator being connected to the control terminal of the switch unit.

[0015] Preferably, the loop control circuit includes a second flip-flop, the first input terminal is an S input terminal, and the second input terminal is an R input terminal.

[0016] Through the above technical solution, the present invention creatively introduces a phase-shifting circuit with adjustable phase shift angle into a buck switching converter. An oscillator circuit is set in the first buck switching converter to generate its own clock signal. Combined with the pulse signal generated by the pulse modulation control circuit, the fixed on-time of the power transistor is controlled. Furthermore, multiple buck switching converters are connected in parallel. Therefore, the present invention can perform multi-phase operation with multiple phases, can provide sufficient load current required for engineering applications, and the inductor current ripple is canceled, resulting in smaller output voltage ripple.

[0017] A third aspect of the present invention provides a converter chip, the converter chip comprising: a buck switching converter group in peak current mode; and a selection switch for selecting the 1st to the kth buck switching converter from N parallel-connected buck switching converters in the buck switching converter group, wherein 1 <k≤N。

[0018] Through the above technical solution, the present invention creatively uses a phase-shifting circuit to form multiple phase-shifting options when multiple chips are connected in parallel, so that the inductor current ripple can be canceled when multiple chips are connected in parallel, the output voltage ripple is smaller, and sufficient load current can be provided for engineering applications.

[0019] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0021] Figure 1 This is a schematic diagram of the phase-shifting circuit provided in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the decoder provided in an embodiment of the present invention;

[0023] Figure 3A This is a schematic diagram of a buck switching converter in peak current mode according to an embodiment of the present invention;

[0024] Figure 3B This is a schematic diagram of a buck switching converter in peak current mode according to an embodiment of the present invention;

[0025] Figure 4This is a clock phase shift diagram of four converters connected in parallel according to an embodiment of the present invention; and

[0026] Figure 5 This is a schematic diagram of a structure in which four converters are connected in parallel according to an embodiment of the present invention. Detailed Implementation

[0027] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0028] Figure 1 This is a schematic diagram of the phase-shifting circuit provided in an embodiment of the present invention. Figure 1 As shown, the phase-shifting circuit 10 includes: a delay phase-shifting module 1, including multiple delay phase-shifting units (e.g., delay phase-shifting units 1-1, 1-2, 1-3, ..., 1-n); a decoder 2, the input terminal of which is connected to different input voltage signals, and multiple output terminals of which are respectively connected to the control terminals of the multiple delay phase-shifting units; a first comparator 3, the positive input terminal of which is connected to the output terminal of the delay phase-shifting module 1, and the negative input terminal of which is connected to a first reference voltage; and a first flip-flop 4, the R input terminal of which is connected to a clock signal (e.g., CLK_IN), the output terminal of which is connected to the input terminal of the delay phase-shifting module 1, and the S input terminal of which is connected to the output terminal of the first comparator 3.

[0029] The decoder 2 is used to control the corresponding delay phase shift unit among the plurality of delay phase shift units to be turned on in response to a specific input voltage signal, so as to output the phase-shifted clock signal through the first comparator 3.

[0030] like Figure 1 As shown, the phase-shifting circuit has three pins: PHMODE, CLK_IN, and CLK_OUT. The PHMODE pin is connected to the input of decoder 2 and is used to receive different input voltage signals. The output of decoder 2 is connected to the control terminal of each delay phase-shifting unit (e.g., the control terminal of a voltage-controlled switch). The truth table of decoder 2 is shown in Table 1 below. Different input PHMODE signals correspond to different delay phase-shifting units (e.g., different capacitors), thus performing different phase shift selections. When the PHMODE pin is connected to input voltage signals greater than V1 and less than V2, greater than V2 and less than V3, greater than V3 and less than V4, etc., a phase difference of 180 degrees, 120 degrees, and 90 degrees (between CLK_IN and CLK_OUT) will be generated, corresponding to 2-phase, 3-phase, or 4-phase operating modes.

[0031] For example, when the input PHMODE signal is V1, D1 outputs a high level to select the delay phase shift unit 1-1. For example, because each delay phase shift unit has a different capacitor, the capacitor charging time is different, resulting in different delay times for the clock pulse signal, thus shifting the phase of the clock pulse signal. The output Q signal of the first flip-flop 4 is connected to the input terminal of the delay phase shift module to control the charging and discharging of the capacitors in the delay phase shift unit. The delay capacitor is connected to the positive input terminal of the first comparator 3, the CLK_IN signal is connected to the R input terminal of the first flip-flop 4 (used to control capacitor charging), the output of the first comparator 3 is connected to the S input terminal of the first flip-flop 4 (used to control capacitor discharging), and finally, the output of the first comparator 3 is connected to the CLK_OUT pin to complete the phase shift.

[0032] Table 1 Truth Table of Decoder

[0033] A1 A2 A3 A4 … An D1D2D3D4…Dn 1 0 0 0 … 0 1000…0 1 1 0 0 … 0 1100…0 1 1 0 0 … 0 1110…0 1 1 0 0 … 0 1111…0 1 1 0 0 … 0 1111…0 1 1 0 0 … 0 1111…1

[0034] Phase-shifting circuits are used to shift the phase of the input clock, enabling the converter to operate in multiple phases. This avoids situations where the load current is insufficient and multiple phases need to be cascaded to provide the load current required for engineering applications.

[0035] like Figure 1 As shown, the plurality of delay phase-shifting units include: a shared complementary MOS transistor; a plurality of parallel capacitor circuits, each capacitor circuit including a capacitor and a switching unit (e.g., a first capacitor circuit including capacitor C1 and switch S1; a second capacitor circuit including capacitor C2 and switch S2; a third capacitor circuit including capacitor C3 and switch S3, etc.), and one end of each capacitor circuit being connected to the drain of the complementary MOS transistor; a plurality of output terminals of the decoder 2 being respectively connected to the control terminals of the switching units (e.g., switches S1, S2, S3, etc.) in the plurality of parallel capacitor circuits; the positive input terminal of the first comparator 3 being connected to the drain of the complementary MOS transistor; and the output terminal of the first flip-flop 4 being connected to the gate of the complementary MOS transistor.

[0036] The decoder 2 is used to control the switching unit on one of the multiple parallel capacitor circuits to close in response to the specific input voltage signal, thereby turning on the corresponding capacitor circuit.

[0037] The complementary MOS transistors include PMOS transistors and NMOS transistors. The plurality of delay-phase shifting units also include a common current source I. REF The current source I REF The source of the PMOS transistor is connected to the source of the NMOS transistor, and the source of the NMOS transistor is grounded.

[0038] The PHMODE pin is connected to the input of decoder 2 to receive different input voltage signals. The output of decoder 2 is connected to the control terminals of each voltage-controlled switch. The truth table of decoder 2 is shown in Table 1. Different input PHMODE signals correspond to different capacitors, thus performing different phase shift selections. For example, when the input PHMODE signal is V1, it corresponds to D1 outputting a high level, thereby selecting capacitor C1. Since each capacitor is different, the charging time of the capacitor is different, thus causing different delay times for the clock pulse signal, thereby shifting the phase of the clock pulse signal. The output Q signal of the first flip-flop 4 is connected to the gates of the two MOS transistors to control the charging and discharging of the capacitor. The delay capacitor is connected to the positive input terminal of the first comparator 3, the CLK_IN signal is connected to the R input terminal of the first flip-flop 4 (used to control the charging of the capacitor), the output of the first comparator 3 is connected to the S input terminal of the first flip-flop 4 (used to control the discharging of the capacitor), and finally the output of the first comparator 3 is connected to the CLK_OUT pin to complete the phase shift.

[0039] like Figure 1 As shown, the clock input CLK_IN is connected to the R input terminal of the first flip-flop 4. The closing of switch S3 (e.g., voltage-controlled switch) is determined by the voltage signal of the PHMODE pin. When the voltage signal input to the PHMODE pin is greater than V3 and less than V4, the D3 signal shown in truth table 1 will output a high level. At this time, the switch S3 of capacitor C3 will be closed and turned on, thereby shifting the clock signal by 90°.

[0040] In one embodiment, the decoder 2 includes: n second comparators, the negative inputs of which are respectively connected to n input voltage signals, and the positive inputs of which are connected to each other; and n logic gate combinations, such as... Figure 2 As shown.

[0041] The i-th logic gate combination includes ni NOT gates and 1 AND gate. The AND gate has n inputs. The outputs of the 1st to 1st second comparators are directly connected to the 1st to 1st inputs of the AND gate. The (i+1)th to nth inputs are connected to the (i+1)th to nth inputs of the AND gate through corresponding NOT gates. Figure 2 As shown in the figure. Where i ≤ n, and both are positive integers.

[0042] In summary, this invention creatively incorporates a delay phase-shifting module, a decoder, a first comparator, and a first flip-flop into a phase-shifting circuit. The decoder's input terminals are connected to different input voltage signals, and its multiple output terminals are respectively connected to the control terminals of multiple delay phase-shifting units within the delay phase-shifting module. The positive input terminal of the first comparator is connected to the output terminal of the delay phase-shifting module, and its negative input terminal is connected to a first reference voltage. The R input terminal of the first flip-flop is connected to a clock signal, its output terminal is connected to the input terminal of the delay phase-shifting module, and its S input terminal is connected to the output terminal of the first comparator. The decoder is used to control the corresponding delay phase-shifting unit among the multiple delay phase-shifting units to conduct in response to a specific input voltage signal, thereby outputting a phase-shifted clock signal through the first comparator. Thus, this invention can effectively shift the phase of a clock signal through a simple circuit design.

[0043] One embodiment of the present invention provides a buck switching converter group in peak current mode, the buck switching converter group comprising: N buck switching converters 100 connected in parallel, such as... Figure 3A or Figure 3B As shown, N is an integer greater than 1. For example, the buck switching converter group includes four buck switching converters 100 connected in parallel, such as... Figure 5 As shown.

[0044] like Figure 3A As shown, the buck converter 100 includes: a main circuit 20; a pulse modulation control circuit 40, one input terminal of which is connected to a voltage feedback point FB external to the output terminal of the main circuit 20; a loop control circuit 30, the output terminal of which is connected to the gates of the upper power transistor M1 and the lower power transistor M2 of the main circuit 20; and a phase shifting circuit 10, the clock input terminal of which is connected to the first input terminal of the loop control circuit 30, and the output terminal of the pulse modulation control circuit 40 is connected to the second input terminal of the loop control circuit 30. The phase shift angle of the phase shifting circuit 10 is 360° / N. Figure 5 As shown, four buck converters 100 connected in parallel have their phase shift angle adjusted to 90°.

[0045] In any two adjacent buck switching converters, the clock output of the phase shift circuit in the first converter is connected to the clock input of the phase shift circuit in the second converter.

[0046] like Figure 5As shown, for four parallel buck converters, the clock output CLK_OUT of the phase shift circuit in the first buck converter is connected to the clock input CLK_IN of the phase shift circuit in the second buck converter; the clock output CLK_OUT of the phase shift circuit in the second buck converter is connected to the clock input CLK_IN of the phase shift circuit in the third buck converter, and the connection of the clock outputs and inputs of the other two adjacent converters is similar.

[0047] like Figure 3B As shown, the first buck switching converter also includes an oscillator circuit 50, the clock signal output terminal of which is connected to the first input terminal of the loop control circuit 30 to generate the initial clock signal.

[0048] Specifically, each buck switching converter includes: a main circuit 20; a pulse modulation control circuit 40; a loop control circuit 30; and a phase shifting circuit 10. The main circuit 20 converts the high voltage provided by the DC source into the low DC voltage required for the normal operation of the electrical equipment. The pulse modulation control circuit 40 employs voltage and current feedback closed-loop control, adjusting the duty cycle based on the output feedback voltage of the buck switching converter to maintain a stable output voltage. In addition, as... Figure 3B As shown, the first buck switching converter also includes an oscillator circuit 50. The loop control circuit 30 is used to output a control signal based on the signal generated by the pulse modulation control circuit 40 and the initial clock signal generated by the oscillator circuit 50, so as to trigger the upper and lower power transistors to turn on or off.

[0049] Figure 4 The diagram shows the clock signals of four buck switching converters 100 connected in parallel: CLK1 (clock signal without phase shift), CLK2 (clock signal with 90° phase shift relative to CLK1), CLK3 (clock signal with 90° phase shift relative to CLK2), and CLK4 (clock signal with 90° phase shift relative to CLK3).

[0050] In various embodiments, the loop control circuit 30 includes a second flip-flop, the first input terminal being an S input terminal, and the second input terminal being an R input terminal.

[0051] Specifically, the buck converter 100 includes: a main circuit 20; a second flip-flop, the output of which is connected to the gates of the upper power transistor M1 and the lower power transistor M2 of the main circuit 20; and a phase shift circuit 10, the clock input of which is connected to the S input of the second flip-flop, and the output of the pulse modulation control circuit 40 is connected to the R input of the second flip-flop. The phase shift angle of the phase shift circuit 10 is 360° / N. Figure 5 As shown, four buck converters 100 connected in parallel have their phase shift angle adjusted to 90°.

[0052] like Figure 3A As shown, the main circuit 20 includes: an upper power transistor M1; a lower power transistor M2; a CCVS located between the upper power transistor M1 and the lower power transistor M2; an inductor L; and an output capacitor Cout, wherein the inductor L is connected in series with the output capacitor Cout and in parallel with the lower power transistor M2. A first voltage divider resistor R1 and a second voltage divider resistor R2, connected in series through the voltage feedback point FB, are connected in parallel with the output capacitor Cout, wherein the first voltage divider resistor R1 and the second voltage divider resistor R2 are either output terminals of the main circuit or external voltage divider resistors connected to the converter.

[0053] An external battery pack can be used to provide power VIN to the converter. Power VIN is connected to the source of the upper power transistor, and the drain is connected to CCVS to collect the current of the upper power transistor. CCVS (which acts as a current sampling module) is a voltage source controlled by current. Through a certain ratio conversion, the current of the upper power transistor is converted into voltage and superimposed with the SLOPE signal generated by the oscillator circuit for slope compensation. The connection point of the drains of the two switching power transistors is SW. The SW node is connected to the inductor L. The inductor L is connected in parallel with the resistor R_ESR and the capacitor C_OUT, and then in parallel with the external voltage divider resistors R1 and R2. The connection point of the voltage divider resistors R1 and R2 is the FB node. The desired feedback voltage is selected by the resistance values ​​of the voltage divider resistors R1 and R2.

[0054] In one embodiment, the pulse modulation control circuit 40 includes: an error amplifier EA, the negative input terminal of which is connected to a voltage feedback point FB external to the output terminal of the main circuit 20, and the positive input terminal of which is connected to a target feedback voltage (e.g., 0.6V); and a PWM comparator, one positive input terminal of which is connected to the output terminal of the CCVS of the main circuit 20, and the output terminal of which is connected to the second input terminal of the loop control circuit 30.

[0055] Specifically, the output of the PWM comparator is connected to the R input of the second flip-flop, and the clock signal output of the oscillator circuit is connected to the S input of the second flip-flop. The clock signal generated by the oscillator circuit 50 is phase-shifted by the phase-shifting circuit 10 to output the phase-shifted clock signal CLK_OUT. This clock signal CLK_OUT serves as the input signal CLK_IN of the phase-shifting circuit of the next buck-type switching converter. Similarly, multiple buck-type switching converters can generate multi-phase output signals. The buck-type switching converter provided by this invention introduces a clock phase-shifting circuit and uses a multi-phase output interleaving method to reduce ripple. This load current sharing technology can solve the problem of local overheating or insufficient output power caused by uneven output current, and quickly achieve loop stability.

[0056] To perform slope compensation, in this embodiment, the other positive input terminal of the PWM comparator is connected to the slope signal output terminal of the oscillator circuit 50, such as... Figure 3B As shown.

[0057] In one embodiment, since it is not yet clear which one will be the first converter in the converter group when the buck switching converter is fabricated, the structures of each converter can be designed to be the same, and the pulse modulation control circuit and the timing circuit can be turned on or off by configuring certain switching modules.

[0058] Specifically, the N parallel-connected buck switching converters have the same structure. For example... Figure 3B As shown, the buck switching converter further includes a switching module, comprising a switching unit S and a switching control circuit, wherein the clock output terminal of the oscillator circuit 50 is connected to the first input terminal of the loop control circuit 30 via the switching unit S.

[0059] Accordingly, the corresponding switch unit S is closed by the switch control circuit in the first buck converter; and the corresponding switch unit S is opened by the switch control circuit in the other buck converters.

[0060] In other words, for the first buck switching converter in the converter group, the oscillator circuit is turned on by controlling S to close; while for the other buck switching converters, the oscillator circuit is turned off by controlling S to open.

[0061] like Figure 3B As shown, the switch control circuit includes: a third comparator 60, the positive input terminal of the third comparator 60 is connected to the selection signal SELECT, the negative input terminal of the third comparator 60 is connected to a second reference voltage (e.g., 4V), and the output terminal of the third comparator 60 is connected to the control terminal of the switch unit S.

[0062] like Figure 3B As shown, SELECT is a direct user input. When the input is high (e.g., above 4V), the comparator connected to the SELECT pin outputs a high level. This high-level signal directly controls the switching state of the switching unit S. At this time, S is closed, using its own clock signal input. When SELECT is grounded, the comparator outputs a low level, the switching unit S is open, and an external clock signal input is used. In other words, SELECT is a direct user input used to determine whether the converter selects the clock output signal generated by the previous converter.

[0063] like Figure 3B As shown, the buck converter uses peak current mode control. A 0.6V reference voltage is connected to the positive terminal of the error amplifier EA (which contains a compensation circuit for EA), and the negative terminal is connected to the feedback voltage at the voltage feedback point FB connected from the converter's periphery. The ramp signal (e.g., SLOPE signal) generated by the oscillator circuit 50 is superimposed on the voltage signal of the upper power transistor M1 (used for ramp compensation) and then connected to the positive input terminal of the PWM comparator. The negative terminal is connected to the output of the error amplifier EA. For the first buck switching converter, the switch unit S is closed by controlling the SELECT signal, so that the output signal Vc of the PWM comparator and the clock signal (e.g., CLK signal) output by the oscillator circuit 50 both enter the loop control circuit 30. The clock signal (e.g., CLK signal) output by the oscillator circuit 50 undergoes a corresponding phase shift via the phase shift circuit 10, that is, the phase shift circuit 10 can output the phase-shifted clock signal (e.g., CLK_OUT). The output signal of the loop control circuit 30 can be connected to the drive circuit, which drives the upper power transistor M1 and the lower power transistor M2 to achieve the switching buck function and output the SW signal.

[0064] The clock signal frequency generated by oscillator circuit 50 is fixed. The phase shift function not only affects the clock but also reduces the current ripple effect. The change of PWM duty cycle is determined by the rise time and fall time of the positive input signal of the PWM comparator.

[0065] During normal operation, the upper power transistor M1 is turned on every cycle when the oscillator circuit 50 sets the loop control circuit 30 (e.g., a trigger) (e.g., S is 1), and turned off when the PWM comparator reset loop control circuit 30 (e.g., a trigger) (e.g., R is 1). The peak inductor current during the PWM comparator reset loop control circuit 30 (e.g., a trigger) is controlled by the output of the error amplifier EA. When the load current increases, it causes the voltage at the voltage feedback point FB to drop slightly relative to the 0.6V reference voltage, which in turn causes the output voltage of the EA amplifier to increase until the average inductor current matches the new load current. When the upper power transistor M1 is turned off, the lower power transistor M2 is turned on until the inductor current begins to reverse or the next clock cycle begins. That is, when the ramp-compensated signal voltage is lower than the EA amplifier output, the PWM comparator output voltage is low, the switching transistor is on, and the inductor current increases; when the ramp-compensated signal voltage is higher than the EA amplifier output, the switching transistor is off, the synchronous rectifier is on, and the inductor current decreases. When the output voltage (VOUT) is disturbed, such as when the output voltage suddenly drops, the output signal of the EA amplifier increases. The time when the slope-compensated signal is lower than the output signal of the EA amplifier will be prolonged, that is, the on-time of the switching transistor is prolonged and the duty cycle is increased, thus modulating the output voltage to the normal state.

[0066] The CLK_IN pin allows the converter to synchronize with an external clock (the output clock of another converter), and the CLK_OUT signal can be connected to the CLK_IN pin of the next converter to adjust the frequency and phase of the entire system.

[0067] The specific principle behind phase shifting of the input clock signal is as follows: The clock frequency of a buck converter is constant, for example, always maintained at 1MHz. In this case, using a phase-shifting circuit to delay the input clock signal allows for phase shifting. For example, to achieve a 180° phase shift, the input clock is delayed by 500ns using a phase-shifting circuit (this can be achieved by adjusting the capacitor size). The final output clock signal is then connected to the loop control circuit (e.g., a trigger) in the next cascaded converter. There, it is calibrated with the clock output from the oscillator circuit within the next converter via a phase-locked loop (PLL) to complete the phase shift.

[0068] As one specific embodiment, four buck converters are connected in parallel, with a clock phase difference of 90° between each converter. Figure 5 As shown. By adjusting the voltage signal input to the PHMODE pin of each converter to a voltage greater than V3 and less than V4, the phase shift circuit inside the converter will delay the clock signal by a corresponding time.

[0069] The phase-shifting circuit provided by this invention is added to a buck switching converter, which enables the converter to operate in multiple phases, thereby avoiding the situation where the load current is insufficient and multiple phases need to be cascaded to provide the load current required for engineering applications.

[0070] Multiphase operation allows multiple converters to operate in different phases while using minimal input and output capacitance. It operates from 20V to 4V and is suitable for point-of-load power applications with dual, triple, or quad lithium-ion battery inputs and 12V or 5V power rails. For applications requiring more than the maximum output load current of a single converter, multiple converters can be cascaded to operate in different phases, thereby providing more output current.

[0071] In summary, this invention creatively introduces a phase-shifting circuit with adjustable phase shift angle into a buck switching converter. An oscillator circuit is set in the first buck switching converter to generate its own clock signal. Combined with the pulse signal generated by the pulse modulation control circuit, the fixed on-time of the power transistor is controlled. Furthermore, multiple buck switching converters are connected in parallel. Therefore, this invention can perform multi-phase operation with multiple phases, providing sufficient load current required for engineering applications, and canceling out inductor current ripple, resulting in smaller output voltage ripple.

[0072] An embodiment of the present invention provides a converter chip, the converter chip comprising: a buck switching converter group in peak current mode; and a selection switch for selecting the 1st to the kth buck switching converter from N parallel-connected buck switching converters in the buck switching converter group, wherein 1 <k≤N。

[0073] Specifically, based on actual needs, the first k buck converters can be selected from N parallel-connected buck converters using a selector switch to form a k-phase output signal. Here, k is an integer. When k = 4, the phase shift angle of the phase-shifting circuit is adjusted to 90°.

[0074] In summary, this invention creatively applies a phase-shifting circuit to multiple parallel circuits, creating various phase-shifting options. This allows the inductor current ripple to be canceled out when multiple circuits are connected in parallel, resulting in smaller output voltage ripple and providing sufficient load current for engineering applications.

[0075] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0076] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0077] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a microcontroller, chip, or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0078] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0079] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0080] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A phase-shifting circuit, characterized in that, The phase-shifting circuit includes: a delay phase-shifting module comprising multiple delay phase-shifting units; a decoder, the input terminals of which are connected to different input voltage signals, and multiple output terminals of which are respectively connected to the control terminals of the multiple delay phase-shifting units; a first comparator, the positive input terminal of which is connected to the output terminal of the delay phase-shifting module, and the negative input terminal of which is connected to a first reference voltage; and a first flip-flop, the R input terminal of which is connected to a clock signal, the output terminal of which is connected to the input terminal of the delay phase-shifting module, and the S input terminal of which is connected to the output terminal of the first comparator. The decoder is used to control the corresponding delay-phase shifting unit among the plurality of delay-phase shifting units to turn on in response to a specific input voltage signal, so as to output a phase-shifted clock signal through the first comparator. The decoder includes: n second comparators, the negative inputs of which are respectively connected to n input voltage signals, and the positive inputs of which are connected to each other; and n logic gate combinations. The i-th logic gate combination includes ni NOT gates and 1 AND gate, wherein the number of input terminals of the AND gate is n, the output terminals of the 1st to i-th second comparators are directly connected to the 1st to i-th input terminals of the AND gate, and the (i+1)th to nth input terminals are connected to the (i+1)th to nth input terminals of the AND gate through corresponding NOT gates.

2. The phase-shifting circuit according to claim 1, characterized in that, The plurality of delay-phase-shifting units include: a shared complementary MOSFET; a plurality of parallel capacitor circuits, each capacitor circuit including a capacitor and a switching unit, and one end of each capacitor circuit being connected to the drain of the complementary MOSFET; a plurality of output terminals of the decoder being respectively connected to the control terminals of the switching units in the plurality of parallel capacitor circuits; the positive input terminal of the first comparator being connected to the drain of the complementary MOSFET; and the output terminal of the first flip-flop being connected to the gate of the complementary MOSFET. The decoder is used to control the switching unit on one of the multiple parallel capacitor circuits to close in response to the specific input voltage signal, thereby turning on the corresponding capacitor circuit.

3. The phase-shifting circuit according to claim 2, characterized in that, The complementary MOS transistors include PMOS transistors and NMOS transistors. The plurality of delay phase-shifting units further include: a common current source, the current source being connected to the source of the PMOS transistor, and the source of the NMOS transistor being grounded.

4. A buck converter bank in peak current mode, characterized in that, The buck switching converter group comprises: N buck switching converters connected in parallel, where N is an integer greater than 1. The buck switching converter includes: a main circuit; a pulse modulation control circuit, one input terminal of which is connected to a voltage feedback point external to the output terminal of the main circuit; a loop control circuit, the output terminal of which is connected to the gates of the upper and lower power transistors of the main circuit; and a phase shifting circuit according to any one of claims 1-3, wherein the clock input terminal of the phase shifting circuit is connected to the first input terminal of the loop control circuit, and the output terminal of the pulse modulation control circuit is connected to the second input terminal of the loop control circuit, wherein the phase shift angle of the phase shifting circuit is 360° / N. In any two adjacent buck switching converters, the clock output of the phase shift circuit in the first converter is connected to the clock input of the phase shift circuit in the second converter. The first step-down switching converter also includes an oscillator circuit, the clock signal output of which is connected to the first input of the loop control circuit to generate the initial clock signal.

5. The step-down switching converter group according to claim 4, characterized in that, The pulse modulation control circuit includes: an error amplifier, the negative input terminal of which is connected to the voltage feedback point, and the positive input terminal of which is connected to the target feedback voltage; and a PWM comparator, one positive input terminal of which is connected to the output terminal of the CCVS of the main circuit, and the output terminal of which is connected to the second input terminal of the loop control circuit.

6. The step-down switching converter group according to claim 5, characterized in that, The other positive input terminal of the PWM comparator is connected to the ramp signal output terminal of the oscillator circuit.

7. The step-down switching converter group according to claim 4, characterized in that, The N parallel-connected buck switching converters have the same structure, and the buck switching converter further includes: The switching module includes a switching unit and a switching control circuit. The clock output of the oscillator circuit is connected to the first input of the loop control circuit via the switching unit. The corresponding switching unit is closed by the switch control circuit in the first buck switching converter; the corresponding switching unit is opened by the switch control circuit in the other buck switching converters.

8. The step-down switching converter group according to claim 7, characterized in that, The switch control circuit includes: a third comparator, the positive input terminal of which is connected to a selection signal, the negative input terminal of which is connected to a second reference voltage, and the output terminal of which is connected to the control terminal of the switch unit.

9. The step-down switching converter group according to claim 4, characterized in that, The loop control circuit includes a second flip-flop, the first input terminal is an S input terminal, and the second input terminal is an R input terminal.

10. A converter chip, characterized in that, The converter chip includes: A buck switching converter bank in peak current mode according to any one of claims 4-9; and A selection switch is used to select the 1st to the kth buck switch converter from the N parallel-connected buck switch converters in the buck switch converter group, wherein 1 <k≤N。

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