Operational amplifier, chip and electronic device

Abstract

The invention discloses an operational amplifier, a chip and an electronic device, and the operational amplifier comprises an input differential pair module, a tail current source module, a bias current source module, a current mirror module, a common-gate module, a common-gate load module, a transconductance linear ring module and a Class AB output stage module. The static bias current provided by the bias current source module comprises IPTAT current, the expression of the IPTAT current is IPTAT = I0 + k0 * (T-T0), k0 is a slope and is a positive value, T0 is 300K, I0 represents current at 300K, and k0 is set to enable the temperature coefficient of transconductance of the operational amplifier to become a constant. According to the high-bandwidth operational amplifier, the temperature excursions of gain, margin, bandwidth and transconductance indexes of the high-bandwidth operational amplifier in a full temperature range can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an operational amplifier circuit, a chip and an electronic device. Background Art

[0002] With the development of complementary metal oxide semiconductor (CMOS) integrated circuit technology, electronic products are increasingly used in daily life and have become an indispensable part of various fields. The development goal of the increasingly miniaturized CMOS integrated circuit chip determines that high performance and high integration have become the important direction of CMOS integrated circuit development.

[0003] High-bandwidth operational amplifier circuits are widely used in ICs such as power management, ADCDAC, and interface circuits. Due to their large output voltage range and strong output voltage Sink-Source capability, this type of operational amplifier has a wider application range and stronger compatibility.

[0004] Conventional high bandwidth operational amplifier circuits such as Figure 1 shown. Figure 1 It is the most common high-bandwidth op amp circuit, and its structure consists of a folded cascode op amp input stage plus a translinear loop class AB output stage.

[0005] The analysis of the impact of the operational amplifier temperature on the frequency characteristics is summarized as follows. Since the characteristics of MOS devices are greatly affected by temperature, the following analysis is only for the MOS devices: ①The effect of temperature on the threshold voltage Vth is: the threshold voltage Vth gradually decreases as the temperature increases;

[0006] ②The effect of temperature on the gate-source voltage Vgs is: the gate-source voltage Vgs gradually decreases as the temperature increases; ③ Temperature proportional adjustment coefficient K P The influence is: proportional adjustment coefficient K P It gradually decreases with increasing temperature; ④The influence of temperature on the source-drain current Ids is: For source-drain current, when Vgs is small, it is mainly affected by the change of Vth, and the source-drain current increases with the increase of temperature; when the current is biased by the current mirror, it is mainly affected by Vth. When Vgs is large, it is mainly affected by K P The source-drain current decreases as the temperature increases.

[0007] ⑤ Effect of temperature on transconductance g m The impact is: Transconductance g m The calculation formula is as follows: (1) Where: μ is the channel mobility; T is the temperature in K; T0 is 300 K; C ox is the dielectric constant; W / L is the width-to-length ratio of the device, I ds is the source-drain current.

[0008] From formula (1), we can get: transconductance g m It gradually decreases as the temperature rises.

[0009] ⑥The influence of temperature on resistance: Effect of temperature on the drain-source resistance r of MOS devices o The influence is as follows: (2) Among them, V E is the Early voltage; λ is the channel length modulation coefficient. o It has a positive temperature coefficient of about 0.1% / °C, so the resistance r increases with temperature. o The resistance value of the folded cascode output resistor R OUT As the temperature rises, the |Vgs| of the PMOS tube MP5 and the NMOS tube MN7 decreases, and the |Vgs| of the corresponding PMOS tube MP8 and the NMOS tube MN10 increases. The gate voltage of the PMOS tube MP8 / NMOS tube MN10 changes by about 0.75mV / ℃, corresponding to the voltage (V GSMP6 +V GSMP7 or V GSMN8 +V GSMN9 ) range is 2*V GS ≈1.4V (where V GS is the conduction voltage drop of the diode, which is 0.7V); where: V GSMP6 is the gate-source voltage of PMOS tube MP6, V GSMP7 is the gate-source voltage of PMOS tube MP7, V GSMN8 is the gate-source voltage of NMOS tube MN8, V GSMN9 is the gate-source voltage of NMOS tube MN9.

[0010] Output resistance R OUT The calculation of is as follows: (3) Where: V is voltage and I is current.

[0011] From formula (3), we can see that when the change of ΔV with temperature is 0.75 / 1400 (i.e. 0.05%) per degree Celsius, combined with the above two aspects of analysis, the change of gain, main pole, secondary point, zero point and bandwidth with temperature is further analyzed as follows: The formula for gain is as follows: (4) Where: Av is the gain, r o is the device output impedance, R L For load resistance, the corresponding NMOS / PMOS tube codes are added to each parameter subscript to further distinguish the meaning of the parameters, such as g mp8 represents the transconductance of the PMOS tube MP8, g mn1,2 It represents the transconductance of PMOS tube MP1 or MP2 (the transconductance of these two tubes is equal). The specific meanings of other parameters in this formula and other formulas are deduced accordingly.

[0012] From formula (4), we can see that the gain decreases gradually with increasing temperature.

[0013] The formula for the dominant pole is as follows: (5) Where: R out1 is the output impedance of the first stage of the op amp, R out2 is the output impedance of the second stage of the op amp, C C is the capacitance of the compensation capacitor.

[0014] From formula (5), we can see that the main pole gradually moves away from the origin as the temperature increases.

[0015] The formula for the sub-pole is as follows: (6) From formula (6), we can see that the secondary point gradually approaches the origin as the temperature increases. The formula for the zero point is as follows: (7) Where: R Z is the zero adjustment resistor.

[0016] From formula (7), we can see that the zero point gradually approaches the origin as the temperature increases.

[0017] The formula for bandwidth is as follows: (8) From formula (7), we can see that the bandwidth decreases as the temperature increases.

[0018] Therefore, according to Figure 1 The traditional high-bandwidth op amp design has large temperature drift in gain, margin, bandwidth, transconductance and other indicators over the entire temperature range. Summary of the invention

[0019] In view of this, the technical problem to be solved by the present invention is to provide an operational amplifier, a chip and an electronic device, which at least to a certain extent solve one of the technical problems existing in the prior art.

[0020] The inventive concept of the present application is: firstly, the required IPTAT (proportional to absolute temperature) current proportional to the absolute temperature is generated by combining a positive temperature coefficient current and a zero temperature coefficient current, so as to improve the technical problem that the transconductance has a large temperature drift in the whole temperature range; further, the temperature compensation of the output impedance of the first-stage operational amplifier is realized by cooperating with the translinear loop through the IPTAT current, so as to improve the technical problem that the gain, bandwidth and transconductance have a large temperature drift in the whole temperature range; and then the temperature compensation of the zero point is realized through the positive temperature coefficient compensation resistor, so as to improve the technical problem that the margin has a large temperature drift in the whole temperature range.

[0021] As a first aspect of the present invention, an embodiment of an operational amplifier is provided as follows: An operational amplifier, characterized by comprising: An input differential pair module, comprising two input terminals, for detecting, amplifying and performing common-mode noise suppression processing on the difference of input signals at the two input terminals and then outputting the difference; A tail current source module, connected to the input differential pair module, and used to provide a bias current for the input differential pair module; A common-gate module connected to the input differential pair module; A common-gate load module, connected to the common-gate module, to provide a load for the common-gate module; A current mirror module, connected to the input differential pair module and the common-gate module at the same time, and forming a common-source common-gate current mirror load structure with the common-gate module, for providing a load for the input differential pair module and providing a bias current for the common-gate module; A bias current source module, connected to the current mirror module, the common-gate module and the common-gate load module, for providing a static bias current for the current mirror module and a bias voltage for the common-gate module and the common-gate load module; A translinear loop module, connected to the current mirror module, the common-gate module and the common-gate load module, for providing a bias voltage for the Class AB output stage module; A Class AB output stage module is connected to the input differential pair module via the translinear loop module, and is used to amplify and improve the driving capability of the signal output by the input differential pair module and then output it under the control of the bias voltage output by the translinear loop module; Wherein: the static bias current provided by the bias current source module includes the IPTAT current, and the expression of the IPTAT current is IPTAT =I0+k0×(T-T0), k0 is the slope and is a positive value, T0 is 300K, I0 represents the current at 300K, and k0 is set to make the temperature coefficient of the transconductance of the operational amplifier a constant.

[0022] Preferably, k0 is 10nA / K, and the corresponding I0 is 2uA.

[0023] Furthermore, the static bias current also includes a compensation current I notemp , used to adjust the compensation current I notemp The size of changes the proportion of the IPTAT current to the static bias current, thereby reducing the temperature variation of the sub-pole, zero point and bandwidth of the operational amplifier.

[0024] Preferably, the translinear loop module includes: an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, a first bias current Ibias1, and a second bias current Ibias2; the eighth PMOS tube MP8 and the tenth PMOS tube MP10 are in a current mirror connection structure, the source of the ninth PMOS tube MP9 is connected to the power supply voltage, and the gate and the drain are simultaneously connected to the source of the tenth PMOS tube MP10, and the tenth PMOS tube MP10 The drain of the ninth NMOS tube MN9 is grounded through the first bias current Ibias1; the ninth NMOS tube MN9 and the tenth NMOS tube MN10 are current mirror connection structures, the source of the tenth NMOS tube MN10 is connected to the power supply voltage through the second bias current Ibias2, and the source is simultaneously connected to the gate and drain of the eleventh NMOS tube MN11, and the source of the eleventh NMOS tube MN11 is grounded; the eighth PMOS tube MP8 and the ninth NMOS tube MN9 are connected to the power supply voltage and the ground terminal through the current mirror module, the common-gate module and the common-gate load module to form a current path.

[0025] Further, the current value of the first bias current Ibias1 is configured to be equal to the current value of the second bias current Ibias2, the aspect ratio of the ninth NMOS tube MN9 is configured to be equal to the aspect ratio of the tenth NMOS tube MN10, the aspect ratio of the ninth NMOS tube MN9 is configured to be equal to the aspect ratio of the tenth NMOS tube MN10, and the effect of temperature on the margin and bandwidth of the operational amplifier is adjusted by setting the aspect ratio of the ninth PMOS tube MP9 and the aspect ratio of the eleventh NMOS tube MN11.

[0026] Preferably, the length-to-width ratio of the ninth PMOS transistor MP9 is 5, and the length-to-width ratio of the eleventh NMOS transistor MN11 is 10.

[0027] Preferably, the Class AB output stage module includes: an eleventh PMOS tube MP11, a twelfth NMOS tube MN12, a first compensation resistor Rz1, a second compensation resistor Rz2, a first compensation capacitor Cc1, a second compensation capacitor Cc2, a load resistor RL and a load capacitor CL; the gate and drain of the eleventh PMOS tube MP11 are connected through the first compensation resistor Rz1 and the first compensation capacitor Cc1 connected in series; the gate and drain of the twelfth NMOS tube MN12 are connected through the second compensation resistor Rz2 and the second compensation capacitor Cc2 connected in series; the source of the eleventh PMOS tube MP11 is connected to the power supply voltage, the drain is connected to the drain of the twelfth NMOS tube MN12, the source of the twelfth NMOS tube MN12 is grounded, the load resistor RL and the load capacitor CL are connected in parallel and connected between the drain and source of the twelfth NMOS tube MN12; the bias voltage of the gate of the eleventh PMOS tube MP11 and the bias voltage of the gate of the twelfth NMOS tube MN12 are provided by the translinear loop module.

[0028] Furthermore, the first compensation resistor Rz1 and / or the second compensation resistor Rz2 are resistors with positive temperature coefficients.

[0029] As a second aspect of the present invention, the embodiment and technical solution of the chip provided are as follows: A chip, comprising: an operational amplifier as described in any one of the first aspects above.

[0030] As a third aspect of the present invention, the technical solution of the embodiment of the electronic device provided is as follows: An electronic device, comprising: an operational amplifier as described in any one of the second aspects above.

[0031] Furthermore, the electronic device is a switching power supply.

[0032] The difference between the embodiment of the present invention and the prior art is that the static bias current provided by the bias current source module is changed from a constant current source current to an IPTAT current, and the expression of the IPTAT current is I PTAT =I0+k0×(T-T0). By setting k0, the temperature coefficient of the operational amplifier transconductance can be made constant, so that it no longer changes with temperature, thereby improving the technical problem of large temperature drift of transconductance in the whole temperature range.

[0033] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is the schematic diagram of the traditional high bandwidth operational amplifier circuit; Figure 2 is a structural block diagram of an operational amplifier circuit according to a first embodiment of the present invention; Figure 3 is a specific circuit diagram of the operational amplifier circuit of the first embodiment of the present invention; Figure 4 for Figure 3 The variation trend diagram of the bias current and bias voltage provided by the tail current source module in the circuit within the full temperature variation range; Figure 5 for Figure 3 A schematic diagram of the size design of each MOS tube in the translinear loop module and Class AB output stage module in the circuit.

[0035] Description of reference numerals: VIN: input signal, VOUT: output signal, VCC: power supply voltage, GND: ground, MN1: first NMOS tube, MN2: second NMOS tube, MN3: third NMOS tube, MN4: fourth NMOS tube, MN5: fifth NMOS tube, MN6: sixth NMOS tube, MN7: seventh NMOS tube, MN8: eighth NMOS tube, MN9: ninth NMOS tube, MN10: tenth NMOS tube, MN11: eleventh NMOS tube, MN12: twelfth NMOS tube, MP1: first PMOS tube, MP2: second PMOS tube, MP3: third PMOS tube, MP4: fourth PMOS tube , MP5: fifth PMOS tube, MP6: sixth PMOS tube, MP7: seventh PMOS tube, MP8: eighth PMOS tube, MP9: ninth PMOS tube, MP10: tenth PMOS tube, MP11: eleventh PMOS tube, R1: first resistor, R2: second resistor, R3: third resistor, Q1: first transistor, Q2: second transistor, OP1, first operational amplifier, Ibias1: first bias current, Ibias2: second bias current, Rz1: first compensation resistor, Rz2: second compensation resistor, Cc1: first compensation capacitor, Cc2: second compensation capacitor:, RL: load resistor, CL: load capacitor. DETAILED DESCRIPTION

[0036] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0037] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application are described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0039] It should be understood that, in the specification, claims and drawings, when a step is described as being connected to another step, the step may be directly connected to the other step, or be connected to the other step through a third step; when an element / unit is described as being "connected" to another element / unit, the element / unit may be "directly connected" to the other element / unit, or be "connected" to the other element / unit through a third element / unit.

[0040] In addition, the drawings of the present disclosure are only schematic diagrams of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in one or more hardware modules or integrated circuits.

[0041] First embodiment The present embodiment provides an operational amplifier circuit, including an input differential pair module, a tail current source module, a bias current source module, a current mirror module, a common gate module, a common gate load module, a translinear loop module and a Class AB output stage module, wherein: the tail current source module adopts an IPTAT current with temperature coefficient compensation, and the Class AB output stage module loop compensation adopts a combination of positive temperature coefficient resistors and zero temperature coefficient resistors.

[0042] Figure 2 FIG. 1 is a block diagram of the operational amplifier circuit of the first embodiment of the present invention. Figure 2 , which include: The input differential pair module 101 includes two input terminals, and is used to detect, amplify and perform common mode noise suppression processing on the difference of input signals at the two input terminals before outputting the result; The tail current source module 102 is connected to the input differential pair module 101 and is used to provide a bias current for the input differential pair module; The common-gate module 103 is connected to the input differential pair module 101; The common-gate load module 104 is connected to the common-gate module 103 to provide a load for the common-gate module 103; The current mirror module 105 is connected to the input differential pair module 101 and the common-gate module 103 at the same time, and forms a common-source common-gate current mirror load structure with the common-gate module 103, so as to provide a load for the input differential pair module 101 and a bias current for the common-gate module 103; The bias current source module 100 is connected to the current mirror module 105, the common-gate module 103 and the common-gate load module 104, and is used to provide a static bias current for the current mirror module 105, and provide a bias voltage for the common-gate module 103 and the common-gate load module 104; The translinear loop module 106 is connected to the current mirror module 105, the common-gate module 103 and the common-gate load module 104, and is used to provide a bias voltage for the Class AB output stage module 107; The Class AB output stage module 107 is connected to the input differential pair module 101 through the translinear loop module 106, and is used to amplify and improve the driving capability of the signal output by the input differential pair module 101 under the control of the bias voltage output by the translinear loop module 106 before outputting it; Wherein: The static bias current provided by the bias current source module 100 includes the IPTAT current, and the expression of the IPTAT current is I PTAT =I0+k0×(T-T0), k0 is the slope and is a positive value, T0 is 300K, I0 represents the current at 300K, k0 is set to make the operational amplifier transconductance g m The temperature coefficient becomes a constant.

[0043] In this embodiment, the static bias current provided by the bias current source module is changed from a constant current source current to an IPTAT current, and the expression of the IPTAT current is I PTAT =I0+k0×(T-T0). By setting k0, the temperature coefficient of the operational amplifier transconductance can be made constant, so that it no longer changes with temperature, thereby improving the technical problem of large temperature drift of transconductance in the whole temperature range.

[0044] Figure 3 A specific circuit diagram of the operational amplifier circuit of the first embodiment of the present invention is shown in FIG. Figure 3 ,in: The input signal includes a differential signal Vin; The input differential pair module includes a first NMOS tube MN1 and a second NMOS tube MN2, the gate of the first NMOS tube is connected to one end of the differential signal, the source of the first NMOS tube is connected to the source of the second NMOS tube, the drain of the first NMOS tube serves as the first output of the input differential pair module, the gate of the second NMOS tube is connected to the other end of the differential signal, and the drain of the second NMOS tube serves as the second output of the input differential pair module; The tail current source module includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a third NMOS tube MN3, a fourth NMOS tube MN4, a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, a second transistor Q2 and a first operational amplifier OP1; the gate of the first PMOS tube is connected to the gates of the second PMOS tube and the second PMOS tube, the source of the first PMOS tube is connected to the power supply voltage, the drain of the first PMOS tube is connected to the first resistor R1, the source of the second PMOS tube is connected to the power supply voltage, the drain of the second PMOS tube is connected to the second resistor R2, the source of the third PMOS tube is connected to the power supply voltage, the drain of the third PMOS tube is connected to the drain of the third NMOS tube, the gate of the third NMOS tube is connected to the drain of the third NMOS tube, the source of the third NMOS tube is grounded, and the gate of the fourth NMOS tube is connected to the third NMOS tube. The gate of the S tube, the drain of the fourth NMOS tube is connected to the source of the first NMOS tube and the second NMOS tube, the source of the fourth NMOS tube is grounded, one end of the first resistor R1 is connected to the drain of the first PMOS tube, the other end of the first resistor R1 is connected to the collector of the first transistor Q1, one end of the second resistor R2 is connected to the drain of the second PMOS tube, the other end of the second resistor R2 is connected to the third resistor R3, the other end of the third resistor R3 is connected to the collector of the second transistor Q2, the base of the first transistor Q1 and the base of the second transistor Q2 are grounded, the emitter of the first transistor Q1 and the emitter of the second transistor Q2 are grounded, the non-inverting input end of the first operational amplifier OP1 is connected to the third resistor R3, the inverting input end of the first operational amplifier OP1 is connected to the collector of the first transistor Q1, and the output end of the first operational amplifier OP1 is connected to the gates of the first PMOS tube, the second PMOS tube, and the second PMOS tube; The common-gate module includes a sixth PMOS tube MP6 and a seventh PMOS tube MP7; the gate of the sixth PMOS tube and the gate of the seventh PMOS tube are connected to the bias current source module, the source of the sixth PMOS tube is connected to the first output, the drain of the sixth PMOS tube is connected to the drain of the fifth NMOS tube, the source of the seventh PMOS tube is connected to the second output, and the drain of the seventh PMOS tube is connected to the drain of the ninth NMOS tube; The common-gate load module includes a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7 and an eighth NMOS tube MN8; the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are connected to the bias current source module, the drain of the fifth NMOS tube is connected to the drain of the sixth PMOS tube, the source of the fifth NMOS tube is connected to the drain of the seventh NMOS tube, the drain of the sixth NMOS tube is connected to the source of the ninth NMOS tube, the source of the sixth NMOS tube is connected to the drain of the eighth NMOS tube, the gate of the seventh NMOS tube and the gate of the eighth NMOS tube are connected to the drain of the fifth NMOS tube, and the source of the seventh NMOS tube and the source of the eighth NMOS tube are grounded; The current mirror module includes a fourth PMOS tube MP4 and a fifth PMOS tube MP5; the gate of the fourth PMOS tube and the gate of the fifth PMOS tube are connected to the bias current source module, the source of the fourth PMOS tube and the source of the fifth PMOS tube are connected to the power supply voltage, the drain of the fourth PMOS tube is connected to the first output, and the drain of the fifth PMOS tube is connected to the second output; The translinear loop module includes an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, a first bias current Ibias1, and a second bias current Ibias2; the gate of the eighth PMOS tube is connected to the gate of the tenth PMOS tube, the source of the eighth PMOS tube is connected to the source of the seventh PMOS tube, the drain of the eighth PMOS tube is connected to the drain of the sixth NMOS tube, the gate of the ninth PMOS tube is connected to the drain of the ninth PMOS tube, the source of the ninth PMOS tube is connected to the power supply voltage, the source of the tenth PMOS tube is connected to the ninth PMOS tube, and the The drain of the tenth PMOS tube is connected to the input end of the first bias current Ibias1, the gate of the ninth NMOS tube is connected to the gate of the tenth NMOS tube, the drain of the ninth NMOS tube is connected to the drain of the seventh PMOS tube, the source of the ninth NMOS tube is connected to the drain of the sixth NMOS tube, the drain of the tenth NMOS tube is connected to the input end of the second bias current Ibias2, the source of the tenth NMOS tube is connected to the drain of the eleventh NMOS tube, the gate of the eleventh NMOS tube is connected to the drain of the eleventh NMOS tube, the source of the eleventh NMOS tube is grounded, the output end of the first bias current Ibias1 is grounded, and the input end of the second bias current Ibias2 is connected to the power supply voltage; The Class AB output stage module includes an eleventh PMOS tube MP11, a twelfth NMOS tube MP12, a first compensation resistor Rz1, a second compensation resistor Rz2, a first compensation capacitor Cc1, a second compensation capacitor Cc2, a load resistor RL and a load capacitor CL; the gate of the eleventh PMOS tube is connected to the source of the seventh PMOS tube, the source of the eleventh PMOS tube is connected to the power supply voltage, the drain of the eleventh PMOS tube is connected to the output voltage, the gate of the twelfth NMOS tube is connected to the drain of the sixth NMOS tube, the drain of the twelfth NMOS tube is connected to the output voltage, and the gate of the twelfth NMOS tube is connected to the drain of the sixth NMOS tube. The source of the OS tube is grounded, one end of the first compensation resistor Rz1 is connected to the gate of the eleventh PMOS tube, one end of the first compensation resistor Rz1 is connected to the first compensation capacitor Cc1, the other end of the first compensation capacitor Cc1 is connected to the output voltage, one end of the second compensation resistor Rz2 is connected to the gate of the twelfth NMOS tube, the other end of the second compensation resistor Rz2 is connected to the second compensation capacitor Cc2, the other end of the second compensation capacitor Cc2 is connected to the output voltage, one end of the load resistor RL and one end of the load capacitor CL are connected to the output voltage, and the other end of the load resistor RL and the other end of the load capacitor CL are grounded.

[0045] Figure 3 In the circuit, the folded cascode op amp input stage circuit composed of the input differential pair module 101, the tail current source module 102, the common gate module 103, the common gate load module 104, the current mirror module 105 and the bias current source module 100 is called the first stage, and the circuit composed of the translinear linear loop module 106 and the Class AB output stage module 107 is called the second stage. Figure 1 The circuit can also be divided into the first level and the second level by analogy.

[0046] Figure 3 The detailed requirements for the derivation and analysis and implementation of the gain, margin, bandwidth and transconductance of the operational amplifier are as follows: (1) Change the constant bias current Ibias provided by the constant current source to IPTAT current After changing the bias current Ibias to IPTAT current, the transconductance g m The temperature coefficient is as follows: (9) Among them: T0 is 300K, I ds is the source-drain current, and the right side of formula (9) is the transconductance g m The temperature coefficient of

[0047] From formula (9), we can know that g m As the temperature increases, it decreases. Therefore, the inventors of this application use the IPTAT current with a positive temperature coefficient to make g m The temperature coefficient of the resistor becomes a constant, thus canceling out the change in transconductance with temperature.

[0048] The relationship between IPTAT current and temperature can be expressed by fitting as the following univariate linear expression: (10) Among them, T0 is 300K, I0 represents the current at 300K, k0 is the slope and is a positive value, that is, the IPTAT current is a current with a positive temperature coefficient.

[0049] Through Ohm's law and transistor current formula, IPTAT current can also be derived as follows: (11) Where: V BE is the voltage difference between the base and emitter of transistor Q1 or transistor Q2, V T is the threshold voltage of the transistor, R is the resistance of resistor R3, k is the Boltzmann constant, q is the amount of electron charge, and n is the ratio of the number of switch tubes Q2 and Q1 connected in parallel. Figure 3 The middle switch tube Q2 and the switch tube Q1 are both single switch tubes, so n is 1.

[0050] According to formula (11), the expression of IPTAT current changing with temperature is: (12) It can be seen from formula (12) that the slope of the IPTAT current is inversely proportional to R. The slope of the IPTAT current in formula (10) can be modified by adjusting the resistor R3.

[0051] It should be noted that Figure 3 The static bias current provided by the circuit bias current source module 100 includes not only the IPTAT current with a positive temperature coefficient, but also a compensation current I notemp , which is used to compensate the IPTAT current with a positive temperature coefficient, thereby adjusting the total static bias current, that is, the total static bias current I bias The expression is as follows: (13) In specific implementation, formula (13) can be adjusted by I notemp The size of the positive temperature coefficient changes the proportion of the IPTAT current in the entire static bias current, making Figure 3 The circuit reduces the temperature variation of the secondary pole, zero and bandwidth by compensating the IPTAT current.

[0052] (2) Adjust the size of the translinear loop module device For point A across the linear loop, the following relationship exists: (14) Where: V gsp8 、V gsp9 、V gsp10 、V gsp11 They are the gate-source voltages of PMOS tubes MP8, MP9, MP10, and MP11 respectively.

[0053] When MP8 and MP10 form a current mirror relationship, the current of MP11 is also in mirror proportion to MP9. Therefore, with the injection of Ibias1 and PTAT current, the right side of formula (14) will gradually increase, and the voltage at point A will gradually move away from the power supply voltage.

[0054] Similar to point B, its voltage will gradually increase with the injection of Ibias2 and IPTAT currents.

[0055] For the designed two-stage op amp, point A corresponds to the output point of the folded cascode op amp, and the following relationship exists: (15) Where: V cc is the power supply voltage, V A is the voltage at point A, V sg9 is the source-gate voltage of MP9, V sg10 is the source-gate voltage of MP10.

[0056] Formula (15) can be further expressed as: (16) In the above formula, V caused by the lining bias effect is ignored. TH Different, μ n is the mobility of the NMOS tube, and (W / L) is the aspect ratio of the MOS tube.

[0057] In addition, for point A of the translinear loop, due to formula (14), when MP8 and MP10 are in a current mirror relationship, the current of MP11 is also in a mirror ratio with MP9. Therefore, the circuit of the translinear loop is similar to a cascode current mirror.

[0058] Assume that the W / L ratio of MP8 and MP10 is a, the W / L ratio of MN9 and MN10 is b, the current split ratio of MP5 and MN7 is c / d, c+d=1, and the current flowing through point A is I A。

[0059] Then the current flowing through MP8 is c×I A , the current flowing through MN9 is d×I A .

[0060] The expressions of Ibias1 and Ibias2 are as follows: (17) Substituting formula (17) into formula (16) yields: (18) From formula (18), the output resistance at point A can be obtained as follows: (19) It can be seen from formula (17) that by adjusting the shunt ratio c / d of MP5 and MN7, the size of MP5, MP6 and MP7 can adjust the output resistance of point A.

[0061] Similarly, the output resistance at point B can be obtained as follows: (20) for Figure 3 For the operational amplifier, the first-stage output includes points A and B. The output impedances of points A and B are as shown in the above formulas. The currents flowing through points A and B are the same. When temperature compensation is performed, the currents flowing through points A and B increase, the voltage at point A decreases, the voltage at point B increases, and the output impedances of points A and B increase, thus achieving temperature compensation.

[0062] The first stage output impedance R out1 Temperature compensation is performed, thereby achieving compensation for the gain and bandwidth of the operational amplifier within the full temperature range, and reducing the temperature drift of the gain and bandwidth of the operational amplifier.

[0063] When designing, set ibias1=ibias2, and adjust the split ratio of MP8 and MN9 to 1:1, (W / L) MP8 :(W / L) MP10 =1:1, (W / L) MN10 :(W / L) MN9 =1:1, by adjusting (W / L) first MP9 and (W / L) MN11 The size ensures that the circuit DC operating point is correct, and then fine-tuned (W / L) MP9 and (W / L) MN11 size improves the temperature drift of the op amp's gain and bandwidth.

[0064] (3) Loop compensation uses resistors with temperature coefficients Figure 3 The formula for the zero point is as follows: From formula (21), we can see that the addition of temperature coefficient resistor will affect fz, but will not affect other parameters. Figure 3The temperature coefficients of the first compensation resistor Rz1 and the second compensation resistor Rz2 must be temperature compensated to achieve zero point compensation in the full temperature range, thereby affecting the phase margin.

[0065] It should be noted that Figure 3 The first compensation resistor Rz1 and the second compensation resistor Rz2 in the output stage module of the circuit Class AB are both resistors composed of a positive temperature coefficient resistor and a zero temperature coefficient resistor. In a specific implementation, the first compensation resistor Rz1 and the second compensation resistor Rz2 as a whole exhibit the characteristics of a positive temperature coefficient resistor by adjusting the proportion of the positive temperature coefficient resistor.

[0066] In summary, through the above three methods, the transconductance g can be realized m , the first stage output impedance R OUT1 And the second stage compensation resistor R Z Temperature compensation is achieved to compensate for gain, margin, transconductance and bandwidth over the full temperature range.

[0067] The above theoretical analysis discusses how the present invention achieves the purpose of the invention, and the following experimental data demonstrates the beneficial effects of the present invention.

[0068] (1) Experiment 1, using Figure 1 Traditional Operational Amplifier The frequency response of the circuit at -40℃, 27℃ and 125℃ obtained by simulation is shown in Table 1:

[0069] Table 1 It can be seen from Table 1 that these four indicators, especially the bandwidth, vary greatly over the entire temperature range, and their variation trends with temperature are consistent with the previous analysis.

[0070] (2) Experiment 2: Figure 1 The bias current Ibias is changed to Figure 3 The PTAT current of the other circuit designs is the same as that of Experiment 1. It has been analyzed above that the slope of the IPTAT current can be modified by adjusting the resistance value of the resistor R3, thereby improving the temperature characteristics of the transconductance. After repeated debugging and simulation verification, the inventor of the present application found that when k0 is 10nA / K and the bias current is 2uA, the IPTAT current expression after substituting into formula (10) is: (twenty two) At this time, the bias current and bias voltage provided by it change within the full temperature range as follows Figure 4 , where the horizontal axis is temperature and the vertical axis is bias voltage. Figure 4It can be seen that the slope of the bias current changes with temperature. Using the slope in formula (22), the frequency response of the circuit at -40℃, 27℃ and 125℃ is simulated as shown in Table 2:

[0071] Table 2 It can be seen that the transconductance index in Table 2 achieves the compensation effect at full temperature compared with that in Table 1.

[0072] (3) Experiment 3: Figure 1 The bias current Ibias is changed to Figure 3 The PTAT current and the device size in the fine-tuning translinear loop module are the same as those in Experiment 1. Will Figure 1 The bias current Ibias is changed to Figure 3 The PTAT current has been verified above and will not be repeated here. The fine-tuning (W / L) has been analyzed above. MP9 and (W / L) MN11 The size improves the gain and bandwidth temperature drift of the operational amplifier. The inventor of this application has repeatedly debugged and simulated the circuit design (W / L) MP9 =5 and (W / L) MN11 =1 to obtain a better compensation effect, and each MOS tube of the translinear loop module adopts Figure 5 The dimensions in the figure are shown in Table 3. The frequency responses of the circuits at -40°C, 27°C and 125°C are simulated as follows:

[0073] Table 3 It can be seen that compared with the gain, bandwidth and transconductance indicators in Table 1, Table 3 achieves the compensation effect at full temperature.

[0074] (4) Experiment 4: The loop compensation uses resistors with temperature coefficients. The other circuit designs are the same as Experiment 1. The first compensation resistor Rz1 and the second compensation resistor Rz2 are both changed to a combination of a positive temperature coefficient resistor and a zero temperature coefficient resistor, the proportion of the positive temperature coefficient resistor is adjusted, and the position of the zero point in the full temperature range is adjusted. The MOS tubes of the Class AB output stage module adopt Figure 5 The dimensions in the figure are shown in Table 4. The frequency responses of the circuits at -40°C, 27°C and 125°C are simulated as follows:

[0075] Table 4 It can be seen that compared with the margin indicators in Table 1, Table 4 achieves the compensation effect at full temperature.

[0076] (5) Experiment 5, combining the techniques of Experiments 2 to 4 At this time, the simulation results show the frequency response of the circuit at -40℃, 27℃ and 125℃ as shown in Table 5:

[0077] Table 5 It can be seen that compared with Table 1, the gain, margin, bandwidth and transconductance indicators in Table 5 achieve the compensation effect at full temperature, and the temperature drift is reduced.

[0078] Second embodiment This embodiment provides a chip, which includes any operational amplifier in the first embodiment.

[0079] Since this embodiment includes any operational amplifier in the first embodiment, it is beneficial to improve the temperature characteristics of the product to a certain extent.

[0080] Third embodiment This embodiment provides an electronic device, which includes any operational amplifier in the first embodiment.

[0081] Since this embodiment includes any operational amplifier in the first embodiment, it is beneficial to improve the temperature characteristics of the product to a certain extent.

[0082] The above are only preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be regarded as limitations of the present invention, and the protection scope of the present invention should be based on the scope defined by the claims. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the spirit and scope of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. An operational amplifier, characterized in that: include: An input differential pair module (101) comprises two input terminals, and is used to detect, amplify and perform common mode noise suppression processing on the difference of input signals at the two input terminals and then output the result; A tail current source module (102), connected to the input differential pair module (101), and used to provide a bias current for the input differential pair module; A common-gate module (103) connected to the input differential pair module (101); A common-gate load module (104) is connected to the common-gate module (103) and provides a load for the common-gate module (103); A current mirror module (105) is connected to the input differential pair module (101) and the common-gate module (103) at the same time, and forms a common-source common-gate current mirror load structure with the common-gate module (103), and is used to provide a load for the input differential pair module (101) and a bias current for the common-gate module (103); A bias current source module (100) is connected to the current mirror module (105), the common-gate module (103) and the common-gate load module (104) at the same time, and is used to provide a static bias current for the current mirror module (105), and to provide a bias voltage for the common-gate module (103) and the common-gate load module (104); A translinear loop module (106) is connected to the current mirror module (105), the common-gate module (103) and the common-gate load module (104) and is used to provide a bias voltage for the Class AB output stage module (107); A Class AB output stage module (107) is connected to the input differential pair module (101) via the translinear loop module (106) and is used to amplify and improve the driving capability of the signal output by the input differential pair module (101) and then output it under the control of the bias voltage output by the translinear loop module (106); Wherein: the static bias current provided by the bias current source module (100) includes an IPTAT current, and the expression of the IPTAT current is I PTAT =I0+k0×(T-T0), k0 is the slope and is a positive value, T0 is 300K, I0 represents the current at 300K, and k0 is set to make the temperature coefficient of the transconductance of the operational amplifier a constant.

2. The operational amplifier according to claim 1, characterized in that: k0 is 10nA / K, and the corresponding I0 is 2uA.

3. The operational amplifier according to claim 1, characterized in that: The static bias current also includes a compensation current I notemp , used to adjust the compensation current I notemp The size of changes the proportion of the IPTAT current to the static bias current, thereby reducing the temperature variation of the sub-pole, zero point and bandwidth of the operational amplifier.

4. The operational amplifier according to claim 1, characterized in that: The translinear loop module (106) comprises: an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, a first bias current Ibias1, and a second bias current Ibias2; the eighth PMOS tube MP8 and the tenth PMOS tube MP10 are in a current mirror connection structure, the source of the ninth PMOS tube MP9 is connected to a power supply voltage, and the gate and drain are simultaneously connected to the source of the tenth PMOS tube MP10, and the drain of the tenth PMOS tube MP10 is connected to the first The bias current Ibias1 is grounded; the ninth NMOS tube MN9 and the tenth NMOS tube MN10 are in a current mirror connection structure; the source of the tenth NMOS tube MN10 is connected to the power supply voltage through the second bias current Ibias2, and the source is simultaneously connected to the gate and drain of the eleventh NMOS tube MN11; the source of the eleventh NMOS tube MN11 is grounded; the eighth PMOS tube MP8 and the ninth NMOS tube MN9 are connected to the power supply voltage and the ground terminal through the current mirror module (105), the common gate module (103) and the common gate load module (104), thereby forming a current path.

5. The operational amplifier according to claim 4, characterized in that: The current value of the first bias current Ibias1 is configured to be equal to the current value of the second bias current Ibias2, the aspect ratio of the ninth NMOS tube MN9 is configured to be equal to the aspect ratio of the tenth NMOS tube MN10, the aspect ratio of the ninth NMOS tube MN9 is configured to be equal to the aspect ratio of the tenth NMOS tube MN10, and the influence of temperature on the gain and bandwidth of the operational amplifier is adjusted by setting the aspect ratio of the ninth PMOS tube MP9 and the aspect ratio of the eleventh NMOS tube MN11.

6. The operational amplifier according to claim 5, characterized in that: The length-to-width ratio of the ninth PMOS transistor MP9 is 5, and the length-to-width ratio of the eleventh NMOS transistor MN11 is 10.

7. The operational amplifier according to any one of claims 1 to 6, characterized in that: The Class AB output stage module (107) comprises: an eleventh PMOS transistor MP11, a twelfth NMOS transistor MN12, a first compensation resistor Rz1, a second compensation resistor Rz2, a first compensation capacitor Cc1, a second compensation capacitor Cc2, a load resistor RL, and a load capacitor CL; the gate and drain of the eleventh PMOS transistor MP11 are connected via the first compensation resistor Rz1 and the first compensation capacitor Cc1 connected in series; the gate and drain of the twelfth NMOS transistor MN12 are connected via the second compensation resistor Rz2 and the second compensation capacitor Cc2 connected in series. The second compensation capacitor Cc2 is connected; the source of the eleventh PMOS tube MP11 is connected to the power supply voltage, the drain is connected to the drain of the twelfth NMOS tube MN12, the source of the twelfth NMOS tube MN12 is grounded, the load resistor RL and the load capacitor CL are connected in parallel and connected between the drain and the source of the twelfth NMOS tube MN12; the bias voltage of the gate of the eleventh PMOS tube MP11 and the bias voltage of the gate of the twelfth NMOS tube MN12 are provided by the translinear loop module (106).

8. The operational amplifier according to claim 7, characterized in that: The first compensation resistor Rz1 and / or the second compensation resistor Rz2 are resistors with positive temperature coefficients.

9. A chip, characterized in that: The operational amplifier comprises the operational amplifier according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The operational amplifier comprises the operational amplifier according to any one of claims 1 to 8.

11. The electronic device according to claim 10, characterized in that: The electronic device is a switching power supply.

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