A process method for improving SiC MOSFET channel mobility and gate dielectric layer reliability

Abstract

The present invention relates to a process for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs, comprising forming a channel layer on an epitaxial layer using ion implantation; surface treating the SiC epitaxial layer using sacrificial oxidation; forming SiO2 on the SiC surface as a gate dielectric layer using a low-pressure chemical vapor deposition process; and performing a post-NO deposition annealing process on the gate dielectric layer. The SiC / SiO2 interface formed by the present invention has reduced roughness, avoiding the problem of carbon clusters and carbon particles generated in traditional thermal oxidation, reducing the interface state density, and thus enhancing channel carrier mobility. Furthermore, a step-by-step low-pressure chemical vapor deposition process is used to densify the gate dielectric layer between two or more deposition stages, fully decomposing precursor residues during deposition, releasing gate dielectric layer stress, reducing gate dielectric layer leakage, enhancing gate dielectric layer reliability, and improving device yield.

Description

Technical Field

[0001] This invention relates to a semiconductor device manufacturing process, and more particularly to a process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs. Background Technology

[0002] Silicon carbide has attracted widespread attention from industry and academia in recent years due to its wide bandgap, high critical breakdown field strength, and high thermal conductivity. Its industrialization prospects are broad, and SiC MOSFET devices have received great attention as the main devices.

[0003] However, due to the presence of carbon in silicon carbide and its large bandgap, the gate oxide interface state density of SiC / SiO2 is extremely high, typically 1-3 orders of magnitude higher than that of traditional Si / SiO2. This extremely high interface state density results in very low channel carrier mobility in the MOSFET, affecting the channel on-state characteristic resistance of the MOSFET device, and consequently, the on-state characteristic resistance of the MOSFET device.

[0004] Currently, it is believed that the SiC / SiO2 interface states originate from the chemical reaction between SiC and O2 during high-temperature oxidation to generate SiO2, while C clusters remain at the SiC / SiO2 interface, affecting the interface quality of SiC / SiO2.

[0005] Therefore, in order to avoid the formation of C clusters during the thermal oxidation process, the gate dielectric layer can be prepared directly by deposition. Generally, chemical deposition or physical deposition can be used to deposit oxides. However, although this method can avoid the formation of C clusters caused by the traditional thermal oxidation method, the density of the deposited gate dielectric layer is not as good as that of the thermal oxidation method, resulting in a larger gate leakage current and a serious reduction in gate reliability. Summary of the Invention

[0006] To address one or more of the technical problems of the prior art, this invention proposes a process method to improve the channel mobility and gate dielectric layer reliability of SiC MOSFETs.

[0007] According to an embodiment of the present invention, a process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs is proposed, characterized by comprising: Step S1, forming an epitaxial layer on a silicon carbide substrate having a first type of doping, wherein the doping type of the epitaxial layer can be either the first doping type or the second doping type; Step S2, forming a base region having a second doping type on the silicon carbide epitaxial layer having the first doping type by ion implantation, or forming a base region having the first doping type on the silicon carbide epitaxial layer having the second doping type by ion implantation; or directly using the epitaxial layer as the base region; Step S3, forming the source contact region and drain contact region of the MOSFET in the base region by ion implantation; when the base region has the first doping type, the source contact region and drain contact region formed by ion implantation have the second doping type; when the base region has the second doping type, the source contact region and drain contact region formed by ion implantation have the first doping type; Step S4, forming a body region in the base region by ion implantation, wherein the body region has the same doping type as the base region, and the doping concentration of the body region is 1×10⁻⁶. 19 ~1×10 21 cm -3 Step S5: The channel region is located between the source contact region and the drain contact region. While the source contact region and the drain contact region are formed by ion implantation, the channel region is naturally formed between the two contact regions. Step S6: The surface of the silicon carbide wafer is treated by sacrificial oxidation to reduce the formation of natural oxides and reduce the surface roughness of the silicon carbide wafer. Step S7: SiO2 is formed on the surface of the silicon carbide wafer as a gate dielectric layer by low-pressure chemical vapor deposition using tetraethyl orthosilicate as a deposition precursor. Step S8: The gate dielectric layer is annealed in an atmosphere of NO, N2, N2O, or NH3 after deposition. Step S9: Polysilicon is deposited on the gate dielectric layer by low-pressure chemical vapor deposition and annealed after deposition of the polysilicon by POCL3 to form the gate electrode. Step S10: Metal is deposited or sputtered in the source contact region, drain contact region, and body region, and ohmic contacts are formed by annealing.

[0008] Furthermore, in step S3, ion implantation of the source and drain contact regions of the MOSFET is performed at room temperature or 500°C, with an implantation angle of 7°, forming a junction depth of 0.2µm-0.5µm.

[0009] Furthermore, in step S4, ion implantation of the MOSFET body region is performed at room temperature or 500°C, with an implantation angle of 7°, forming a junction depth of 0.2µm-0.5µm and a doping concentration of 1×10⁻⁶. 19 ~1×10 21 cm -3 .

[0010] Furthermore, in step S7, the process flow of the low-pressure chemical vapor deposition process includes deposition to form a gate dielectric layer, post-deposition heating to densify the gate dielectric layer, first-step densification followed by cooling and re-deposition to prepare the gate dielectric layer, and second-step deposition followed by heating to densify the gate dielectric layer.

[0011] Further, in step S7, the deposition process temperature for forming the gate dielectric layer using low-pressure chemical vapor deposition is 640℃-690℃, and the deposition time is 8min-12min. After the first stage of deposition, the process temperature is increased to 750℃. During the heating process, the oxygen content is gradually increased while the precursor valve is gradually closed, and the precursor remaining in the furnace tube is removed. The pure oxygen environment is maintained at 750℃ for 30min-120min. Then, the process temperature is reduced to the deposition process temperature of 640℃-690℃ to restore the gas atmosphere to that used when depositing SiO2, i.e., the precursor flow rate is increased and the oxygen flow rate is reduced. The deposition time is 8min-12min. Afterward, the densification process is repeated, and the process temperature is increased to 750℃. During the heating process, the oxygen content is gradually increased while the precursor valve is gradually closed, and the precursor remaining in the furnace tube is removed. The pure oxygen environment is maintained at 750℃ for 30min-120min. After densification is completed, the wafer is cooled and removed to complete the preparation of the gate dielectric layer.

[0012] Furthermore, the thickness of the deposited SiO2 gate dielectric layer is 35nm-60nm.

[0013] Furthermore, in step S8, the post-deposition annealing temperature is 1200℃-1400℃, the annealing time is 30min-90min, and the annealing gas can be NO, N2, N2O or NH3.

[0014] Furthermore, in step S10, metallic nickel is sputtered as an ohmic contact material by sputtering or evaporation. The thickness of the metallic nickel is 100nm-300nm. After annealing at 650℃-950℃ in an N2 atmosphere for 60s-240s to form an ohmic contact, the excess unalloyed metallic nickel is removed by cleaning with dilute sulfuric acid.

[0015] According to another embodiment of the present invention, a silicon carbide MOSFET device is provided, characterized in that it is prepared by the above-mentioned process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFET, including a silicon carbide substrate layer, an epitaxial layer, a base region, a source contact region, a drain contact region, a body region, a gate dielectric layer, a gate, and an ohmic contact region.

[0016] According to another embodiment of the present invention, a process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs is proposed, comprising the following steps: preparing an N-type silicon carbide substrate material; fabricating an N-type epitaxial layer on the prepared N-type silicon carbide substrate material; forming a P-type doped base region on the prepared N-type silicon carbide epitaxial layer by ion implantation; forming an N-type source contact region and a drain contact region with high doping concentration in the prepared P-type base region by ion implantation; forming a P-type body region with high doping concentration in the prepared P-type base region by ion implantation; and fabricating a gate dielectric layer using a low-pressure chemical vapor deposition process, wherein in this process step, gate dielectric deposition is performed first, followed by heating to densify the gate dielectric, and then cooling to deposit the gate dielectric layer. The process involves depositing a gate dielectric, followed by heating to densify the gate dielectric. During the heating and cooling processes, as well as the densification process, the stress of the deposited gate dielectric is fully released, and precursor residues are decomposed. Polycrystalline silicon is deposited on the prepared gate dielectric layer using low-pressure chemical vapor deposition (LPCVD), and phosphorus doping is performed on the polycrystalline silicon using LCVD. An insulating dielectric layer is formed by LCVD or plasma-enhanced chemical vapor deposition to insulate the gate from the source and drain. A nickel metal layer with a thickness of 100nm-300nm is formed on the semiconductor surface using magnetron sputtering or evaporation, and rapid thermal annealing is used to create an ohmic contact between the metal and the semiconductor. Finally, the SiC MOSFET device is formed.

[0017] The beneficial effects of the present invention include, but are not limited to:

[0018] 1. A gate dielectric layer is deposited on a silicon carbide wafer using low-pressure chemical vapor deposition, which avoids the carbon clusters generated at the SiC / SiO2 interface by the traditional thermal oxidation method. This improves the SiC / SiO2 interface quality, reduces the interface state density of SiC / SiO2, and increases the channel mobility of SiC MOSFET.

[0019] 2. In the low-pressure chemical vapor deposition process, a deposition-densification-redeposition-redensification method is adopted. After deposition, the internal temperature of the furnace tube is changed to release the stress of the gate dielectric layer, eliminate precursor residues, and densify the gate dielectric layer. The segmented deposition and densification method can improve the density of the gate dielectric layer in layers, which solves the problems of large leakage current and low reliability of the gate dielectric layer caused by traditional deposition processes. It improves the reliability of the gate dielectric layer, increases the overall device fabrication yield, and has certain industrial application value. Attached Figure Description

[0020] Figure 1 This is a flowchart of a process method for improving the channel mobility and gate dielectric reliability of SiC MOSFETs according to an embodiment of the present invention;

[0021] Figure 2This is a schematic diagram of the process flow for a low-pressure chemical vapor deposition process according to an embodiment of the present invention;

[0022] Figure 3 A comparison of leakage current curves of a gate dielectric layer prepared by a low-pressure chemical vapor deposition process according to an embodiment of the present invention and a gate dielectric layer prepared by a conventional low-pressure chemical vapor deposition process.

[0023] Figure 4 This is a schematic diagram of the process flow for fabricating SiC MOSFETs according to an embodiment of the present invention. Detailed Implementation

[0024] Specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention. In the following description, numerous specific details are set forth to facilitate a thorough understanding of the invention. However, those skilled in the art will understand that these specific details are not essential for carrying out the invention. Furthermore, in some embodiments, well-known circuits, materials, or methods are not specifically described to avoid obscuring the invention.

[0025] Throughout this specification, references to "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes, with the same reference numerals indicating the same elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. The steps are not limited to a strict sequential relationship; for example, steps S1 to S10 can be performed in any order as needed.

[0026] The power MOSFET devices described in this invention include, but are not limited to, planar MOSFETs, trench MOSFETs, and split-gate MOSFETs; parasitic diodes include, but are not limited to, pin diodes and Schottky diodes; and materials include, but are not limited to, silicon carbide, gallium nitride, and silicon.

[0027] This invention provides a process method to improve the channel mobility and gate dielectric reliability of SiC MOSFETs. The method involves forming a gate dielectric layer on the surface of a silicon carbide wafer using low-pressure chemical vapor deposition (LPCVD). This avoids the formation of carbon clusters at the SiC / SiO2 interface, which is a problem associated with traditional thermal oxidation methods. This improves the SiC / SiO2 interface quality, reduces the SiC / SiO2 interface state density, and ultimately increases the channel mobility of the SiC MOSFET. The LCVD process employs a deposition-densification-redeposition-redensification approach, completing the deposition and densification process in the same equipment and process. This effectively releases the stress in the gate dielectric layer, improves its density, reduces leakage current, and enhances its reliability.

[0028] Specifically, such as Figure 1 As shown, the present invention provides a process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs, comprising the following steps:

[0029] Step S0: Prepare a silicon carbide substrate.

[0030] Step S1: Form an epitaxial layer on a silicon carbide substrate with a substrate doping concentration of 1×10⁻⁶. 19 cm -3 An N-type epitaxial layer with a thickness of 350 μm is formed on the substrate, and the doping concentration of the epitaxial layer is 8 × 10⁻⁶. 15 cm -3 The thickness is 12um. After the epitaxial layer growth is completed, RCA cleaning is performed to remove contaminants and the native oxide layer on the wafer surface.

[0031] Step S2: Form a base region on the epitaxial layer by ion implantation. The doping concentration of the base region can be 1e. 17 cm -3 The injection conditions can be 25keV 3.6E11cm -2 ; 60keV 5.8E11cm -2 ;115keV 9E11cm -2 ;200keV 1.5E12cm -2 .

[0032] Step S3: In the base region, source and drain contact regions are formed by ion implantation. The doping concentration of the contact regions can be 5e19cm. -3 The injection conditions can be 60keV 9E15cm⁻²; 80keV 1E16cm⁻². -2 ;100keV 9E15cm -2 ;180keV9E15cm -2 .

[0033] Step S4: In the base region, a bulk region is formed by ion implantation, with a bulk doping concentration of 2e19cm. -3 The injection conditions were 30keV and 5E14cm. -2 ; 90keV 1E15cm -2 ;200keV 4E15cm -2 .

[0034] Step S5: Perform activation annealing on all injections. The activation annealing temperature can be 1600℃-1850℃, and the annealing time can be 20min-90min.

[0035] Step S6: Further sacrificial oxidation is performed on the silicon carbide wafer, and the oxide layer is removed using BOE.

[0036] Step S7: The wafer is further placed in the furnace tube of a low-pressure chemical vapor deposition (LPCVD) system. The deposition temperature for the gate dielectric layer can be 640℃-690℃, and the deposition time can be 8-12 minutes. After the first stage of deposition, the process temperature is increased to 750℃. During the heating process, the oxygen content is gradually increased while the precursor valve is gradually closed, and any remaining precursor in the furnace tube is removed. A pure oxygen environment is maintained at 750℃ for 30-120 minutes. Then, the process temperature is reduced to the deposition temperature between 640℃ and 690℃, or to either 640℃ or 690℃, restoring the gas atmosphere to that used during SiO2 deposition. This involves increasing the precursor flow rate and decreasing the oxygen flow rate, with a deposition time of 8-12 minutes. The densification process is then repeated, with the process temperature increased to 750℃. During the heating process, the oxygen content is gradually increased while the precursor valve is gradually closed, and any remaining precursor in the furnace tube is removed. A pure oxygen environment is maintained at 750℃ for 30-120 minutes. After densification, the wafer is cooled and removed to complete the fabrication of the gate dielectric layer. The thickness of the gate dielectric layer can be 40nm-60nm.

[0037] Step S8: After depositing the gate dielectric layer, perform post-annealing at a temperature of 1200℃. The gas atmosphere is a mixture of NO and N2 in a ratio of 1:4. The annealing time can be 45 minutes.

[0038] Step S9: Polycrystalline silicon is deposited by low-pressure chemical vapor deposition and annealed with POCL3 to dope P element into the polycrystalline silicon to form a gate electrode.

[0039] Step S10: Low-pressure chemical vapor deposition is used to deposit insulating dielectric layers for the gate, source, and drain.

[0040] Step S11: Sputter metallic nickel using magnetron sputtering and anneal it in a rapid annealing apparatus to form an ohmic contact between the source and drain. The annealing atmosphere is N2, the temperature is 900℃, and the time is 2 minutes.

[0041] Figure 2 The process flow diagram of the low-pressure chemical vapor deposition process proposed in this invention mainly includes: depositing to form a gate dielectric layer S70, heating and densifying the gate dielectric layer after deposition S71, cooling and re-depositing the gate dielectric layer after the first step of densification S72, and heating and densifying the gate dielectric layer after the second step of deposition S73.

[0042] Figure 3 The graph shows a comparison of leakage current levels between the gate dielectric layer prepared using the low-pressure chemical vapor deposition process proposed in this invention (deposition-densification-redeposition-redensification) and the gate dielectric layer formed by conventional low-pressure chemical vapor deposition. As can be seen from the graph, the breakdown field strength of the gate dielectric layer prepared using the process proposed in this invention is increased by nearly 4 MV / cm compared to the conventional deposition process. When the gate electric field is 4 MV / cm, the leakage current level is reduced by three orders of magnitude compared to the conventional preparation process using the deposition process proposed in this invention, which greatly improves the reliability of the gate dielectric layer.

[0043] Figure 4 The process flow diagram for fabricating the SiC MOSFET is shown below. Figure 4 (a) The prepared N-type silicon carbide substrate material; Figure 4 (b) shows the preparation of an N-type epitaxial layer on a prepared N-type silicon carbide substrate material; Figure 4 (c) shows the formation of a P-type doped base region on the prepared N-type silicon carbide epitaxial layer by ion implantation; Figure 4 (d) shows that an N-type source and drain contact region with a high doping concentration is formed in the prepared P-type base region by ion implantation. Figure 4 (e) shows the formation of a P-type body region with a high doping concentration in the prepared P-type base region by ion implantation; Figure 4 (f) is a schematic diagram of the process for preparing the gate dielectric layer by the low-pressure chemical vapor deposition process proposed in this invention. In this process step, the gate dielectric is deposited first, then the gate dielectric is heated to densify, then the gate dielectric is deposited again after cooling, and then the gate dielectric is densified again after heating. During the heating and cooling process and the densification process, the stress of the deposited gate dielectric is fully released and the precursor residues are decomposed. Figure 4 (g) shows that polycrystalline silicon is deposited on the prepared gate dielectric layer by low-pressure chemical vapor deposition and phosphorus doping is performed on the polycrystalline silicon by low-pressure chemical vapor deposition. Figure 4 (h) shows how an insulating dielectric layer is formed by low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition to insulate and isolate the gate, source, and drain. Figure 4 (i) shows the formation of a SiC MOSFET device by forming a nickel metal with a thickness of 100nm-300nm on the semiconductor surface through magnetron sputtering or evaporation, followed by rapid thermal annealing to form an ohmic contact between the metal and the semiconductor.

[0044] In summary, this invention employs low-pressure chemical vapor deposition (LPCVD) to fabricate the gate dielectric layer of SiC MOSFETs and uses tetraethyl orthosilicate as a precursor for SiO2 deposition. This avoids the formation of carbon clusters at the SiC / SiO2 interface, which is a problem associated with traditional thermal oxidation methods. This improves the SiC / SiO2 interface quality, reduces the SiC / SiO2 interface state density, and increases the channel mobility of the SiC MOSFET. The LCVD process uses a deposition-densification-redeposition-redensification approach, completing the deposition and densification process in the same equipment and process. This effectively releases the stress in the gate dielectric layer, improves its density, reduces leakage current, and enhances its reliability.

[0045] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs, characterized in that, include: Step S0: Prepare a silicon carbide substrate; Step S1: An epitaxial layer is formed on a silicon carbide substrate with a first type of doping, wherein the doping type of the epitaxial layer is either the first doping type or the second doping type. Step S2: On a silicon carbide epitaxial layer with a first doping type, a base region with a second doping type is formed by ion implantation, or on a silicon carbide epitaxial layer with a second doping type, a base region with a first doping type is formed by ion implantation, or the epitaxial layer is directly used as the base region. Step S3: In the base region, the source contact region and drain contact region of the MOSFET are formed by ion implantation; when the base region has a first doping type, the source contact region and drain contact region formed by ion implantation have a second doping type; when the base region has a second doping type, the source contact region and drain contact region formed by ion implantation have a first doping type. Step S4: In the base region, a body region is formed by ion implantation. The body region has the same doping type as the base region, and the doping concentration of the body region is 1×10⁻⁶. 19 ~1×10 21 cm -3 between; Step S5: The channel region is located between the source contact region and the drain contact region. While the source contact region and the drain contact region are formed by ion implantation, the channel region is naturally formed between the two contact regions. Step S6: The surface of the silicon carbide wafer is treated by sacrificial oxidation to reduce the formation of natural oxides and reduce the surface roughness of the silicon carbide wafer. Step S7: Using tetraethyl orthosilicate as a deposition precursor, SiO2 is formed on the surface of a silicon carbide wafer as a gate dielectric layer by low-pressure chemical vapor deposition. Step S8: Anneal the gate dielectric layer in a NO, N2, N2O, or NH3 atmosphere after deposition; Step S9: Deposit polysilicon on the gate dielectric layer using low-pressure chemical vapor deposition, and then anneal the polysilicon after deposition using POCL3 to form the gate electrode; Step S10: Low-pressure chemical vapor deposition is used to deposit insulating dielectric layers for the gate, source, and drain. Step S11: Deposit or sputter metal in the source contact region, drain contact region, and body region, and form ohmic contacts by annealing.

2. The process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs as described in claim 1, characterized in that, In step S3, ion implantation of the source and drain contact regions of the MOSFET is performed at room temperature or 500°C, with an implantation angle of 7°, forming a junction depth of 0.2um-0.5um.

3. The process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs as described in claim 1, characterized in that, In step S4, ion implantation of the MOSFET body region is performed at room temperature or 500°C, with an implantation angle of 7°, forming a junction depth of 0.2µm-0.5µm and a doping concentration of 1×10⁻⁶. 19 ~1×10 21 cm -3 .

4. The process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs as described in claim 1, characterized in that, In step S7, the process flow of the low-pressure chemical vapor deposition process includes deposition to form a gate dielectric layer, post-deposition heating to densify the gate dielectric layer, first-step densification followed by cooling and re-deposition to prepare the gate dielectric layer, and second-step deposition followed by heating to densify the gate dielectric layer.

5. The process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs as described in claim 1, characterized in that, In step S7, the deposition process temperature for forming the gate dielectric layer using low-pressure chemical vapor deposition is 640℃-690℃, and the deposition time is 8min-12min. After the first stage of deposition, the process temperature is increased to 750℃. During the heating process, the oxygen content is gradually increased while the precursor valve is gradually closed, and the precursor remaining in the furnace tube is removed. The pure oxygen environment is maintained at 750℃ for 30min-120min. Then, the process temperature is reduced to the deposition process temperature of 640℃-690℃ to restore the gas atmosphere to that used when depositing SiO2, i.e., the precursor flow rate is increased and the oxygen flow rate is reduced. The deposition time is 8min-12min. Afterward, the densification process is repeated, and the process temperature is increased to 750℃. During the heating process, the oxygen content is gradually increased while the precursor valve is gradually closed, and the precursor remaining in the furnace tube is removed. The pure oxygen environment is maintained at 750℃ for 30min-120min. After densification is completed, the wafer is cooled and removed to complete the preparation of the gate dielectric layer.

6. The process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs as described in claim 5, characterized in that, The thickness of the deposited SiO2 gate dielectric layer is 35nm-60nm.

7. The process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFET as described in claim 1, characterized in that, In step S8, the post-deposition annealing temperature is 1200℃-1400℃, the annealing time is 30min-90min, and the annealing gas is NO, N2, N2O or NH3.

8. The process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFET as described in claim 1, characterized in that, In step S10, metallic nickel is sputtered as an ohmic contact material by sputtering or evaporation. The thickness of the metallic nickel is 100nm-300nm. After annealing at 650℃-950℃ in an N2 atmosphere for 60s-240s to form an ohmic contact, the excess unalloyed metallic nickel is removed by cleaning with dilute sulfuric acid.

9. A silicon carbide MOSFET device, characterized in that, The process described in any one of claims 1 to 7 for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs includes a silicon carbide substrate, an epitaxial layer, a base region, a source contact region, a drain contact region, a body region, a gate dielectric layer, a gate, and an ohmic contact region.

10. A process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFETs, characterized in that, Includes the following steps: Prepare an N-type silicon carbide substrate; fabricate an N-type epitaxial layer on the prepared N-type silicon carbide substrate; form a P-type doped base region on the fabricated N-type silicon carbide epitaxial layer by ion implantation; form highly doped N-type source and drain contact regions in the fabricated P-type base region by ion implantation; form a highly doped P-type body region in the fabricated P-type base region by ion implantation; fabricate a gate dielectric layer using a low-pressure chemical vapor deposition (LPCVD) process, in which gate dielectric deposition is performed first, followed by heating to densify the gate dielectric, cooling to perform gate dielectric deposition again, and then heating to perform gate dielectric deposition once more. During the densification process, the stress of the deposited gate dielectric is fully released during the heating and cooling process, and the precursor residues are decomposed. Polycrystalline silicon is deposited on the prepared gate dielectric layer via low-pressure chemical vapor deposition (LPCVD), and phosphorus doping is performed on the polycrystalline silicon using LCVD. An insulating dielectric layer is formed by LCVD or plasma-enhanced chemical vapor deposition to insulate the gate from the source and drain. A nickel metal layer with a thickness of 100nm-300nm is formed on the semiconductor surface by magnetron sputtering or evaporation, and rapid thermal annealing is used to form an ohmic contact between the metal and the semiconductor. Finally, a... The SiC MOSFET device is constructed.

Images