Lateral shield grid optimized vertical power field effect transistor with super junction structure

Abstract

The invention discloses a side shield grid optimized vertical power field effect transistor with a super junction structure, which comprises an N + type substrate as a drain electrode, an N type epitaxial layer grown on the N + type substrate, and a drift region generated on the N type epitaxial layer. The top of the drift region is provided with a P-type channel region, an N + type doped source region and a P + region. And the grid is arranged between the P-type channel region and the N + type source region and is separated by a grid oxide layer. The super junction structure is embedded in the drift region below the gate. Shield gates are symmetrically arranged on two sides of the device and wrapped in shield gate oxide layers, and high-K dielectric cylinders are filled below the shield gates. Compared with a common shield grid vertical power device, the shield grid is separated into the shield grids on the two sides, the drift region is transversely assisted to be depleted, vertical depletion of the drift region is weakened, and therefore on resistance is optimized. The super junction structure is embedded in the drift region, the electric field distribution of the drift region is optimized, and the fixed relation between the on-resistance and the breakdown voltage is changed, so that the on-resistance and the breakdown voltage are better balanced.

Description

Technical Field

[0001] The invention belongs to the field of field effect transistors in semiconductor devices, and in particular relates to a side shielded gate optimized vertical power field effect transistor with a super junction structure. Background Art

[0002] As the performance of traditional planar MOSFETs is limited in high current and high voltage scenarios, many new device structures have been proposed to meet the needs of the times. Among them, the vertical double diffused power field effect transistor (VDMOS) can achieve higher current density and voltage resistance in a small chip area due to its unique vertical structure, thus solving the bottleneck of the planar structure. VDMOS also takes advantage of the low drive power and simple gate control advantages of MOSFET, and therefore quickly became a core device for switching and control applications in high-power electronic devices and power converters.

[0003] At the same time, the shielded-gate trench power field effect transistor (SGT-MOSFET) relies on its unique shielded gate structure to introduce a horizontal depletion layer on the basis of the vertical depletion layer, so that the electric field distribution changes to an approximate trapezoidal shape, and the vertical distribution of the electric field is more uniform. This allows a higher breakdown voltage to be obtained while ensuring a smaller on-resistance of the device with the same doping concentration, thereby improving the performance of the device. However, the mutual restriction relationship between its breakdown voltage and on-resistance still exists, resulting in its static quality factor FOM being still small and its application occasions being relatively limited. At present, it is necessary to break the restriction relationship between its breakdown voltage and on-resistance and improve its static quality factor FOM. Summary of the invention

[0004] The purpose of the present invention is to solve the problem of small static quality factor FOM of existing shielded gate trench power field effect transistors, and propose a side shielded gate optimized vertical power field effect transistor with a super junction structure. By moving the shielded gate to both sides of the device to form a side shielded gate structure, the horizontal depletion of the device is strengthened, the vertical depletion is weakened, and the on-resistance is reduced. At the same time, a super junction structure is embedded in the device to achieve charge balance, so that the breakdown voltage can be improved without increasing the on-resistance.

[0005] To achieve the above object, the present invention adopts the following technical solutions: A side shielded gate optimized vertical power field effect transistor of a super junction structure is characterized in that it comprises: A substrate as a drain terminal, an epitaxial layer on the substrate; a drift region disposed above the epitaxial layer; A gate disposed at the center of the top of the drift region and a gate oxide layer wrapped around the gate; A shielding gate oxide layer disposed on both sides of the top of the drift region; A shielding grid high-K dielectric column and a shielding grid are arranged closely to the outside of the shielding grid oxide layer and symmetrically up and down; A superjunction structure disposed below the gate oxide layer and embedded in the drift region; A P-type channel region symmetrically disposed between the shielding gate oxide layer and the gate oxide layer; An N+ type doped source region and a P+ region are arranged above the P-type channel region, between the gate oxide layer and the shielding gate oxide layer and are adjacently placed.

[0006] Further, the substrate, epitaxial layer and drift region are bulk silicon; The gate oxide layer and the shielding gate oxide layer are silicon dioxide; The gate and the shielding gate are made of polysilicon; The shielding grid high-K dielectric column is hafnium dioxide; The super junction structure is single crystal silicon that is backfilled after etching; The P-type channel region, the N+-type doped source region and the P+ region are ion-implanted single crystal silicon.

[0007] Furthermore, the length of the shielding gate structure is equal to the length of the shielding gate high-K structure; the width of the super junction structure is smaller than the width of the gate; the widths of the N+ type doped source region and the P+ region are equal; and the length of the P type channel region does not exceed the length of the gate oxide layer.

[0008] The side shielded gate optimized vertical power field effect transistor of the super junction structure proposed in the present invention has the following advantages compared with the general shielded gate vertical power field effect transistor: Change the constraint relationship between on-resistance and breakdown voltage, and increase the breakdown voltage while maintaining on-resistance; The vertical electric field distribution is more uniform, which makes the device have a larger breakdown voltage; It has a wide range of applications and is suitable for fields requiring high current such as high power, radio frequency and microwave. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a structural schematic diagram of the present invention; Figure 2 for Figure 1 Cross-section at AA; Figure 3 A schematic diagram of electric field distribution along the cross section at AA of a conventional shielded gate vertical power field effect transistor; Figure 4 Schematic diagram of electric field distribution along the cross section at AA of the present invention; Figure 5A comparison diagram of the electric field distribution of the existing shielded gate vertical power field effect transistor and the present invention taken along BB; Figure 6 A schematic diagram showing the relationship between breakdown voltage and on-resistance of the present invention; Figure 7 A schematic diagram comparing the breakdown voltage and on-resistance of the shielded gate vertical power field effect transistor of the present invention and the prior art; Figure 8 A schematic diagram showing a comparison of static quality factors of the present invention and the prior art shielded gate vertical power field effect transistor; Fig. 9 The figure is a transfer characteristic curve diagram of the present invention and the prior art shielded gate vertical power field effect transistor; Fig.10 It is an output characteristic curve diagram of the present invention and the prior art shielded gate vertical power field effect transistor; Fig.11 It is a preparation flow chart of the present invention. DETAILED DESCRIPTION

[0010] The present invention is described in detail below with reference to the accompanying drawings and an embodiment taking nanosheets as an example.

[0011] See also Figure 1-2 The side shielded gate optimized vertical power field effect transistor of the super junction structure is characterized in that the length of the shielded gate structure is equal to the length of the shielded gate high-K structure, the width of the super junction structure is smaller than the width of the gate, the widths of the N+ type doped source region and the P+ region are equal, and the length of the P type channel region does not exceed the length of the gate oxide layer.

[0012] The transistor of the present invention comprises: a substrate 1 at a drain end, an epitaxial layer 2 on the substrate; a drift region 3 arranged above the epitaxial layer 2; a gate oxide layer 9 arranged at the center of the top of the drift region 3; a gate oxide layer 9 arranged on the gate 8; shielding gate high-K dielectric pillars 5 symmetrically arranged on both sides of the device; a shielding gate 6 arranged above the shielding gate high-K dielectric pillar 5 and symmetrically arranged with the shielding gate high-K dielectric pillar 5; a shielding gate oxide layer 7 arranged between the shielding gate 6 and the shielding gate high-K dielectric pillar 5 and the drift region 3; a super junction structure 4 arranged below the gate oxide layer 9 and embedded in the drift region 3; a P-type channel region 12 symmetrically arranged between the shielding gate oxide layer 7 and the gate oxide layer 9; an N+ type doped source region 10 arranged above the P-type channel region 12, adjacently placed and close to the gate oxide layer 9, and a P+ region 11 close to the shielding gate oxide layer 7.

[0013] The substrate 1, the epitaxial layer 2 and the drift region 3 are bulk silicon; The gate oxide layer 9 and the shielding gate oxide layer 7 are made of silicon dioxide; The gate 8 and the shielding gate 6 are made of polysilicon; The shielding gate high-K dielectric column 5 is made of hafnium dioxide; The super junction structure 4 is single crystal silicon that is backfilled after etching; The P-type channel region 12 , the N+-doped source region 10 and the P+ region 11 are ion-implanted single crystal silicon.

[0014] The current of the shielded gate vertical power field effect transistor flows in the vertical direction, but due to the existence of the drift region, although the breakdown voltage of the device is increased, the on-resistance of the device will be reduced. The most important issue for power field effect transistors is to balance the relationship between breakdown voltage and on-resistance and improve the static quality factor FOM of the device. The present invention adopts a combination of a side shielded gate structure and a super junction structure, adds a shielded gate high-K dielectric column, and changes the electric field distribution of the entire device. By moving the shielded gate to both sides of the device to form a side shielded gate structure, the horizontal depletion of the device is strengthened, the vertical depletion is weakened, and the on-resistance is reduced. At the same time, a super junction structure is embedded in the device to achieve charge balance, which allows the breakdown voltage to be increased without increasing the on-resistance.

[0015] Figure 3-4 The electric field distribution of the present invention and the existing shielded gate vertical power field effect transistor during breakdown is shown. The uniformity of the electric field distribution determines the voltage resistance of the power field effect transistor, so the electric field distribution in the vertical direction is an important performance indicator for judging the power field effect transistor. It can be seen that in the vertical direction, there is a strong electric field gathering at the bottom of the shielding gate of the existing shielded gate vertical power field effect transistor. However, there is basically no electric field gathering in the cell of the present invention. It can be seen that the electric field lines are evenly distributed in the shielding gates on both sides of the vertical power field effect transistor, compared with the existing shielded gate vertical power field effect transistor, there is no large amount of electric field gathering. This shows that the present invention has the most uniform electric field distribution during breakdown, which is also the reason why it obtains the maximum breakdown voltage. At the same time, due to its uniform electric field distribution, the risk of field oxygen being broken down by a strong electric field is greatly reduced, which improves the reliability of the vertical power field effect transistor in a breakdown environment.

[0016] Figure 5 The longitudinal electric field distribution along BB of the present invention and the existing shielded gate vertical power field effect transistor is given. It can be seen that the longitudinal electric field of the existing shielded gate vertical power field effect transistor is triangular, and there is a large electric field peak at the bottom of the vertical power field effect transistor. The present invention adjusts the distribution of the electric field peak by introducing a side shielding gate and a super junction structure, so that it has two electric field peaks, and the final maximum electric field peak is located at the center of the vertical power field effect transistor. Such a vertical electric field distribution makes the entire electric field curve present a rectangular shape, which also confirms the characteristic that the present invention has a more uniform electric field distribution.

[0017] Figure 6 The graph is a relationship between the breakdown voltage and the on-resistance measured at different drift region doping concentrations of the present invention. For power field effect transistors, if you want to increase their breakdown voltage, you must lightly dope them. But the on-resistance increases after light doping. The forward on-resistance and reverse breakdown voltage of a device are always in a mutually restrictive relationship, so there is an urgent need to propose a new structure to break the restrictive relationship. The on-resistance of the existing shielded gate vertical power field effect transistor is proportional to the 2.5th power of its breakdown voltage, and through calculation, it can be obtained that the on-resistance of the present invention is proportional to the square of its breakdown voltage. Through this feature, a better balance between the breakdown voltage and the on-resistance can be achieved by adjusting the drift region doping concentration of the power field effect transistor.

[0018] Figure 7 The present invention is a schematic diagram comparing the breakdown voltage and on-resistance of the shielded gate vertical power field effect transistor with the existing shielded gate vertical power field effect transistor. BV represents the breakdown voltage of the vertical power field effect transistor when the current is 1.5μA, and Rds(on) represents the on-resistance of the vertical power field effect transistor when the current is 100A. The breakdown voltage BV of the present invention is 132.954V, which is 56.90% higher than the breakdown voltage BV of the existing shielded gate vertical power field effect transistor of 86.824V. The on-resistance Rds(on) of the present invention is 5.829mΩ, which is 21.35% lower than the on-resistance Rds(on) of the existing shielded gate vertical power field effect transistor of 7.411mΩ.

[0019] Figure 8 The figure is a schematic diagram comparing the static quality factor FOM of the present invention and the existing shielded gate vertical power field effect transistor. The static quality factor FOM represents the DC performance of the vertical power field effect transistor, and characterizes the trade-off relationship between the on-resistance Rds(on) and the breakdown voltage BV. The larger the static quality factor FOM, the smaller the on-resistance Rds(on) will be under the same breakdown voltage BV, and the better the conduction loss, which means that the DC characteristics will also be better. The static quality factor FOM of the present invention achieves 577.6mW / cm2 by optimizing both the on-resistance and the breakdown voltage, which is 205% higher than the static quality factor FOM of 189.3mW / cm2 of the existing shielded gate vertical power field effect transistor.

[0020] Figure 9-10The transfer characteristic curves and output characteristic curves of the present invention and the existing shielded gate vertical power field effect transistor are provided. It can be seen that compared with the existing shielded gate vertical power field effect transistor, the present invention has improvements in current in both output characteristics and transfer characteristics. The on-state current of the present invention is 469.30A, and the on-state current of the existing shielded gate vertical power field effect transistor is 341.05A.

[0021] See also Fig.11 , the production process of the present invention is as follows: (1) A silicon substrate 1 and an epitaxial layer 2 serving as a drain are obtained by ion implantation and annealing; (2) A drift region 3 is obtained by thermal growth and ion implantation followed by annealing; (3) Reactive ion etching technology is used to anisotropically etch a groove of the super junction structure 4 on the drift region, and a thermal annealing is performed; (4) using chemical vapor deposition technology to deposit a super junction structure 4 inside the trench that is different from the doping in the offset region; (5) Reactive ion etching technology is used to anisotropically etch trenches of the shield gate oxide layer 7 on the left and right sides of the drift region, and a thermal annealing is performed; (6) using chemical vapor deposition technology to deposit a shielding gate oxide layer 7 of silicon dioxide; (7) using chemical vapor deposition technology to deposit a shielding gate high-K dielectric column 5 of hafnium dioxide on the shielding gate oxide layer 7; (8) Using reactive ion etching technology, anisotropically etching the shielding gate high-K dielectric pillars 5 on both sides; (9) Using chemical vapor deposition technology, depositing polysilicon shielding gate 6 in the shielding gate trenches on both sides, and performing ion implantation; (10) Reactive ion etching technology is used to anisotropically etch a groove of the gate oxide layer 9 in the center of the drift region, and a thermal annealing is performed; (11) using chemical vapor deposition technology to deposit a gate oxide layer 9 of silicon dioxide; (12) Using chemical vapor deposition technology, a polysilicon gate 8 is deposited on the gate oxide layer 9, and ion implantation is performed; (13) Anisotropically etching the gate level 8 using reactive ion etching technology; (14) using chemical vapor deposition technology to deposit a gate oxide layer 9 of silicon dioxide on the gate 8; (15) Using ion implantation technology, a P-type channel region 12, an N+-type doped source region 10, and a P+ region 11 are formed.

Claims

1. A side shielded gate optimized vertical power field effect transistor of a super junction structure, characterized in that: It includes: A substrate (1) serving as a drain terminal, and an epitaxial layer (2) on the substrate; A drift region (3) disposed above the epitaxial layer (2); A gate (8) disposed at the center of the top of the drift region (3) and a gate oxide layer (9) wrapped around the gate (8); A shielding gate oxide layer (7) provided on both sides of the top of the drift region (3); A shielding gate high-K dielectric column (5) and a shielding gate (6) are arranged in close contact with the outside of the shielding gate oxide layer (7) and symmetrically arranged up and down; A super junction structure (4) disposed below the gate oxide layer (9) and embedded in the drift region (3); A P-type channel region (12) symmetrically arranged between the shielding gate oxide layer (7) and the gate oxide layer (9); An N+ type doped source region (10) and a P+ region (11) are arranged above a P-type channel region (12), between a gate oxide layer (9) and a shielding gate oxide layer (7), and are adjacently placed.

2. The side shielded gate optimized vertical power field effect transistor of super junction structure according to claim 1, characterized in that: The substrate (1), the epitaxial layer (2) and the drift region (3) are bulk silicon; The gate oxide layer (9) and the shielding gate oxide layer (7) are silicon dioxide; The gate (8) and the shielding gate (6) are made of polysilicon; The shielding grid high-K dielectric column (5) is hafnium dioxide; The super junction structure (4) is single crystal silicon that is backfilled after etching; The P-type channel region (12), the N+-type doped source region (10) and the P+ region (11) are ion-implanted single crystal silicon.

3. The side-shielded gate optimized vertical power field effect transistor of super junction structure according to claim 1, characterized in that: The length of the shielding gate structure (6) is equal to the length of the shielding gate high-K structure (5); the width of the super junction structure (4) is smaller than the width of the gate (8); the widths of the N+ type doped source region (10) and the P+ region (11) are equal; and the length of the P-type channel region (12) does not exceed the length of the gate oxide layer (9).

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