A semiconductor device and a method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device includes the following steps: providing a substrate, forming a gate structure on the substrate, and forming a drain doping region and a source doping region in the substrate on both sides of the gate structure; forming an epitaxial layer on the substrate of the source doping region and the drain doping region, and metallizing the epitaxial layer to form a conductive contact layer, the surface of the conductive contact layer being flush with the surface of the gate structure; forming an interlayer dielectric layer on the conductive contact layer and the gate structure, and forming a conductive contact hole in the interlayer dielectric layer, the conductive contact hole penetrating through the interlayer dielectric layer and respectively contacting the conductive contact layer and the gate structure, so that the gate structure, the source and the drain are on the same horizontal plane, which can reduce the process difficulty of the contact hole lithography and etching processes and solve the problems that occur in the contact hole etching.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the logic circuit manufacturing process, after forming a gate structure on a substrate, a metal silicide layer is formed on the surfaces of the source region S, drain region D, and gate G, and an SPT (Stress Proximity Technology) process is performed to laterally reduce the width of the sidewalls on both sides of the gate G. Finally, contact holes CT are formed, as Figure 1 shown. However, with the continuous reduction of the manufacturing requirements, the CD (Critical Dimension) size of the contact holes CT becomes smaller and smaller, which makes the process of etching the contact holes CT more and more difficult, and contact hole CT etching problems often occur in the active area (AA), such as the problem of open contact holes CT (the contact holes CT cannot be connected to the source region S, drain region D, or gate G in the MOS transistor), thereby affecting the yield, as Figure 2 shown. Summary of the Invention

[0003] The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the process difficulty of the contact hole lithography and etching processes and solve the problems occurring in the contact hole etching.

[0004] To solve the above problems, the present invention provides a method for manufacturing a semiconductor device, including the following steps:

[0005] Provide a substrate, on which a gate structure is formed, and a drain doping region and a source doping region are respectively formed in the substrate on both sides of the gate structure;

[0006] Form an epitaxial layer on the substrate of all the source doping regions and drain doping regions, and metalize the epitaxial layer to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure;

[0007] Form an interlayer dielectric layer on the conductive contact layer and the gate structure, and form a plurality of conductive contact holes in the interlayer dielectric layer. All the conductive contact holes penetrate the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure.

[0008] Optionally, the gate structure includes a gate oxide layer, a polysilicon gate, and sidewalls. The gate oxide layer is located on the surface of the substrate, the polysilicon gate is stacked on the gate oxide layer, and the sidewalls are located on both sides of the gate oxide layer and the polysilicon gate and cover the sidewalls of the gate oxide layer and the polysilicon gate.

[0009] Further, the specific method for forming the conductive contact layer is:

[0010] Measure the height of the gate structure through an optical critical dimension measurement process, where the height of the gate structure is the total height of the gate oxide layer and the polysilicon gate;

[0011] Form an epitaxial layer on the substrate of the source doping region and the substrate of the drain doping region through an epitaxial process. At the same time, form a polysilicon epitaxial structure on the surface of the polysilicon gate. Among them, the height of the epitaxial layer is the same as the height of the gate structure;

[0012] Convert the epitaxial layer and the polysilicon epitaxial structure into a metal silicide layer;

[0013] Planarize the substrate so that the metal silicide layer on the polysilicon gate, the metal silicide layer above the source doping region, and the metal silicide layer above the drain doping region are on the same horizontal plane.

[0014] Furthermore, when forming the metal silicide layer, the thickness of the metal silicide layer on the substrates of the source doping region and the drain doping region is less than the thickness of the metal silicide layer on the polysilicon gate.

[0015] Furthermore, the gate structure further includes a hard mask layer that covers the polysilicon gate.

[0016] Furthermore, the specific method for forming the conductive contact layer is:

[0017] Measure the height of the gate structure through an optical critical dimension measurement process, where the height of the gate structure is the total height of the gate oxide layer and the polysilicon gate;

[0018] Form an epitaxial layer on the substrate of the source doping region and the substrate of the drain doping region through an epitaxial process. Among them, the height of the epitaxial layer is the same as the height of the gate structure;

[0019] Planarize the substrate to expose the polysilicon gate and make the polysilicon gate and the epitaxial layer on the same horizontal plane;

[0020] Perform a metal element implantation process on the epitaxial layer close to the substrate side;

[0021] Convert a part of the thickness of the epitaxial layer far from the substrate side and a part of the thickness of the polysilicon gate into a metal silicide layer, where the metal element implantation position is below the metal silicide layer.

[0022] Furthermore, the metal element is at least one of magnesium, calcium, and barium, and the doping concentration of the metal element is greater than or equal to 1×10 21 atoms / cm3 。

[0023] Further, the specific method for forming the conductive contact hole is as follows:

[0024] An etch stop layer, an interlayer dielectric layer, a pattern transfer layer, and a patterned photoresist layer are sequentially formed on the metal silicide layer;

[0025] Using the patterned photoresist layer as a mask, the pattern transfer layer, the interlayer dielectric layer, and the etch stop layer are sequentially etched to expose the metal silicide layer, and at the same time, a transition trench is formed;

[0026] The photoresist layer and the pattern transfer layer are removed to expose the interlayer dielectric layer to form a second trench;

[0027] A conductive contact hole is formed in the second trench.

[0028] On the other hand, the present invention also provides a semiconductor device, including a substrate, a gate structure is formed on the substrate, a drain doping region and a source doping region are respectively formed in the substrate on both sides of the gate structure, a conductive contact layer is formed on the substrate of all the source doping regions and drain doping regions, an interlayer dielectric layer is formed on the conductive contact layer and the gate structure, and a plurality of conductive contact holes are formed in the interlayer dielectric layer. All the conductive contact holes penetrate the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure. Wherein, the conductive contact layer includes a metal silicide layer.

[0029] Optionally, the conductive contact layer further includes an epitaxial layer, the epitaxial layer is located between the metal silicide layer and the substrate, and the epitaxial layer is doped with a metal element.

[0030] Compared with the prior art, the present invention has the following unexpected technical effects:

[0031] The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device includes the following steps: providing a substrate, on which a gate structure is formed, and a drain doping region and a source doping region are respectively formed in the substrate on both sides of the gate structure; forming an epitaxial layer on the substrate of all the source doping regions and drain doping regions, and metallizing the epitaxial layer to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure; forming an interlayer dielectric layer on the conductive contact layer and the gate structure, and forming a plurality of conductive contact holes in the interlayer dielectric layer, and all the conductive contact holes penetrate the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure. By forming the epitaxial layer and metallizing the epitaxial layer, the gate structure, the source and the drain are in the same horizontal plane, which reduces the process difficulty of the lithography and etching processes for forming the conductive contact holes, reduces the process difficulty and cost of the manufacturing process of the conductive contact layer, improves the etching process window of the conductive contact holes, and also solves problems such as open circuits of the conductive contact holes in the etching process of the conductive contact holes, thereby improving the yield, reducing the alignment specification requirements for the conductive contact holes, and also omitting the removal of the sidewall part (i.e., the SPT process), which reduces the process cost. Description of the Drawings

[0032] Figure 1 It is a schematic structural diagram of a semiconductor device in the prior art.

[0033] Figure 2 It is a schematic diagram when an open contact hole appears in the prior art.

[0034] Figure 3 It is a schematic flow diagram of a method for manufacturing a semiconductor device provided by the present invention.

[0035] Figure 4 It is a schematic structural diagram of a substrate provided in Embodiment 1 of the present invention.

[0036] Figure 5 It is a schematic structural diagram after forming an epitaxial layer in Embodiment 1 of the present invention.

[0037] Figure 6 It is a schematic structural diagram after forming a metal silicide layer in Embodiment 1 of the present invention.

[0038] Figure 7 It is a schematic structural diagram after forming a filling layer in Embodiment 1 of the present invention.

[0039] Figure 8 It is a schematic structural diagram after forming a patterned photoresist layer in Embodiment 1 of the present invention.

[0040] Figure 9 It is a schematic structural diagram after forming a transition trench in Embodiment 1 of the present invention.

[0041] Figure 10 This is a schematic diagram of the structure after forming a conductive contact hole in the first embodiment of the present invention.

[0042] Figure 11 This is a schematic diagram of the structure of the substrate provided in the second embodiment of the present invention.

[0043] Figure 12 This is a schematic diagram of the structure after forming an epitaxial layer in the second embodiment of the present invention.

[0044] Figure 13 This is a schematic diagram of the structure after forming a filling layer in the second embodiment of the present invention.

[0045] Figure 14 This is a schematic diagram of the structure when metal elements are implanted into the epitaxial layer in the second embodiment of the present invention.

[0046] Figure 15 This is a schematic diagram of the structure after forming a metal silicide layer in the second embodiment of the present invention.

[0047] Figure 16 This is a schematic diagram of the structure after forming a patterned photoresist layer in the second embodiment of the present invention.

[0048] Figure 17 This is a schematic diagram of the structure after forming a transition trench in the second embodiment of the present invention.

[0049] Figure 18 This is a schematic diagram of the structure after forming a conductive contact hole in the second embodiment of the present invention.

[0050] Explanation of reference numerals:

[0051] I - First active region; II - Second active region; 100 - Substrate; 101 - First well region; 102 - Second well region; 103 - Shallow trench isolation structure; 104 - First source doping region; 105 - First drain doping region; 106 - Second source doping region; 107 - Second drain doping region; 200 - Gate structure; 201 - Gate oxide layer; 202 - Polysilicon gate; 203 - Sidewall; 204 - Hard mask layer; 301 - Epitaxial layer; 302 - Polysilicon epitaxial structure; 303 - First trench; 310 - Metal silicide layer; 320 - Filling layer; 330 - Etch stop layer; 340 - Interlayer dielectric layer; 350 - Pattern transfer layer; 360 - Photoresist layer; 371 - Second trench; 372 - Conductive contact hole; Detailed implementation manners

[0052] A semiconductor device according to the present invention and a method for manufacturing the same will be described in further detail below. The present invention will be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein and still achieve the advantageous effects of the present invention. Therefore, the following description should be understood as broad knowledge for those skilled in the art and not as a limitation of the present invention.

[0053] For clarity, not all features of actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would obscure the present invention with unnecessary details. It should be considered that in the development of any actual embodiment, numerous implementation details must be made to achieve the specific goals of the developer, such as changing from one embodiment to another according to system-related or business-related constraints. Additionally, it should be considered that such development work may be complex and time-consuming, but it is only routine work for those skilled in the art.

[0054] To make the objectives and features of the present invention more obvious and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise ratios, only for the purpose of conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0055] Embodiment 1

[0056] As Figure 3 shown, this embodiment provides a method for manufacturing a semiconductor device, including the following steps:

[0057] Step S1: Provide a substrate, on which a gate structure is formed, and source doping regions and drain doping regions are respectively formed in the substrate on both sides of the gate structure;

[0058] Step S2: Form an epitaxial layer on the substrate of all the source doping regions and drain doping regions, and metalize the epitaxial layer to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure;

[0059] Step S3: Form an interlayer dielectric layer on the conductive contact layer and the gate structure, and form a plurality of conductive contact holes in the interlayer dielectric layer. All the conductive contact holes penetrate the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure.

[0060] In the present invention, by forming an epitaxial layer and metallizing the epitaxial layer, the gate structure, source, and drain are in the same horizontal plane, reducing the process difficulty of the lithography and etching processes for forming conductive contact holes, reducing the process difficulty and cost of the conductive contact layer manufacturing process, increasing the etching process window of the conductive contact holes, and also solving problems such as open circuits in the conductive contact hole etching process, thereby improving the yield, reducing the overlay alignment specification requirements for the conductive contact holes, and also omitting the sidewall partial removal (i.e., the SPT process), reducing the process cost.

[0061] The following will be described in detail Figures 4 - 10 a method for manufacturing a semiconductor device provided in this embodiment.

[0062] As Figure 4 shown, first, step S1 is performed to provide a substrate 100, on which a gate structure 200 is formed, and source doping regions and drain doping regions are formed in the substrate 100 on both sides of the gate structure 200.

[0063] An active region is provided in the substrate 100, and a shallow trench isolation structure 103 is annularly provided outside the active region. A well region is formed in the substrate 100 of the active region, and the well region extends from one side of the substrate 100 into the substrate 100 and stops in the substrate 100. A gate structure 200 is formed on the surface of one side of the substrate 100. The gate structure 200 includes a gate oxide layer 201, a polysilicon gate 202, and sidewalls 203. The gate oxide layer 201 is located on the surface of the substrate 100, the polysilicon gate 202 is stacked on the gate oxide layer 201, and the sidewalls 203 are located on both sides of the gate oxide layer 201 and the polysilicon gate 202 and cover the sidewalls of the gate oxide layer 201 and the polysilicon gate 202. Source doping regions and drain doping regions are respectively formed in the substrate 100 on both sides of the gate structure 200. A source extension doping region is provided in the substrate 100 on the side of the source doping region close to the drain doping region, and a drain extension doping region is provided in the substrate 100 on the side of the drain doping region close to the source doping region, such that both the source extension doping region and the drain extension doping region are located below the gate structure 200. A pocket doping region is also provided in the substrate 100 below the source extension doping region and the drain extension doping region.

[0064] In this embodiment, the substrate 100 includes a first active region I and a second active region II for forming low-voltage devices. The first active region I is used to form low-voltage NMOS transistors, and the second active region II is used to form low-voltage PMOS transistors. The first active region I and the second active region II are adjacent to each other, and shallow trench isolation structures 103 are disposed around the outside of the first active region I and the outside of the second active region II. A first well region 101 is formed in the substrate 100 of the first active region I. The first well region 101 extends from one surface of the substrate 100 to the other surface and stops in the substrate 100. A second well region 102 is formed in the substrate 100 of the second active region II. The second well region 102 is disposed on the same side as the first well region 101, and the second well region 102 also extends from one surface of the substrate 100 to the other surface and stops in the substrate 100. Preferably, the depth of the second well region 102 is the same as the depth of the first well region 101. Among them, the first well region 101 is doped with P-type ions, the second well region 102 is doped with N-type ions, and the height of the shallow trench isolation structure 103 is greater than the depth of the first well region 101 and also greater than the depth of the second well region 102.

[0065] In the first active region I, a first source doping region 104 and a first drain doping region 105 are formed in the substrate 100 on both sides of the gate structure 200. Among them, both the first source doping region 104 and the first drain doping region 105 are doped with N-type ions; in the second active region II, a second source doping region 106 and a second drain doping region 107 are formed in the substrate 100 on both sides of the gate structure 200. Among them, both the second source doping region 106 and the second drain doping region 107 are doped with P-type ions.

[0066] As Figures 4 - 7 shown, then step S2 is executed. An epitaxial layer 301 is formed on the substrate 100 of all the source doping regions and drain doping regions, and the epitaxial layer 301 is metallized to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure 200.

[0067] This step specifically includes the following steps:

[0068] Please refer to Figure 4 , first, the height H of the gate structure 200 is measured through an OCD (Optical Critical Dimension) measurement process, that is, the total height of the gate oxide layer 201 and the polysilicon gate 202 is measured.

[0069] Please refer to Figure 5, an epitaxial layer 301 is formed on the substrate 100 of the source doping region and the substrate 100 of the drain doping region through an epitaxial process, wherein the material of the epitaxial layer 301 is silicon.

[0070] In this embodiment, on the surface of the substrate 100 of the first active region I and the second active region II, an epitaxial layer 301 is formed on the surface of the substrate 100 through an epitaxial process. The epitaxial layer 301 covers the first source doping region 104, the first drain doping region 105, the second source doping region 106, and the second drain doping region 107. At the same time, since the polysilicon gate 202 is exposed to the external environment, a polysilicon epitaxial structure 302 is also formed on the surface of the polysilicon gate 202. At this time, no epitaxial layer 301 is formed above the shallow trench isolation structure 103, so that a first trench 303 is formed above the shallow trench isolation structure 103. The material of the epitaxial layer 301 is the same as that of the substrate 100, and the materials of the polysilicon gate 202 and the polysilicon epitaxial structure 302 are the same.

[0071] Please refer to Figure 6 , then, the epitaxial layer 301 and the polysilicon epitaxial structure 302 are converted into a metal silicide layer 310 to realize the metallization of the epitaxial layer.

[0072] Specifically, first, a shielding layer is formed on the surface of a part of the substrate 100, and the shielding layer covers the area that does not need to be metallized (to form a metal silicide layer). The shielding layer sequentially includes a first oxide layer and a first silicon nitride layer from bottom to top, and the material of the first oxide layer is the same as that of the shallow trench isolation structure 103.

[0073] Then, the natural oxide layer formed on the surfaces of the epitaxial layer 301 and the polysilicon epitaxial structure 302 is removed through a pre-cleaning process.

[0074] Then, a nickel-platinum (NiPt) alloy film layer with a first preset thickness (such as 120 Å) and a titanium nitride film layer with a second preset thickness (such as 50 Å) are sequentially deposited, and the epitaxial layer 301 and the polysilicon epitaxial structure 302 are converted into a low-resistance nickel-platinum silicide layer (NiPtSi2) through two heat treatment processes (RTP), and then the excess nickel that has not formed the nickel-platinum silicide layer (NiPtSi2) is removed. In the two heat treatment processes, since the formation rate of nickel silicide (NiSi) in the polysilicon epitaxial structure 302 is faster than that in the epitaxial layer 301, when the entire epitaxial layer 301 is converted into the metal silicide layer 310, the polysilicon epitaxial structure 302 has been converted first and has converted a part of the thickness of the polysilicon gate 202. Therefore, the thickness of the metal silicide layer 310 above the gate structure 200 is greater than the thickness of the epitaxial layer 301.

[0075] Please refer to Figure 7 , then, an insulating material is filled in the first trench 303, and the substrate is planarized to form a filling layer 320, so that the metal silicide layers 310 on the polysilicon gate 202, the metal silicide layers 310 above the source doping region, and the metal silicide layers 310 above the drain doping region are on the same horizontal plane. Specifically, the first silicon nitride layer is first removed, and an oxide material is used in the first trench 303 to form a filling layer 320, and the oxide material also covers the epitaxial layer 301. Then, the excess oxide material is removed by a CMP (chemical mechanical polishing) process to expose the epitaxial layer 301, and at the same time, part of the metal silicide layer 310 above the gate structure 200 is removed, so that the metal silicide layers 310 on the polysilicon gate 202, the metal silicide layers 310 above the source doping region, and the metal silicide layers 310 above the drain doping region are on the same horizontal plane. At this time, the filling layer 320 and the shallow trench isolation structure 103 together serve as a new shallow trench isolation structure.

[0076] As Figures 8 - 10 shown, then step S3 is executed, an interlayer dielectric layer 340 is formed on the conductive contact layer and the gate structure 200, and a plurality of conductive contact holes 372 are formed in the interlayer dielectric layer 340, and all the conductive contact holes 372 penetrate through the interlayer dielectric layer and are in contact with the conductive contact layer and the gate structure 200 respectively.

[0077] This step specifically includes the following steps:

[0078] Please refer to Figure 8 , first, an etch stop layer 330, an interlayer dielectric layer 340, a pattern transfer layer 350, and a patterned photoresist layer 360 are sequentially formed on the metal silicide layer 310 and the filling layer 320, and the patterned photoresist layer 360 has openings above the source doping region, the drain doping region, and the polysilicon gate 202. In this embodiment, the patterned photoresist layer 360 has openings above the first source doping region 104, the first drain doping region 105, and the polysilicon gate 202 in the first active region I, and also has openings above the second source doping region 106, the second drain doping region 107, and the polysilicon gate 202 in the second active region II.

[0079] Among them, the material of the interlayer dielectric layer is an oxide layer, the material of the etch stop layer 330 is silicon nitride, and the pattern transfer layer 350 sequentially includes an α-carbon film layer, a silicon oxynitride layer, a first silicon oxide layer, and a BARC layer from bottom to top.

[0080] Please refer to Figure 9, then, using the patterned photoresist layer 360 as a mask, at the opening, the pattern transfer layer 350, the interlayer dielectric layer 340, and the etch stop layer 330 are sequentially etched through a multi-step etching process, and the metal silicide layer 310 is exposed, and a transition trench is formed.

[0081] Next, the photoresist layer 360 and the pattern transfer layer 350 are removed, and the interlayer dielectric layer 340 is exposed to form a second trench 371.

[0082] Please refer to Figure 10 , then, a conductive contact hole 372 is formed in the second trench 371. Specifically, first, a first conductive layer is formed on the inner walls (bottom wall and side walls) of the second trench 371 through a deposition process. The first conductive layer sequentially includes a titanium film layer and a titanium nitride film layer, and the first conductive layer also covers the interlayer dielectric layer 340 outside the second trench 371. Then, a metal material is filled in the second trench 371 through a CVD (chemical vapor deposition) process, and the metal material also covers the first conductive layer on the interlayer dielectric layer 340; finally, the metal material and the first conductive layer on the interlayer dielectric layer 340 are removed through a CMP process to expose the interlayer dielectric layer 340, thereby forming a conductive contact hole 372.

[0083] This embodiment also provides a semiconductor device, including a substrate 100, a gate structure 200 is formed on the substrate 100, a source doping region and a drain doping region are respectively formed in the substrate 100 on both sides of the gate structure 200, a conductive contact layer is formed on the substrate 100 of all the source doping regions and drain doping regions, an interlayer dielectric layer 340 is formed on the conductive contact layer and the gate structure 200, and a plurality of conductive contact holes 372 are formed in the interlayer dielectric layer 340. All the conductive contact holes 372 penetrate through the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure 200. Among them, the conductive contact layer only includes a metal silicide layer 310.

[0084] Embodiment Two

[0085] Compared with Embodiment One, there are differences in the steps of the manufacturing method of the semiconductor device provided in this embodiment.

[0086] Specifically, in step S1, the gate structure 200 further includes a hard mask layer 204, the hard mask layer 204 covers the polysilicon gate 202, the hard mask layer 204 sequentially includes a second silicon oxide layer and a second silicon nitride layer from bottom to top, and the partial film layer formed by the hard mask layer 204 and the sidewall 203 is the same in the deposition process, but these film layers (i.e., the second silicon oxide layer and the second silicon nitride layer) on the surface of the polysilicon gate 202 are retained when etching to form the sidewall 203, asFigure 11 as shown

[0087] As Figures 12 - 13 shown, step S2 specifically includes the following steps:

[0088] Please refer to Figure 11 , first, measure the height H of the gate structure 200 through an OCD (Optical Critical Dimension) measurement process, that is, measure the total height of the gate oxide layer 201 and the polysilicon gate 202.

[0089] At this time, the thickness of the formed epitaxial layer 301 is still the height H. However, since the polysilicon gate 202 is covered by the hard mask layer 204, therefore, as Figure 12 shown, then, in the epitaxial process, no polysilicon epitaxial structure 302 is formed on the surface of the polysilicon gate 202. That is to say, through the epitaxial process, the epitaxial layer 301 is formed only on the substrate 100 of the source doping region and the substrate 100 of the drain doping region. In this embodiment, the epitaxial layer 301 is formed on the substrates 100 of the first source doping region 104, the first drain doping region 105, the second source doping region 106, and the second drain doping region 107 through the epitaxial process.

[0090] As Figure 13 shown, then, fill the first trench 303 with an insulating material and planarize the substrate to form a filling layer 320 to expose the polysilicon gate 202 and make the polysilicon gate 202 and the epitaxial layer 301 on the same horizontal plane. Specifically, first deposit a filling material in the first trench 303. The filling material covers the epitaxial layer 301, and remove the filling material on the epitaxial layer 301 and the hard mask layer 204 through a CMP process to form a filling layer 320. At this time, the filling layer 320, the epitaxial layer 301, and the polysilicon gate 202 are on the same horizontal plane.

[0091] As Figure 14 shown, then, perform a metal element implantation process on the epitaxial layer 301 close to the substrate side. The metal element can be at least one of magnesium (Mg), calcium (Ca), and barium (Ba). Since the material of the epitaxial layer 301 is the semiconductor material silicon, and since the doping of the metal element adjusts the Schottky barrier height (SBH), thereby effectively reducing the electrical interface resistance of the source / drain electrodes. At the same time, this ion implantation process has no effect on the polysilicon gate 202, and since the material of the sidewall 203 is an insulating material, this makes the sidewall 203 still non-conductive even if a metal element is implanted into it. Therefore, this step only reduces the resistance of the epitaxial layer 301 close to the substrate side. Among them, the doping concentration of the metal element is greater than or equal to 1×10 21atoms / cm 3 In this step, the epitaxial layer 301 does not form a metal silicide layer during the metal element implantation process. Therefore, this step is different from the step of converting the epitaxial layer 301 and the polysilicon epitaxial structure 302 into a metal silicide layer 310 to achieve metallization of the epitaxial layer.

[0092] As Figure 15 shown, then, a part of the thickness of the epitaxial layer 301 on the side away from the substrate and a part of the thickness of the polysilicon gate 202 are converted into a metal silicide layer 310, wherein the metal element implantation position is below the metal silicide layer 310.

[0093] Step S3 specifically includes:

[0094] As Figure 16 shown, first, an etch stop layer 330, an interlayer dielectric layer 340, a pattern transfer layer 350, and a patterned photoresist layer 360 are formed on the surfaces of the metal silicide layer 310 and the fill layer 320. The patterned photoresist layer 360 has openings above the first source doping region 104, the first drain doping region 105, and the polysilicon gate 202 in the first active region I, and above the second source doping region 106, the second drain doping region 107, and the polysilicon gate 202 in the second active region II.

[0095] As Figure 17 shown, then, using the patterned photoresist layer 360 as a mask, at the openings, the pattern transfer layer 350, the interlayer dielectric layer 340, and the etch stop layer 330 are sequentially etched through a multi-step etching process, and the metal silicide layer 310 is exposed, and a transition trench is formed.

[0096] Next, the photoresist layer 360 and the pattern transfer layer 350 are removed, and the interlayer dielectric layer 340 is exposed to form a second trench 371.

[0097] As Figure 18 shown, a conductive contact hole 372 is formed in the second trench 371.

[0098] This embodiment provides a semiconductor device, including a substrate 100, on which a gate structure 200 is formed. Source doping regions and drain doping regions are respectively formed in the substrate 100 on both sides of the gate structure 200. A conductive contact layer is formed on the substrate 100 of all the source doping regions and drain doping regions. An interlayer dielectric layer 340 is formed on the conductive contact layer and the gate structure 200, and a plurality of conductive contact holes 372 are formed in the interlayer dielectric layer 340. All the conductive contact holes 372 penetrate the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure 200. Among them, the conductive contact layer includes an epitaxial layer 301 and a metal silicide layer 310 from bottom to top, and the epitaxial layer 301 is doped with metal elements.

[0099] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device includes the following steps: providing a substrate, on which a gate structure is formed, and respectively forming a drain doping region and a source doping region in the substrate on both sides of the gate structure; forming an epitaxial layer on the substrate of all the source doping regions and drain doping regions, and metallizing the epitaxial layer to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure; forming an interlayer dielectric layer on the conductive contact layer and the gate structure, and forming a plurality of conductive contact holes in the interlayer dielectric layer. All the conductive contact holes penetrate the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure. By forming an epitaxial layer and metallizing the epitaxial layer, the gate structure, the source and the drain are on the same horizontal plane, reducing the process difficulty of the lithography and etching processes for forming the conductive contact holes, reducing the process difficulty and cost of the manufacturing process of the conductive contact layer, increasing the etching process window of the conductive contact holes, and also solving problems such as open circuits of the conductive contact holes in the etching process of the conductive contact holes, thereby improving the yield, reducing the requirements for the overlay alignment specification of the conductive contact holes, and also omitting the removal of the sidewall part (i.e., the SPT process), reducing the process cost.

[0100] In addition, it should be noted that unless otherwise specified or indicated, the descriptions of the terms "first" and "second" in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship, etc. between each component, element, step.

[0101] It will be understood that although the present invention has been disclosed above in preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible variations and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, on which a gate structure is formed, and in which a drain doping region and a source doping region are respectively formed in the substrate on both sides of the gate structure; Forming an epitaxial layer on the substrate of all the source doping regions and the drain doping regions, and metalizing the epitaxial layer to form a conductive contact layer, wherein the surface of the conductive contact layer is flush with the surface of the gate structure, and the height of the epitaxial layer is the same as the height of the gate structure; An interlayer dielectric layer is formed on the conductive contact layer and the gate structure, and a plurality of conductive contact holes are formed in the interlayer dielectric layer, all of which penetrate the interlayer dielectric layer and contact the conductive contact layer and the gate structure respectively.

2. The method for preparing a semiconductor device according to claim 1, wherein: The gate structure includes a gate oxide layer, a polysilicon gate and a sidewall, wherein the gate oxide layer is located on the surface of the substrate, the polysilicon gate is stacked on the gate oxide layer, and the sidewall is located on both sides of the gate oxide layer and the polysilicon gate and covers the sidewalls of the gate oxide layer and the polysilicon gate.

3. The method for preparing a semiconductor device according to claim 2, wherein: The specific method of forming the conductive contact layer is: Measuring the height of the gate structure by an optical critical dimension measurement process, wherein the height of the gate structure is the total height of the gate oxide layer and the polysilicon gate; Forming an epitaxial layer on the substrate of the source doping region and the substrate of the drain doping region through an epitaxial process, and forming a polysilicon epitaxial structure on the surface of the polysilicon gate; converting the epitaxial layer and the polysilicon epitaxial structure into a metal silicide layer; The substrate is planarized so that the metal silicide layer on the polysilicon gate, the metal silicide layer above the source doping region, and the metal silicide layer above the drain doping region are on the same level.

4. The method for preparing a semiconductor device according to claim 3, wherein: When the metal silicide layer is formed, the thickness of the metal silicide layer on the substrate of the source doping region and the drain doping region is smaller than the thickness of the metal silicide layer on the polysilicon gate.

5. The method for preparing a semiconductor device according to claim 2, wherein: The gate structure further includes a hard mask layer, and the hard mask layer covers the polysilicon gate.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The specific method of forming the conductive contact layer is: Measuring the height of the gate structure by an optical critical dimension measurement process, wherein the height of the gate structure is the total height of the gate oxide layer and the polysilicon gate; Forming an epitaxial layer on the substrate of the source doping region and on the substrate of the drain doping region through an epitaxial process; Planarizing the substrate to expose the polysilicon gate and make the polysilicon gate and the epitaxial layer be on the same level; Performing a metal element implantation process on the epitaxial layer close to the substrate side; A portion of the thickness of the epitaxial layer away from the substrate side and a portion of the thickness of the polysilicon gate are converted into a metal silicide layer, wherein the metal element injection position is located below the metal silicide layer.

7. The method for preparing a semiconductor device according to claim 6, wherein: The metal element is at least one of magnesium, calcium and barium, and the doping concentration of the metal element is greater than or equal to 1×10 21 atoms / cm 3 .

8. The method for preparing a semiconductor device according to claim 3 or 6, characterized in that: The specific method of forming the conductive contact hole is: forming an etch stop layer, an interlayer dielectric layer, a pattern transfer layer and a patterned photoresist layer in sequence on the metal silicide layer; Using the patterned photoresist layer as a mask, sequentially etching the pattern transfer layer, the interlayer dielectric layer and the etching stop layer, exposing the metal silicide layer, and forming a transition trench at the same time; removing the photoresist layer and the pattern transfer layer and exposing the interlayer dielectric layer to form a second trench; A conductive contact hole is formed in the second trench.

9. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1, characterized in that: The invention comprises a substrate, a gate structure is formed on the substrate, a drain doping region and a source doping region are respectively formed in the substrate on both sides of the gate structure, a conductive contact layer is formed on the substrate of all the source doping regions and the drain doping regions, an interlayer dielectric layer is formed on the conductive contact layer and the gate structure, and a plurality of conductive contact holes are formed in the interlayer dielectric layer, all the conductive contact holes penetrate the interlayer dielectric layer and are respectively in contact with the conductive contact layer and the gate structure, wherein the conductive contact layer comprises a metal silicide layer.

10. The semiconductor device according to claim 9, wherein: The conductive contact layer further includes an epitaxial layer, the epitaxial layer is located between the metal silicide layer and the substrate, and the epitaxial layer is doped with metal elements.

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