TBC battery and preparation method thereof

Abstract

The invention discloses a TBC battery and a preparation method thereof. The method comprises the following steps: providing an N-type silicon substrate; the N-type silicon substrate comprises a front surface and a back surface; preparing a first tunneling oxide layer and a first doping layer on the back surface; forming a first region and a second region which are alternately arranged in an interdigital manner on the back surface by using a preset laser condition; removing the first tunneling oxide layer and the first doping layer in the second region, and preparing a second tunneling oxide layer and a second doping layer in the second region; performing front surface texturing on the front surface, preparing a first protection layer on the surfaces of the sides, deviating from the N-type silicon substrate, of the first doping layer and the second doping layer on the back surface, and preparing a second protection layer on the front surface subjected to front surface texturing; and performing silk-screen printing and high-temperature sintering on the first region and the second region to form a first electrode in contact with the first doping layer in the first region and form a second electrode in contact with the second doping layer in the second region, thereby obtaining the TBC battery. By using the method, the conversion efficiency of the battery is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to a TBC cell and a preparation method thereof. Background Art

[0002] The renewal and iteration of photovoltaic cell structure has led to the continuous accumulation of old production capacity, and cost reduction and efficiency improvement have become the key issues of the photovoltaic industry. Compared with P-type crystalline silicon cells, N-type crystalline silicon cells have a long minority carrier lifetime, no photoinduced degradation, good weak light effect, and a small temperature coefficient. They are the hope for crystalline silicon solar cells to break through the theoretical maximum efficiency. TBC cells are crystalline silicon solar cells with a back contact structure. They use P+ and N+ Poly-Si as the emitter and back surface field (Back Surface Field, BSF) respectively. They are solar cells that deposit a tunneling oxide layer between Poly-Si and the silicon substrate to increase the selectivity of carriers, reduce the recombination of minority carriers, and increase the open circuit voltage of the cell. The light-receiving surface of the cell is not blocked by any metal grid lines, that is, the light-receiving surface has no electrode, so that the light incident on the cell surface can be used to a greater extent. At the same time, the back side (non-light-receiving surface) can allow wider metal grid lines to reduce the series resistance and thus improve the fill factor, plus the open circuit voltage gain brought by the front surface field of the cell and the excellent passivation effect, thereby improving the cell conversion efficiency.

[0003] Although laser technology is used to define the P and N regions of existing TBC cells on N-type silicon substrates, ordinary laser etching cannot accurately define the N and P regions due to its low precision, which causes a short circuit risk between the N and P regions, reduces the light utilization rate of the TBC cell, and reduces the conversion efficiency of the TBC cell. Summary of the invention

[0004] The present invention provides a TBC battery and a preparation method thereof, which utilizes high-precision laser conditions to achieve accurate definition of the first area and the second area on the back, reduce the shading area of ​​the first electrode and the second electrode, optimize the light utilization rate of the TBC battery, and improve the conversion efficiency of the TBC battery.

[0005] In a first aspect, the present invention provides a method for preparing a TBC battery, comprising:

[0006] Providing an N-type silicon substrate; the N-type silicon substrate comprises a front side and a back side;

[0007] Prepare a first tunneling oxide layer and a first doping layer on the back side;

[0008] Using preset laser conditions, forming a first area and a second area alternately arranged in an interdigitated shape on the back surface;

[0009] removing the first tunneling oxide layer and the first doping layer in the second region, and preparing a second tunneling oxide layer and a second doping layer in the second region;

[0010] Performing front texturing on the front side, preparing a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the front side after the front texturing;

[0011] The first region and the second region are screen printed and sintered at high temperature to form a first electrode in contact with the first doping layer in the first region and a second electrode in contact with the second doping layer in the second region, thereby manufacturing a TBC battery.

[0012] Optionally, while preparing the first tunneling oxide layer and the first doping layer on the back side, the method further includes:

[0013] forming a first mask layer on a surface of the first doped layer that is away from the N-type silicon substrate;

[0014] After forming the first and second regions alternately arranged in an interdigitated manner on the back side using a preset laser condition, the method further includes:

[0015] Using a preset laser condition, removing the first mask layer in the second area;

[0016] After preparing the second tunnel oxide layer and the second doping layer in the second region, the method further includes:

[0017] forming a second mask layer on a surface of the second doped layer that is away from the N-type silicon substrate;

[0018] The second mask layer in the first area is removed using a preset laser condition.

[0019] Optionally, while removing the second mask layer in the second area by using a preset laser condition, the method further includes:

[0020] A boundary area between the first area and the second area is removed so that a preset interval exists between the first area and the second area.

[0021] Optionally, in the preset laser conditions, the laser power is 40W-50W, and the laser speed is 30000mm / s-70000mm / s.

[0022] Optionally, the laser frequency of the laser in the preset laser condition is 400kHz-700kHz.

[0023] Optionally, the spot spacing of the laser in the preset laser condition is 70um-110um.

[0024] Optionally, the laser pulse width per second in the preset laser condition is 0.5us-1.5us.

[0025] Optionally, the laser marking time in the preset laser condition is 10s-15s.

[0026] Optionally, before preparing the first tunneling oxide layer and the first doping layer on the back side, the method further includes:

[0027] The front and back sides of the N-type silicon substrate are double-sided polished.

[0028] In a second aspect, the present invention provides a TBC battery, which is manufactured using the above-mentioned TBC battery manufacturing method.

[0029] The technical solution of the present invention provides an N-type silicon substrate; the N-type silicon substrate includes a front side and a back side; a first tunneling oxide layer and a first doping layer are prepared on the back side; a first region and a second region arranged alternately in a forked shape are formed on the back side by using preset laser conditions; the first tunneling oxide layer and the first doping layer of the second region are removed, and a second tunneling oxide layer and a second doping layer are prepared in the second region; a front surface is textured on the front side, and a first protective layer is prepared on the surface of the first doping layer and the second doping layer on the back side away from the N-type silicon substrate, and a second protective layer is prepared on the front side after the front surface is textured; the first region and the second region are screen printed and sintered at high temperature to form a first electrode in contact with the first doping layer in the first region, and a second electrode in contact with the second doping layer in the second region, so as to prepare a TBC battery. Through the above method, using high-precision preset laser conditions, the first region and the second region on the back side are accurately defined, the light shielding area of ​​the first electrode and the second electrode is reduced, the light utilization rate of the TBC battery is optimized, and the conversion efficiency of the TBC battery is improved. At the same time, it provides the possibility for narrower electrode pattern processes, improves the bifacial power generation capacity of TBC batteries, and reduces the use of metal paste and manufacturing costs.

[0030] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A flow chart of a method for preparing a TBC battery provided by an embodiment of the present invention;

[0033] Figure 2A schematic diagram of the structure of a TBC battery provided by an embodiment of the present invention;

[0034] Figure 3 A flow chart of a method for preparing a second TBC battery provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, preparation method, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] In one embodiment, Figure 1 A flowchart of a method for preparing a TBC battery provided by an embodiment of the present invention, Figure 2 A schematic diagram of the structure of a TBC battery provided by an embodiment of the present invention. This embodiment is applicable to situations where the N region and the P region on the back side of an N-type silicon substrate cannot be precisely defined, such as Figure 1 and Figure 2 As shown, the method includes:

[0038] S110 , providing an N-type silicon substrate.

[0039] The N-type silicon substrate 1 includes a front side and a back side. The front side is used for texturing and receiving photons from sunlight, and the back side is used for preparing electrodes.

[0040] S120, preparing a first tunneling oxide layer and a first doping layer on the back side.

[0041] The first tunneling oxide layer 21 is used to allow the majority carriers (electrons) to pass smoothly through the tunneling effect, while preventing the recombination of minority carriers (holes), so as to achieve selective collection of carriers, reduce surface recombination, and increase the open circuit voltage and fill factor of the battery, thereby improving the photoelectric conversion efficiency of the TBC battery. The first doping layer 22 is a boron-doped polysilicon layer, which is a special semiconductor layer with a high doping concentration formed by doping boron elements.

[0042] Specifically, a first tunnel oxide layer 21 and a first intrinsic silicon layer are sequentially deposited in the first region using a deposition process. After the first intrinsic silicon layer is formed, the first intrinsic silicon layer needs to be elementally doped to form a first doped layer 22 .

[0043] S130, using preset laser conditions, forming a first area and a second area alternately arranged in an interdigitated shape on the back surface.

[0044] Typically, the first region may be an n region or a p region, and correspondingly, the second region may be a p region or an n region.

[0045] Specifically, by using laser technology, under preset laser conditions, that is, by setting laser power, laser speed and other parameters of the laser, the first area and the second area can be accurately defined on the back side of the N-type silicon substrate 1, and the first area and the second area are arranged alternately in a forked finger shape to improve the utilization rate of sunlight, thereby improving the conversion efficiency of the TBC battery.

[0046] S140, removing the first tunneling oxide layer and the first doping layer in the second region, and preparing a second tunneling oxide layer and a second doping layer in the second region.

[0047] The second tunneling oxide layer 31 is used to allow the majority carriers (electrons) to pass smoothly through the tunneling effect, while preventing the recombination of minority carriers (holes), so as to achieve selective collection of carriers, reduce surface recombination, and increase the open circuit voltage and fill factor of the battery, thereby improving the photoelectric conversion efficiency of the TBC battery. The second doping layer 32 is a phosphorus-doped polysilicon layer, which is a special semiconductor layer with a high doping concentration formed by doping phosphorus.

[0048] Specifically, when preparing the first tunneling oxide layer 21 and the first doping layer 22 on the back side, they are formed by deposition on the entire surface. After defining the first region and the second region under the preset laser conditions, the first tunneling oxide layer 21 and the first doping layer 22 deposited in the second region need to be removed, and can be removed by alkali etching or other methods, which are not limited here. After removing the first tunneling oxide layer 21 and the first doping layer 22 in the second region, the surface of the N-type silicon substrate 1 in the second region will be exposed. At this time, the second tunneling oxide layer 31 and the second intrinsic silicon layer are prepared by deposition or other processes in the second region where the N-type silicon substrate 1 is exposed. The second intrinsic silicon layer is doped with elements so that the elements diffuse into the second intrinsic silicon layer to form the second doping layer 32. Among them, the deposition to form the second tunneling oxide layer 31 and the second intrinsic silicon layer includes but is not limited to low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or physical vapor deposition, etc., which can be determined according to actual conditions and are not limited here.

[0049] S150, performing front texturing on the front side, preparing a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the front side after the front texturing.

[0050] Among them, front texturing refers to the special treatment of the front surface of the N-type silicon substrate 1 of the TBC cell during the production process of the TBC cell to form a rough, velvet-like structure. The first protective layer and the second protective layer both include a passivation layer and an anti-reflection layer, which are used to reduce the reflection of sunlight, increase the absorption of sunlight, improve the conversion efficiency of the TBC cell, reduce surface recombination, increase the mobility of carriers, and improve the overall performance of the TBC cell.

[0051] Specifically, a texturing process is used to perform texturing on the front side of the N-type silicon substrate 1 to form a front velvet structure. After the front texturing is completed, a first protective layer 4 needs to be prepared on the surface of the first doping layer 22 and the second doping layer 32 on the back side away from the N-type silicon substrate 1. Specifically, it can be prepared and formed by deposition and other processes, which are not limited here. In addition, it is also necessary to prepare a second protective layer 5 on the front surface after the front texturing to reduce the surface reflection of the TBC battery, increase the surface area of ​​the TBC battery, and reduce the reflection of sunlight, improve the light trapping effect of the battery and the absorption rate of sunlight, generate more photogenerated carriers, and improve the conversion efficiency of the TBC battery. The texturing process may include but is not limited to trough texturing and other processes. The process for preparing the first protective layer 4 and the second protective layer 5 includes but is not limited to low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or physical vapor deposition, etc., which can be determined according to actual conditions and are not limited here.

[0052] In an optional embodiment, a trough texturing process is used to texturize the front surface under preset alkaline solution conditions to form a front velvet structure. The preset alkaline solution can be an alkaline solution formed by configuring a sodium hydroxide solution with a concentration of 0.5%-3%, a texturing additive and DIW in a preset ratio of 5:3.5:340, and the alkaline solution temperature is 70°C, the texturing time is 450s, and the weight is reduced by 0.2g-0.4g, which ensures that the front velvet structure reaches the ideal depth and density, maximizes the photon capture efficiency, and improves the photoelectric conversion efficiency of the TBC battery.

[0053] S160, screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doping layer in the first region, and a second electrode in contact with the second doping layer in the second region, to manufacture a TBC battery.

[0054] Among them, screen printing is one of the core processes in the manufacturing process of TBC battery cells, and is mainly used for electrode forming of TBC batteries. This process uses the basic principle that the mesh holes of the graphic part of the screen are transparent to the slurry, and the mesh holes of the non-graphic part are not transparent to the slurry for printing. During the printing process, the slurry is accurately squeezed onto the N-type silicon substrate 1 through the mesh holes of the screen to form the required electrode pattern. Generally, the slurry for screen printing can include but is not limited to silver paste. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to process the electrode material screen-printed on the surface of the battery cell at high temperature so that the metal grid lines form a good ohmic contact with the N-type silicon substrate 1.

[0055] Specifically, after forming the first protective layer 4 on the back side, it is necessary to form an electrode on the back side so that the photogenerated carriers generated by the solar energy are converted into electric current and then flow to the external circuit. In this embodiment, the first area and the second area on the back side are screen printed so that metal grid lines are formed on the surfaces of the first area and the second area. Specifically, the main grid lines can be printed first, and then the fine grid lines can be printed after the main grid lines are printed. After printing, the main grid lines and the fine grid lines need to be dried at a drying temperature of 370°C. After the metal grid lines are formed, the formed metal grid lines need to be sintered at a high temperature. The temperature of the high temperature sintering can be 700°C-900°C to remove the organic components in the metal slurry. After the metal particles are sintered at a high temperature, a tight conductive network is formed on the surface of the first doping layer 22 and the second doping layer 32, and the metal grid lines can be in contact with the first doping layer 22 and the second doping layer 32 to form a good ohmic contact, thereby improving the electrical performance of the battery. Specifically, after high-temperature sintering, a first electrode 6 in contact with the first doping layer 22 is formed in the first region, and a second electrode 7 in contact with the second doping layer 32 is formed in the second region, thereby preparing a TBC battery. In addition, the polarities of the first electrode 6 and the second electrode 7 are opposite. When the first electrode 6 is a positive electrode, the corresponding second electrode 7 is a negative electrode; when the first electrode 6 is a negative electrode, the corresponding second electrode 7 is a positive electrode. In this embodiment, the first region is a p region, and the second region is an n region. The corresponding first electrode 6 formed in the p region is a positive electrode, and the second electrode 7 formed in the n region is a negative electrode.

[0056] It should be noted that after forming the first electrode 6 and the second electrode 7, in the present embodiment, the TBC cell will also be subjected to light injection treatment. The temperature of the light injection heating zone is set to 200°C-550°C, and the temperature of the insulation zone is set to 80°C-150°C. The light injection temperature is adjusted to adjust the mobility and migration concentration of the hydrogen atoms released from the first protective layer 4 and the second protective layer 5. At the same time, the TBC cell absorbs photons from sunlight to generate a large number of non-equilibrium carriers, which further adjust the charge state of the penetrated hydrogen. Finally, the hydrogen atoms combine with internal defects to complete the passivation process.

[0057] The technical solution of the embodiment of the present invention is provided by providing an N-type silicon substrate; the N-type silicon substrate includes a front side and a back side; a first tunneling oxide layer and a first doping layer are prepared on the back side; a first region and a second region arranged alternately in a forked shape are formed on the back side by using preset laser conditions; the first tunneling oxide layer and the first doping layer of the second region are removed, and a second tunneling oxide layer and a second doping layer are prepared in the second region; a front surface is textured on the front side, and a first protective layer is prepared on the surface of the first doping layer and the second doping layer on the back side away from the N-type silicon substrate, and a second protective layer is prepared on the front side after the front surface is textured; the first region and the second region are screen printed and sintered at high temperature to form a first electrode in contact with the first doping layer in the first region, and a second electrode in contact with the second doping layer in the second region, so as to prepare a TBC battery. Through the above method, using high-precision preset laser conditions, the first region and the second region on the back side are accurately defined, the light shielding area of ​​the first electrode and the second electrode is reduced, the light utilization rate of the TBC battery is optimized, and the conversion efficiency of the TBC battery is improved. At the same time, it provides the possibility for narrower electrode pattern processes, improves the bifacial power generation capacity of TBC batteries, and reduces the use of metal paste and manufacturing costs.

[0058] Optionally, before S120 , forming the first tunneling oxide layer 21 and the first doping layer 22 on the back side, the method further includes: performing double-side polishing on the front side and the back side of the N-type silicon substrate 1 .

[0059] Specifically, double-sided polishing includes pre-cleaning, alkaline polishing, post-cleaning and pickling. That is to say, the loaded N-type silicon substrate 1 is immersed in a pre-cleaning tank and pre-cleaned with a mixed solution containing potassium hydroxide or sodium hydroxide and hydrogen peroxide to wash away dust and oil on the surface of the silicon wafer. After pre-cleaning, the silicon wafer enters a pure water tank for pure water cleaning to remove residual solvents. Polishing and cleaning ensure that the surface of the N-type silicon substrate 1 is flat and reduce the interference of pollutants in subsequent processes. The pre-cleaned N-type silicon substrate 1 is then alkaline polished, that is, the N-type silicon substrate 1 is immersed in an alkaline mixed solution composed of sodium hydroxide, pure water and polishing additives in a volume ratio of 10:325:2.6, the alkaline solution temperature is set to 80°C, and the processing time is 150s to remove the mechanical damage layer and organic matter on the front and back sides and improve the surface flatness. After alkali polishing, the N-type silicon substrate 1 is placed in a mixed solution of sodium hydroxide, hydrogen peroxide and pure water in a volume ratio of 3:12:325, the temperature of the mixed solution is set to 65°C, and the treatment time is 120s to remove additives and organic dirt in the alkali polishing. Finally, the N-type silicon substrate 1 is pickled, and the pickling acid solution is a mixed solution of hydrofluoric acid and pure water in a volume ratio of 20:330. The pickling solution temperature is set to room temperature and the treatment time is 120s to neutralize the alkaline solution and dehydrate to prevent the N-type silicon substrate 1 from being attached.

[0060] Figure 3This is a flow chart of a second method for preparing a TBC battery provided by an embodiment of the present invention. This embodiment refines the method for preparing a TBC battery in the above embodiment. For the contents not yet fully described in this embodiment, please refer to the above embodiment, and no further description will be given here. Figure 2 and Figure 3 As shown, the method includes:

[0061] S210 , providing an N-type silicon substrate.

[0062] S211 , preparing a first tunneling oxide layer and a first intrinsic silicon layer on the front and back sides by using a deposition process.

[0063] The deposition process includes low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, etc., which can be determined according to the specific situation and are not limited here. The first intrinsic silicon layer is a silicon material layer with intrinsic semiconductor properties. Intrinsic semiconductors refer to semiconductor materials that have neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and their conductivity mainly depends on the generation and recombination of electron-hole pairs in the material itself.

[0064] Specifically, by using a deposition process, such as a low-pressure chemical vapor deposition process, by setting the reaction chamber of the deposition process to a high temperature and introducing a certain flow rate of oxygen, an ultra-thin first tunneling oxide layer 21 can be deposited on the back to provide good interface passivation and different carrier tunneling barriers, and the thickness of the formed first tunneling oxide layer 21 is 1nm-2nm. After the first tunneling oxide layer 21 is formed, a certain flow rate of silane is introduced into the reaction chamber of the deposition process, for example, a flow rate of 100sccm-400sccm, and at a preset deposition temperature, a first intrinsic silicon layer is deposited on the surface of the first tunneling oxide layer 21 away from the N-type silicon substrate 1, and the thickness of the first intrinsic silicon layer is 250nm-350nm.

[0065] It is understandable that, since the N-type silicon substrate 1 is placed in a high-temperature furnace when depositing on the back side of the N-type silicon substrate 1, deposition is usually not performed only on the back side, but also on the front side.

[0066] S212, using a boron diffusion process to perform boron doping on the N-type silicon substrate forming the first intrinsic silicon layer to form a first doped layer.

[0067] S213, forming a first mask layer on a surface of the first doped layer that is away from the N-type silicon substrate, and forming a first mask layer on the front surface.

[0068] The boron diffusion process is a doping technology used to introduce boron atoms into the first intrinsic silicon layer to form a P-type doped region.

[0069] Specifically, boron trichloride and oxygen are introduced into the reaction chamber of the boron diffusion process, and the flow rate ratio of the introduced boron trichloride and oxygen and the diffusion temperature are set. Under the diffusion conditions, a layer of boron is deposited at low temperature on the surface of the first intrinsic silicon layer away from the N-type silicon substrate 1 by utilizing the chemical reaction between boron trichloride, oxygen and the first intrinsic silicon layer. After the boron is deposited, the boron is pushed at high temperature, and the pushing temperature is set to 900°C-950°C, so that the boron doping diffuses into the first intrinsic silicon layer to form a first doping layer 22. The concentration range of the formed first doping layer 22 is 5e19cm -3 -6e19cm -3 After high-temperature doping forms the first doping layer 22, since the boron in the doping process usually does not completely react to enter the first intrinsic silicon layer, a certain amount of residual organic matter will be generated in the reaction process. In order to prevent the residual organic matter from affecting the first doping layer 22, the residual organic matter can be post-oxidized by introducing a certain flow rate of oxygen into the post-oxidation reaction chamber so that the residual organic matter reacts with the oxygen to form a first mask layer. Usually, the first mask layer is a borosilicate glass layer, and the thickness of the formed first mask layer is 45nm-50nm.

[0070] It is understandable that the equipment for the boron diffusion process includes but is not limited to a boron diffusion furnace. When boron diffusion is performed in the equipment, double-sided diffusion is usually performed, or the N-type silicon substrate 1 is subjected to boron diffusion in a double-insertion manner. In this process, it cannot be guaranteed that the borosilicate glass layer produced by post-oxidation is only formed on the back side of the N-type silicon substrate 1. In the actual production process, the borosilicate glass layer will also be generated on the front side at the same time.

[0071] S214, using preset laser conditions to remove the first mask layer in the second area.

[0072] Specifically, since the first tunneling oxide layer 21 and the first doping layer 22 are formed by full-surface deposition and diffusion on the back, the back of the TBC battery needs to be provided with two interdigitated first and second regions for forming electrodes. Therefore, it is necessary to remove the first mask layer, the first doping layer 22 and the first tunneling oxide layer 21 formed in the second region. In this embodiment, an ultrashort pulse laser is used to remove the first mask layer on the back by laser etching under preset laser conditions, and the heat-affected area is small, thereby reducing damage to other areas. In this embodiment, the laser power in the preset laser conditions is 40W-50W, the laser speed is 30000mm / s-70000mm / s, the laser frequency is 400kHz-700kHz, the laser spot spacing is 70um-110um, and the laser marking time is 10s-15s. Among them, the laser power can be determined according to the single spot energy and the laser frequency of the laser, and can be obtained by multiplying the single spot energy and the laser frequency of the laser, which is not limited here. The laser pulse can be determined according to the laser frequency, which can be obtained by multiplying the inverse of the laser frequency by a preset constant, and is not limited here. The laser spot spacing can be determined according to the laser speed and the laser frequency, which can be obtained by dividing the laser speed and the laser frequency, and is not limited here. For example, when removing the first mask layer, the laser spot spacing can be set to 75um, the laser overlap rate is 50%, the laser speed is 37500mm / s, the laser frequency is 500kHz, the laser power is 45W, the laser pulse width is 1us, and the laser marking time is 10s. Among them, the repetition rate of the laser can be determined according to the laser spot size and the spot spacing, which can be obtained by dividing the difference between the spot size and the spot spacing by the spot size, and is not limited here.

[0073] S215, removing the first doping layer and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region, and removing the first mask layer, the first doping layer and the first tunneling oxide layer on the front side.

[0074] Among them, this step can be refined as follows: using an alkaline etching process to remove the first doping layer 22 in the second region, and the first mask layer and the first doping layer on the front side; using an acid etching process to remove the first tunneling oxide layer 21 in the second region, and the first tunneling oxide layer on the front side, exposing the N-type silicon substrate 1.

[0075] The alkaline etching process is a process of removing the first doping layer 22 by chemically reacting the alkaline solution with the first doping layer 22 using a prepared alkaline solution. The acid etching process, i.e., chain acid etching, is a wet etching technology widely used in the field of solar cell manufacturing, which mainly involves chemically treating the surface of a silicon wafer using a prepared acidic solution to achieve the purpose of removing a specific material layer or forming a specific structure.

[0076] Specifically, after removing the first mask layer, the first doping layer 22 and the first tunneling oxide layer 21 need to be removed, that is, by introducing an alkaline solution formed by an alkaline solution such as sodium hydroxide or potassium hydroxide, pure water and an etching additive in a volume ratio of 25:325:3.5 into the reaction chamber of the alkaline etching process, using the configured alkaline solution, by setting the etching temperature to 78° C., the etching time to 270s, and the etching amount to 0.3g-0.5g, using the chemical reaction between the alkaline solution and the first doping layer 22, the first doping layer 22 in the second region is removed, and the first tunneling oxide layer 21 in the second region is exposed. After removing the first doping layer 22, by using an acid etching process, by setting an acidic solution such as hydrofluoric acid, and setting the concentration of the hydrofluoric acid in a certain range, such as 5%-30%, the hydrofluoric acid will react chemically with the first tunneling oxide layer 21, and the first tunneling oxide layer 21 in the second region is removed, thereby exposing the N-type silicon substrate 1 in the second region. It is understandable that, in order to reduce the battery preparation time, the first doping layer 22 and the first tunneling oxide layer 21 can be removed by etching in different tanks in the tank cleaning equipment.

[0077] In addition, because the front side needs to be textured, the first mask layer, the first doping layer and the first tunneling oxide layer formed on the front side also need to be removed. Specifically, the conditions for removing the first mask layer and the first doping layer on the front side can be set to be consistent with the conditions for removing the first doping layer in the second area on the back side, and the conditions for removing the first tunneling oxide layer on the front side can be set to be consistent with the conditions for removing the first tunneling oxide layer in the second area on the back side. For details, please refer to the above embodiment and will not be repeated here.

[0078] S216, using a deposition process, preparing a second tunneling oxide layer and a second intrinsic silicon layer on the surface of the N-type silicon substrate and the first mask layer in the exposed second region away from the N-type silicon substrate, and forming a second tunneling oxide layer and a second intrinsic silicon layer on the front side.

[0079] The second intrinsic silicon layer has the same meaning as the first intrinsic silicon layer, and reference may be made to the above description, which will not be repeated here.

[0080] Specifically, after the N-type silicon substrate 1 in the second region is exposed, a deposition process can be used to introduce a certain flow rate of nitrogen oxide gas into the reaction chamber of the deposition process, and under certain deposition conditions, a second tunneling oxide layer 31 with a thickness of 1nm-2nm is deposited on the first region and the second region on the back side of the N-type silicon substrate 1. After the second tunneling oxide layer 31 is formed, a certain flow rate of silane is introduced into the reaction chamber of the deposition process, and under preset deposition conditions, a second intrinsic silicon layer is deposited on the surface of the second tunneling oxide layer 31 away from the N-type silicon substrate 1.

[0081] It is understandable that, since the N-type silicon substrate 1 is placed in a high-temperature furnace when depositing the second region of the N-type silicon substrate 1, deposition is usually not performed only on the back side, but also on the front side.

[0082] S217, using a phosphorus diffusion process to perform phosphorus doping on the N-type silicon substrate forming the second intrinsic silicon layer to form a second doped layer.

[0083] S218, forming a second mask layer on a surface of the second doped layer that is away from the N-type silicon substrate, and forming a second mask layer on the front surface.

[0084] The phosphorus diffusion process is a process for forming an N-type region by phosphorus diffusion on an N-type silicon substrate 1, thereby forming a PN junction. The PN junction is responsible for separating photogenerated carriers (electron-hole pairs) to achieve photoelectric conversion.

[0085] Specifically, similar to the formation process of the first doped layer 22, a certain flow of nitrogen and oxygen is introduced into the reaction chamber of the low-temperature deposition process, phosphorus oxychloride is doped in the nitrogen, and phosphorus oxychloride is the doping source of the phosphorus diffusion process. Under certain deposition conditions, a layer of phosphorus can be deposited on the surface of the second intrinsic silicon layer away from the N-type silicon substrate 1 by utilizing the chemical reaction between phosphorus oxychloride and oxygen. After the phosphorus is formed, the phosphorus is high-temperature promoted, and the promotion temperature of the high-temperature promotion is set to 850°C-950°C, so that the phosphorus is diffused into the second intrinsic silicon layer to form a second doped layer 32. The doping concentration of the second doped layer 32 is 4e20cm -3 -5e20cm -3 After forming the second doping layer 32, the residual organic matter generated during the doping process is post-oxidized, and a certain flow rate of oxygen is introduced into the post-oxidation reaction chamber so that the residual organic matter reacts with the oxygen to form a second mask layer. Usually, the second mask layer is a phosphorus silicon glass layer.

[0086] It is understandable that the equipment for the phosphorus diffusion process includes but is not limited to a phosphorus diffusion furnace. When phosphorus diffusion is performed in the equipment, double-sided diffusion is usually performed, or the N-type silicon substrate 1 is phosphorus diffused in a double-insertion manner. In this process, it cannot be guaranteed that the phosphosilicate glass layer produced by post-oxidation is only formed on the back side of the N-type silicon substrate 1. In the actual production process, the phosphosilicate glass layer will also be generated on the front side at the same time.

[0087] S219, using preset laser conditions, removing the second mask layer in the first area, and removing the boundary area between the first area and the second area, so that there is a preset interval between the first area and the second area.

[0088] Specifically, the preset laser conditions for removing the second mask layer are the same, that is, the laser power in the preset laser conditions is 40W-50W, the laser speed is 30000mm / s-70000mm / s, the laser frequency is 400kHz-700kHz, the laser spot spacing is 70um-110um, and the laser marking time is 10s-15s. Exemplarily, when removing the second mask layer and the boundary area between the first area and the second area, the laser spot spacing can be set to 100um, the laser overlap rate is 33.3%, the laser speed is 60700mm / s, the laser frequency is 607kHz, the laser power is 41.5W, the laser pulse width is 0.8us, and the laser marking time is 11s.

[0089] It should be noted that, in order to prevent a short circuit between the first region and the second region, when the second mask layer of the first region is etched and removed, the boundary region of the first region and the second region is simultaneously etched and removed, so that there is a preset interval between the first region and the second region, thereby establishing independent electron and hole transmission channels on the back of the TBC battery. The specific etching conditions can be the same as the conditions for removing the second mask layer mentioned above to ensure the performance of the TBC battery.

[0090] S220 , removing the second mask layer, the second doping layer, and the second tunneling oxide layer from the front side and the first region.

[0091] Among them, this step can be refined as: using an alkaline etching process to remove the second doping layer 32 in the first region, and the second mask layer and the second doping layer on the front side; using an acid etching process to remove the second tunneling oxide layer 31 in the first region, and the second tunneling oxide layer on the front side.

[0092] Specifically, the second tunneling oxide layer 31, the second doping layer 32 and the second mask layer are all deposited on the entire surface, that is, the above three-layer structure is also deposited in the first region. At this time, the second tunneling oxide layer 31, the second doping layer 32 and the second mask layer in the first region need to be removed. In this embodiment, an alkaline etching process is used, and an alkaline solution formed by an alkaline solution such as sodium hydroxide or potassium hydroxide, pure water and an etching additive with a volume ratio of 25:325:3.5 is introduced into the reaction chamber of the alkaline etching process. Under the etching conditions, the second doping layer 32 in the first region is removed by a chemical reaction between the alkaline solution and the second doping layer 32, and the second tunneling oxide layer 31 in the first region is exposed. After the second tunneling oxide layer 31 in the first region is exposed, an acid etching process is used, and an acidic solution such as hydrofluoric acid is set, and the concentration of the hydrofluoric acid is set within a certain range. The hydrofluoric acid will react chemically with the second tunneling oxide layer 31 to remove the second tunneling oxide layer 31 in the first region.

[0093] In addition, because the front side needs to be textured, the first mask layer, the first doping layer and the first tunneling oxide layer formed on the front side also need to be removed. Specifically, the conditions for removing the first mask layer and the first doping layer on the front side can be set to be consistent with the conditions for removing the first doping layer in the second area on the back side, and the conditions for removing the first tunneling oxide layer on the front side can be set to be consistent with the conditions for removing the first tunneling oxide layer in the second area on the back side. For details, please refer to the above embodiment and will not be repeated here.

[0094] S221. Use a velvet making process to perform velvet making on the front side to form a velvet structure.

[0095] S222 , removing the first mask layer in the first area and the second mask layer in the second area.

[0096] Specifically, after removing the first mask layer and the second mask layer on the front side, the front side can be textured under preset texture conditions using a texture making process. The specific texture making process can be set according to actual conditions and is not limited here. After the texture making is completed, the first mask layer in the first area and the second mask layer in the second area need to be etched and removed. They can also be etched and removed using an acidic solution such as hydrofluoric acid that has been preset. The process steps for removing the first mask layer in the first area and the second mask layer in the second area are set after the texture making process on the front side. The purpose is to not affect the first doping layer 22 and the second doping layer 32 on the back side during the texture making process on the front side. The first mask layer and the second mask layer play a protective role to ensure the performance of the TBC battery.

[0097] In addition, after the velvet structure is formed on the front side, the velvet structure needs to be cleaned to remove the etching byproducts and impurities remaining on the surface of the N-type silicon substrate 1, such as silicate residues, metal ion impurities, organic pollutants, etching product particles, etc. The cleaning conditions can be set to a mixed solution formed by configuring sodium hydroxide, hydrogen peroxide and pure water in a volume ratio of 3:12:335, a cleaning temperature of 65°C, and a cleaning time of 120s.

[0098] S223, using a deposition process, preparing a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the surface of the suede structure on the side away from the N-type silicon substrate.

[0099] Specifically, after the first mask layer in the first region and the second mask layer in the second region are removed, a first protective layer 4 needs to be prepared on the surface of the first doping layer 22 and the second doping layer 32 on the back side away from the N-type silicon substrate 1. The first protective layer 4 includes a first passivation layer and a first anti-reflection layer. In this embodiment, an atomic layer deposition process is used to introduce TMA and a certain amount of water into the reaction chamber of the atomic layer deposition, and the number of cycles is set to 30. Under this condition, a first passivation layer is deposited on the surface of the first doping layer 22 and the second doping layer 32 on the back side. The components of the first passivation layer include but are not limited to aluminum oxide, silicon oxide, or a combination of aluminum oxide and silicon oxide. The thickness of the first passivation layer is 4nm-5nm. The first passivation film layer on the back side of the TBC battery contains a large amount of fixed negative charges, which can produce an efficient field passivation effect on the surface of the N-type silicon substrate 1; at the same time, a large amount of hydrogen atoms can be stored in the first passivation film, which can be released during the heat treatment process to saturate the dangling bonds on the surface of the N-type silicon substrate 1, producing a good chemical passivation effect. Secondly, a first anti-reflection layer is deposited on the surface of the first passivation layer away from the N-type silicon substrate 1 by using a deposition process such as plasma enhanced chemical vapor deposition. The components of the first anti-reflection layer may include but are not limited to silicon nitride, or a combination of silicon nitride and silicon oxide, or silicon oxynitride. The thickness of the first anti-reflection layer is 75nm-80nm. In addition, a second protective layer 5 needs to be prepared on the front side. The second protective layer 5 includes a second passivation layer and a second anti-reflection layer. Specifically, an atomic layer deposition process can be used to deposit the second passivation layer on the surface of the velvet structure on the front side away from the N-type silicon substrate 1. The components of the second passivation layer include but are not limited to aluminum oxide, silicon oxide, or a combination of aluminum oxide and silicon oxide. The thickness of the formed second passivation layer is 4nm-5nm. After the second passivation layer is formed, a second anti-reflection layer may be deposited on the surface of the second passivation layer facing away from the N-type silicon substrate 1 by a deposition process such as plasma enhanced chemical vapor deposition. The components of the second anti-reflection layer may include but are not limited to silicon nitride, or a combination of silicon nitride and silicon oxide, or silicon nitride oxide. The thickness of the formed second anti-reflection layer is 80nm-85nm, thereby forming a second protective layer 5.

[0100] It should be noted that, usually, in the process of preparing the passivation layer on the front and back sides, an atomic layer deposition process is usually used to deposit the passivation layer on the front and back sides simultaneously, so as to reduce the process flow and shorten the preparation time.

[0101] S224, screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doping layer in the first region, and a second electrode in contact with the second doping layer in the second region, to manufacture a TBC battery.

[0102] The technical solution of the embodiment of the present invention comprises the following steps: using a deposition process to prepare a first tunneling oxide layer and a first intrinsic silicon layer in a first region and a second region; using a boron diffusion process to boron-dope an N-type silicon substrate forming the first intrinsic silicon layer under a preset high temperature condition to form a first doping layer, and forming a first mask layer on the front surface and the surface of the first doping layer; removing the first mask layer, the first doping layer and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region; using a deposition process to prepare a second tunneling oxide layer and a second intrinsic silicon layer on the surface of the N-type silicon substrate and the first mask layer in the exposed second region away from the N-type silicon substrate; using a phosphorus diffusion process to dope the N-type silicon substrate in the second region to form a first doping layer; and The method comprises the following steps: using a dispersion process to dope the N-type silicon substrate forming the second intrinsic silicon layer with phosphorus to form a second doped layer; forming a second mask layer on the front surface and the surface of the second doped layer; removing the second mask layer, the second doped layer and the second tunneling oxide layer in the first region; removing the first mask layer and the second mask layer on the front surface; using a texturing process to perform front texturing on the front surface to form a velvet structure; removing the first mask layer in the first region and the second mask layer in the second region; using a deposition process to prepare a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the surface of the velvet structure away from the N-type silicon substrate. The above method is used to realize the preparation of TBC batteries, improve the passivation effect, effectively inhibit the recombination of electrons and holes, reduce surface defects, improve the opening voltage and fill factor of TBC batteries, and thus improve the conversion rate and surface quality of TBC batteries.

[0103] Based on the same inventive concept, an embodiment of the present invention further provides a TBC battery, which is manufactured using the above-mentioned TBC battery preparation method and has functional modules and beneficial effects corresponding to the execution method.

[0104] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0105] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a TBC battery, characterized in that: include: Providing an N-type silicon substrate; The N-type silicon substrate comprises a front side and a back side; Prepare a first tunneling oxide layer and a first doping layer on the back side; Using a preset laser condition, forming a first region and a second region alternately arranged in an interdigitated shape on the back surface; removing the first tunneling oxide layer and the first doping layer in the second region, and preparing a second tunneling oxide layer and a second doping layer in the second region; Performing front texturing on the front side, preparing a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the front side after the front texturing; The first region and the second region are screen printed and sintered at high temperature to form a first electrode in contact with the first doping layer in the first region, and a second electrode in contact with the second doping layer in the second region, so as to manufacture a TBC battery.

2. The preparation method according to claim 1, characterized in that: While preparing the first tunneling oxide layer and the first doping layer on the back side, the method further includes: forming a first mask layer on a surface of the first doped layer that is away from the N-type silicon substrate; After forming the first and second regions alternately arranged in an interdigitated manner on the back side by using a preset laser condition, the method further comprises: Using the preset laser conditions, removing the first mask layer in the second area; After preparing the second tunneling oxide layer and the second doping layer in the second region, the method further includes: forming a second mask layer on a surface of the second doped layer that is away from the N-type silicon substrate; The second mask layer in the first area is removed using the preset laser conditions.

3. The preparation method according to claim 2, characterized in that: While removing the second mask layer in the second area by using the preset laser condition, the method further includes: A boundary area between the first area and the second area is removed so that a preset interval exists between the first area and the second area.

4. The preparation method according to claim 3, characterized in that: The laser power of the laser in the preset laser conditions is 40W-50W, and the laser speed is 30000mm / s-70000mm / s.

5. The preparation method according to claim 3, characterized in that: The laser frequency of the laser in the preset laser condition is 400kHz-700kHz.

6. The preparation method according to claim 3, characterized in that: The spot spacing of the laser in the preset laser condition is 70um-110um.

7. The preparation method according to claim 3, characterized in that: The laser pulse width per second in the preset laser condition is 0.5us-1.5us.

8. The preparation method according to claim 3, characterized in that: The laser marking time in the preset laser conditions is 10s-15s.

9. The preparation method according to claim 1, characterized in that: Before preparing the first tunneling oxide layer and the first doping layer on the back side, the method further includes: The front side and the back side of the N-type silicon substrate are double-sided polished.

10. A TBC battery, characterized in that: The TBC battery is prepared by the preparation method of any one of claims 1 to 9.

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