Solar cell and method of manufacturing the same

Abstract

The application relates to a solar cell and a preparation method thereof, the solar cell comprising a first electrode, a first passivation layer, a semiconductor substrate, a second passivation layer and a second electrode arranged in sequence from top to bottom, the semiconductor substrate being provided with a plurality of first grooves arranged at intervals on the front surface, the first electrode being arranged in the first grooves, and the surface of the semiconductor substrate in the first grooves being in contact with the first passivation layer being provided with a first polarizing structure and / or at least one sidewall of the first electrode being provided with a third polarizing structure. The application reduces the light shielding area of the electrode by arranging grooves on the semiconductor substrate before texturing, and the polarizing structure is obtained through secondary texturing treatment, the polarizing structure can increase the folding times of light, so that the light path is longer when the sunlight is irradiated, light absorption is promoted, and the photoelectric conversion efficiency of the cell is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor solar cell technology, and in particular to solar cells and their fabrication methods. Background Technology

[0002] With the continuous development of market demand and industry technology, solar cell technology has received increasing attention in recent years. Traditionally, solar cell electrodes are printed on the light-receiving surface of the solar cell. Reducing the shading area of ​​the electrode grid lines on the light-receiving surface of the solar cell is an important direction for improving the conversion efficiency of solar cells. In the production process of solar cells, the shading problem of the metal grid lines of the cell electrodes leads to a reduction in the light flux entering the cell body, resulting in a lower short-circuit current of the solar cell. In addition, solar cells printed by screen printing also have the problem of low tension of the electrode grid. Conventionally, the tension is increased by increasing the amount of resin in the paste. However, increasing the amount of resin in the paste will increase the resistivity of the cell.

[0003] Therefore, there is an urgent need to develop a solar cell that can solve the above problems.

[0004] Application content

[0005] In view of this, in order to overcome the above-mentioned defects, this application provides a solar cell and a method for preparing the same, which can reduce the light-blocking loss of the electrodes, enhance the light-trapping effect of the cell, strengthen light absorption, and thus improve the photoelectric conversion efficiency of the solar cell.

[0006] In a first aspect, embodiments of this application provide a solar cell, the solar cell comprising a first electrode, a first passivation layer, a semiconductor substrate, a second passivation layer, and a second electrode arranged sequentially from top to bottom. The semiconductor substrate has a plurality of spaced first trenches on its front side, the first electrode is disposed in the first trench, and the surface of the semiconductor substrate located in the first trench that contacts the first passivation layer is provided with a first polarization structure and / or at least one sidewall of the first electrode is provided with a third polarization structure.

[0007] Optionally, a plurality of second trenches are formed on the back side of the semiconductor substrate, the second electrode is disposed in the second trench, and the surface of the semiconductor substrate in contact with the second passivation layer located in the second trench is provided with a second polarization structure and / or at least one sidewall of the second electrode is provided with a fourth polarization structure.

[0008] Optionally, the morphology of at least one of the first polarizing structure, the second polarizing structure, the third polarizing structure, and the fourth polarizing structure includes any one of the following: arc-shaped pit, spherical, conical, columnar, and pen-shaped.

[0009] Optionally, the height of at least one of the first, second, third, and fourth polarizing structures is 50 nm to 1800 nm, the width of at least one of the first, second, third, and fourth polarizing structures is 40 nm to 1500 nm, the height-to-width ratio of the first polarizing structure is (0.3 to 2.0):1, the height-to-width ratio of the second polarizing structure is (0.3 to 2.0):1, the height-to-width ratio of the third polarizing structure is (0.3 to 2.0):1, and the height-to-width ratio of the fourth polarizing structure is (0.3 to 2.0):1.

[0010] Optionally, the width of the first trench and / or the second trench is 20 μm to 50 μm, the height of the first trench is 5% to 90% of the height of the first electrode, and / or the height of the second trench is 5% to 90% of the height of the second electrode.

[0011] Optionally, a first gap is provided between the first electrode and at least one sidewall of the first trench and / or a second gap is provided between the second electrode and at least one sidewall of the second trench, wherein the first gap is filled with a first nano-light-trapping layer and / or the second gap is filled with a second nano-light-trapping layer.

[0012] Optionally, the solar cell includes at least one of the following technical features a to c:

[0013] a. The thickness of the first nano-light-trapping layer and / or the second nano-light-trapping layer is 50 nm to 1000 nm;

[0014] b. The first nano-light-trapping layer and / or the second nano-light-trapping layer comprises any one of polystyrene, silicon dioxide, zinc oxide, gold, and silver;

[0015] c. The first nano-light-trapping layer and / or the second nano-light-trapping layer are monolayer structures.

[0016] Optionally, the width of the first gap and / or the second gap is 50 nm to 1000 nm.

[0017] Optionally, the first passivation layer includes an amorphous silicon passivation layer.

[0018] Secondly, embodiments of this application provide a method for preparing a solar cell, comprising the following steps:

[0019] A semiconductor substrate is provided, and a plurality of spaced first trenches are formed on the front side of the semiconductor substrate; a first texturing process is performed on the front side of the semiconductor substrate to form a surface texture structure, and a second texturing process is performed on the surface texture structure in the first trenches, so that the surface texture structure in the first trenches is transformed into a first polarizing structure.

[0020] A first passivation layer is deposited on the front side of the semiconductor substrate after secondary texturing, and a first electrode is formed in the first trench where the first passivation layer is formed, thereby obtaining a solar cell.

[0021] Optionally, the method further includes:

[0022] A plurality of spaced-apart second trenches are formed on the back side of the semiconductor substrate;

[0023] The back side of the semiconductor substrate is texturized once to form a surface texture structure, and the surface texture structure in the second trench is texturized a second time to transform the surface texture structure in the second trench into a second polarization structure.

[0024] A second passivation layer is deposited on the back side of the semiconductor substrate after secondary texturing, and a second electrode is formed in the second trench where the second passivation layer is formed.

[0025] Optionally, the method further includes:

[0026] A third polarizing structure is formed on at least one sidewall of the first electrode and / or a fourth polarizing structure is deposited on at least one sidewall of the second electrode.

[0027] Optionally, the morphology of at least one of the first polarizing structure, the second polarizing structure, the third polarizing structure, and the fourth polarizing structure includes any one of the following: arc-shaped pit, spherical, conical, columnar, and pen-shaped.

[0028] Optionally, the height of at least one of the first, second, third, and fourth polarizing structures is 50 nm to 1800 nm, the width of at least one of the first, second, third, and fourth polarizing structures is 40 nm to 1500 nm, the height-to-width ratio of the first polarizing structure is (0.3 to 2.0):1, the height-to-width ratio of the second polarizing structure is (0.3 to 2.0):1, the height-to-width ratio of the third polarizing structure is (0.3 to 2.0):1, and the height-to-width ratio of the fourth polarizing structure is (0.3 to 2.0):1.

[0029] Optionally, the method further includes:

[0030] A first gap is formed between the first electrode and at least one sidewall of the first trench, and / or a second gap is formed between the second electrode and at least one sidewall of the second trench. A nano-light-trapping suspension is filled into the first gap and / or the second gap using any one of the following methods: micro-push injection, lifting, evaporation, and spin coating, so that a first nano-light-trapping layer is formed in the first gap and / or a second nano-light-trapping layer is formed in the second gap. The nano-light-trapping suspension includes a suspension containing at least one of polystyrene, silica, zinc oxide, gold, and silver.

[0031] Thirdly, embodiments of this application provide a photovoltaic module, which includes multiple solar cell strings, each solar cell string including the solar cell described in the first aspect or the solar cell prepared by the preparation method described in the second aspect.

[0032] The beneficial effects of this application are:

[0033] (1) This application obtains polarization structures in the form of arc-shaped pits, spheres, cones, inverted pyramids, columns, and pens by performing secondary texturing on the semiconductor substrate in the first and second trenches after a primary texturing process and by processing the electrode sidewalls. The polarization structures can increase the refraction and reflection of light, resulting in a longer light path when sunlight is irradiated. Furthermore, the polarization structures can reduce the aspect ratio of the surface texture structure formed by the primary texturing process, thereby reducing the light-shielding area of ​​the electrode, promoting light absorption, and thus improving the photoelectric conversion efficiency of the battery.

[0034] (2) In this application, a gap is formed between the electrode and the trench during screen printing and a nano light trapping layer is filled in. The nano light trapping layer can reduce the reflectivity of the battery surface, thereby enhancing light absorption and improving the photoelectric conversion efficiency of the battery. Attached Figure Description

[0035] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0036] Figure 1 This is a schematic diagram of the structure of the solar cell in this application;

[0037] Figure 2 This is a SEM image of the surface texture structure of a conventional solar cell.

[0038] Figure 3 This is a SEM image of the polarization structure of the solar cell in this application;

[0039] Figure 4 This is a schematic diagram of the structure of the solar cell containing the nano-light-trapping layer in this application;

[0040] Figure 5 The fabrication process of the solar cell of this application Figure 1;

[0041] Figure 6 The fabrication process of the solar cell of this application Figure 2 ;

[0042] Figure 7 This is a SEM image of the nano-light-trapping layer in this application;

[0043] Figure 8 This is a schematic diagram of a conventional heterojunction solar cell.

[0044] Figure 9 This is a schematic diagram of the heterojunction solar cell structure of this application.

[0045] In the picture:

[0046] 100 - First electrode;

[0047] 200 - First passivation layer;

[0048] 300 - Semiconductor substrate;

[0049] 400 - Second passivation layer;

[0050] 500 - Second electrode;

[0051] 600 - First trench;

[0052] 700 - Second trench;

[0053] 800 - First gap;

[0054] 900 - Second gap;

[0055] 110 - First nanometer light-trapping layer;

[0056] 120 - Second nanometer light-trapping layer;

[0057] 130 - First amorphous silicon film layer;

[0058] 140-P type amorphous silicon doped layer;

[0059] 150 - First TCO conductive layer;

[0060] 160 - Second amorphous silicon film layer;

[0061] 170-N type amorphous silicon doped layer;

[0062] 180 - Second TCO conductive layer. Detailed Implementation

[0063] The following are preferred embodiments of the present application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of the embodiments of the present application, and these improvements and modifications should also be considered within the protection scope of the embodiments of the present application.

[0064] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0065] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0066] In a first aspect, embodiments of this application provide a solar cell, such as... Figure 1 The diagram shows the structure of the solar cell of this application. The solar cell includes a first electrode 100, a first passivation layer 200, a semiconductor substrate 300, a second passivation layer 400, and a second electrode 500 arranged sequentially from top to bottom. The semiconductor substrate 300 has a plurality of spaced first trenches 600 on its front side. The first electrode 100 is disposed in the first trenches 600. The surface of the semiconductor substrate 300 in contact with the first passivation layer 200 in the first trenches 600 is provided with a first polarizing structure. It can be understood that the first polarizing structure can be disposed at the bottom and / or sidewall of the first trench. A third polarizing structure can also be disposed on at least one sidewall of the first electrode. It can be understood that the third polarizing structure can be disposed on one sidewall of the first electrode 100, or on two, three, or four sidewalls of the first electrode 100. The specific number of structures disposed is selected according to the light absorption capacity requirements of the cell.

[0067] It is understandable that a "polarizing structure" refers to a micro- or nano-sized structure that can refract or reflect light to enhance light absorption.

[0068] To achieve greater light absorption, multiple spaced second trenches 700 can be formed on the back side of the semiconductor substrate 300. The second electrode 500 is disposed within the second trenches 700. A second polarizing structure is provided on the surface of the semiconductor substrate 300 in contact with the second passivation layer 400 within the second trenches. Understandably, the second polarizing structure can be disposed at the bottom and / or sidewalls of the second trenches. A fourth polarizing structure can also be disposed on at least one sidewall of the second electrode 500. Understandably, the fourth polarizing structure can be disposed on one, two, three, or four sidewalls of the second electrode 500. The specific number of structures is selected according to the light absorption capacity requirements of the battery. It is worth noting that since the bottom of the electrode is blocked and cannot absorb light, a polarizing structure is not required at the bottom of the electrode.

[0069] In the above technical solution, by setting a first trench 600 and a second trench 700 on the surface of the semiconductor substrate 300, the function of the trench is to: embed the electrode in the trench to reduce light shading, thereby increasing the light flux entering the solar cell; and set a polarizing structure in the trench and / or on the sidewall of the electrode to enhance the electrode's capture of light, reduce optical loss, thereby enhancing the light absorption capacity of the cell and improving the solar energy conversion efficiency.

[0070] In some embodiments, the morphology of at least one of the first, second, third, and fourth polarizing structures includes any one of the following: arc-shaped pits, spherical, conical, columnar, inverted pyramidal, and pen-shaped. A conventional method is to texturize the semiconductor substrate 300 to obtain a textured surface structure, such as... Figure 2 As shown, the conventional surface texture structure is a "positive pyramid" structure. A passivation layer is then applied to this surface texture structure, and finally, electrodes are screen-printed. This application transforms the conventional textured surface or surface texture structure within the grooves into a polarizing structure with a specific morphology by performing a secondary texturing process on top of the initial texturing. Figure 3 The diagram shown is a schematic representation of the morphology of the polarizing structure of this application. By controlling the process parameters, the prepared polarizing structure can be a concave, arc-shaped structure. Figure 3 (a) Inverted pyramid Figure 3 (b) Columnar Figure 3 (c) and pen-shaped Figure 3 (d) Conical Figure 3 (e) Spherical Figure 3(f) The polarizing structure of this application is essentially a micro-nano scale light-trapping structure. During sunlight irradiation, this polarizing structure allows sunlight to undergo more light folding and reflection cycles, enabling the battery to utilize more light and thus increasing the number of light-trapping round trips, thereby further improving the light-trapping effect. Furthermore, compared to the "positive pyramid" textured structure, the polarizing structure of this application has a smaller aspect ratio, which reduces contact recombination between the electrode and the semiconductor substrate, and reduces the surface recombination rate of charge carriers. In addition, the polarizing structure of this application overcomes the problem of increased surface recombination rate caused by the increased surface area of ​​the traditional "positive pyramid" structure.

[0071] In some embodiments, the morphologies of the first polarizing structure, the second polarizing structure, the third polarizing structure, and the fourth polarizing structure may be the same or different, but their morphologies are all within the scope defined in this application.

[0072] In some embodiments, the height of at least one of the first, second, third, and fourth polarizing structures is 50 nm to 1800 nm, specifically 50 nm, 100 nm, 500 nm, 700 nm, 1000 nm, 1500 nm, 1800 nm, etc. The width of at least one of the first, second, third, and fourth polarizing structures is 40 nm to 1500 nm, specifically 40 nm, 100 nm, 500 nm, 1000 nm, 1200 nm, 1500 nm, etc. Specifically, the width of the polarizing structures in this application refers to the maximum width. For example, for a conical polarizing structure, its width refers to the width of the bottom of the cone; for a pen-shaped polarizing structure, its width refers to the width of the pen tip. The height-to-width ratio of the first polarizing structure is (0.3-2.0):1, the height-to-width ratio of the second polarizing structure is (0.3-2.0):1, the height-to-width ratio of the third polarizing structure is (0.3-2.0):1, and the height-to-width ratio of the fourth polarizing structure is (0.3-2.0):1. Specifically, for a columnar polarizing structure, the height-to-width ratio is (0.3–2.0):1, where the height is 300 nm–1500 nm and the width is 500 nm–1000 nm; for a pencil-shaped polarizing structure, the height-to-width ratio is (0.6–1.8):1, where the height is 600 nm–1800 nm and the width is 500 nm–1000 nm; for a spherical polarizing structure, the height-to-width ratio is (0.8–1.20):1, where the height is 50 nm–500 nm and the width is 40 nm–625 nm; and for a conical polarizing structure, the height-to-width ratio is (0.3–1.5):1. The height ranges from 300nm to 1500nm, and the width from 200nm to 1200nm. For the arc-shaped pit-like polarizing structure, its height is represented by its depth, with a depth-to-width ratio of (0.4–0.6):1, where the depth is 50nm–800nm ​​and the width is 80nm–1500nm. For the inverted pyramid-shaped polarizing structure, its height is represented by its depth, where the depth is 100nm–1000nm and the width is 120nm–1200nm, with a depth-to-width ratio of (0.5–0.8):1. If the aspect ratio of the polarizing structure is too small, the light absorption capacity cannot meet the requirements. If the aspect ratio is too large, the specific surface area of ​​the light-trapping structure under the polarizing structure increases rapidly, leading to an increase in the number of surface recombination sites. The conventional "positive pyramid" structure typically has a height of 1µm–5µm, which is relatively large in size and has a large surface area. This increases the metal recombination between the electrode and the semiconductor substrate, which is not conducive to improving the photoelectric conversion efficiency of the battery.The polarizing structure designed in this application has a height at the micro-nano level, or even at the nanometer level. During the process of sunlight irradiation, the polarizing structure has more light folding and reflection times compared to the "positive pyramid" structure, which allows the battery to utilize more light, thereby increasing the number of light trapping round trips and enhancing the light trapping effect.

[0073] In some embodiments, the width of the first trench 600 and / or the second trench 700 is 20µm to 50µm. Specifically, the width of the first trench 600 and / or the second trench 700 can be 20µm, 30µm, 40µm, 50µm, etc. The function of the trench is to accommodate the electrode. The width of the trench is greater than or equal to the width of the electrode. If the width of the trench is too large, the size of the semiconductor substrate 300 will increase, which will restrict the development of the battery. If the width of the trench is too small, it cannot accommodate the electrode and will not play a role in improving the light flux. The height of the first trench 600 is 5% to 90% of the height of the first electrode 100, and the height of the second trench 700 is 5% to 90% of the height of the second electrode 500. Specifically, the height of the first trench 600 can be 5%, 10%, 20%, or 30% of the height of the first electrode 100. The height of the second trench 700 can be 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, etc., which are the heights of the second electrode 500. Generally, the heights of the first trench 600 and the second trench 700 can be set from 50nm to 1μm. Within the selectable range, the higher the trench height, the less light will be blocked by the electrode. Since the battery assembly will be soldered later, the upper limit of the height of the first trench 600 is set to 90% of the height of the first electrode 100, and the upper limit of the height of the second trench 700 is set to 90% of the height of the second electrode 500. In addition, the cross-sectional shape of the first trench 600 and the second trench 700 includes rectangle, teardrop, trapezoid, etc., which serve to accommodate the electrode and are not limited here.

[0074] In some embodiments, when the trench height is 50% to 90% of the electrode height, a buried gate electrode is formed, which extends out of the surface of the semiconductor substrate.

[0075] In some embodiments, a first gap 800 is provided between the first electrode 100 and at least one sidewall of the first trench 600, and the first gap 800 is filled with a first nano-light-trapping layer 110; a second gap 900 is provided between the second electrode 500 and at least one sidewall of the second trench 700, and the second gap 900 is filled with a second nano-light-trapping layer 120. The battery structure containing the nano-mask layer is as follows: Figure 4As shown, during the screen printing process, when printing electrodes, one, two, three, or four gaps are left in the trenches on the front and back sides of the semiconductor substrate 300, and the gaps are filled with a nano-light-trapping layer ( Figure 4 (A schematic diagram showing a nano-light-trapping layer in each trench) The nano-light-trapping layer can enhance the light absorption capacity of the battery.

[0076] The thickness of the first nano-light-trapping layer 110 and / or the second nano-light-trapping layer 120 is 50nm to 1000nm. Specifically, the thickness can be 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, etc. After the electrode meets the process requirements for solar energy fabrication, the thickness of the first nano-light-trapping layer 110 and the second nano-light-trapping layer 120 is set as large as possible to maximize the light absorption capacity of the battery.

[0077] The first nano-light-trapping layer 110 and / or the second nano-light-trapping layer 120 include any one of polystyrene, silicon dioxide, zinc oxide, gold, and silver. Polystyrene has the advantages of low cost, good repeatability, and controllable morphology. By simply changing the particle size of the micro-nano spheres, large-area periodic array structures of different sizes can be obtained, achieving efficient anti-reflection and light-trapping effects. Silicon dioxide has a simple preparation process, is easy to form into nanospheres, has good affinity with silicon substrates, and has a moderate refractive index. Although metals or their oxides are more expensive, they have excellent electrical properties. When a light-trapping layer is formed, it has certain light-trapping and anti-reflection effects without sacrificing electrical properties.

[0078] The first nano light-trapping layer 110 and / or the second nano light-trapping layer 120 are monolayer structures. The nano light-trapping layer can be a self-assembled layer composed of thin films, nanospheres or nano cubes arranged in an array with different particle sizes.

[0079] The width of the first gap 800 and / or the second gap 900 is 50nm to 1000nm. The width of the first gap and / or the second gap refers to the distance between the electrode sidewall and the inner wall of the nearest trench. Generally, the thickness of the first nano-light trapping layer 110 is adapted to the width of the first gap 800, and the thickness of the second nano-light trapping layer 120 is adapted to the width of the second gap 900.

[0080] Figure 5 This is a flowchart of a solar cell fabrication method provided in this embodiment, as shown below. Figure 5 As shown, Embodiment 1 of this application provides a method for preparing a solar cell, comprising the following steps:

[0081] S10, a semiconductor substrate 300 is provided, and a plurality of first trenches 600 arranged at intervals are formed on the front side of the semiconductor substrate 300, and a plurality of second trenches 700 arranged at intervals are formed on the back side of the semiconductor substrate 300.

[0082] S20, a texturing process is performed on the front and back sides of the semiconductor substrate 300 to form a surface texture structure, and a secondary texturing process is performed on the surface texture structure in the first trench 600 and the second trench 700, so that the surface texture structure in the first trench 600 is transformed into a first polarizing structure, and the surface texture structure in the second trench 700 is transformed into a second polarizing structure.

[0083] S30, deposit a first passivation layer 200 and a second passivation layer 400 on the front and back sides of the semiconductor substrate 300 after secondary texturing, respectively.

[0084] S40, a first electrode 100 is formed in the first trench 600 where the first passivation layer 200 is formed, and a second electrode 500 is formed in the second trench 700 where the second passivation layer 400 is formed, thereby obtaining a solar cell.

[0085] Understandably, the method for fabricating the solar cell of this application may form a first polarizing structure only on the front side of the semiconductor substrate, or a second polarizing structure separately on the back side of the semiconductor substrate, or polarizing structures simultaneously on both the front and back sides of the semiconductor substrate, depending on the specific requirements of the solar cell.

[0086] According to the light absorption requirements, step S40 may further include: after forming the first electrode 100 and the second electrode 500, forming a third polarizing structure on the sidewall of the first electrode 100 and / or forming a fourth polarizing structure on the sidewall of the second electrode 500. It is understood that setting a polarizing structure on the electrode sidewall can increase the number of light folds under sunlight, promoting light absorption. The polarizing structure can be set in the trench or on the electrode sidewall according to specific needs. Of course, polarizing structures can also be set simultaneously on the trench and on the electrode sidewall to further improve the light absorption capability of the battery.

[0087] Specifically, taking the fabrication of a solar cell as an example, which involves forming polarization structures in both the front and back trenches of a semiconductor substrate, as well as in both the front and back electrode sidewalls of the semiconductor substrate, the specific fabrication steps are as follows:

[0088] S10, a semiconductor substrate 300 is provided, and a plurality of first trenches 600 arranged at intervals are formed on the front side of the semiconductor substrate 300, and a plurality of second trenches 700 arranged at intervals are formed on the back side of the semiconductor substrate 300.

[0089] In some embodiments, the front side of the semiconductor substrate 300 is the surface facing the sun, and the back side is the surface facing away from the sun. It should also be noted that the semiconductor substrate 300 can be a crystalline silicon substrate (silicon substrate), such as a polycrystalline silicon substrate, a monocrystalline silicon substrate, or a monocrystalline silicon-like substrate. The specific type of semiconductor substrate is not limited in the embodiments of this application.

[0090] In some embodiments, the thickness of the semiconductor substrate 300 is 110um to 250um. Specifically, the thickness of the semiconductor substrate 300 can be 110um, 120um, 140um, 150um, 160um, 170um, 180um, 180um, 190um, 200um, 210um, 220um, 230um, 240um, 250um, etc. The embodiments of this application do not limit the thickness of the semiconductor substrate.

[0091] In some embodiments, the first trench 600 and the second trench 700 are formed by any one of plasma etching, mechanical etching or laser etching. The top view of the formed trench is rectangular, teardrop-shaped, trapezoidal or the like, as long as it can serve to accommodate the electrode. The embodiments of this application do not limit the specific method of trenching the semiconductor substrate.

[0092] S20, a texturing process is performed on the front and back sides of the semiconductor substrate 300 to form a surface texture structure, and a secondary texturing process is performed on the surface texture structure in the first trench 600 and the second trench 700, so that the surface texture structure in the first trench 600 is transformed into a first polarizing structure, and the surface texture structure in the second trench 700 is transformed into a second polarizing structure.

[0093] In some embodiments, the front and back sides of the semiconductor substrate 300 can be texturized once to form a positive pyramid structure. The texturization process can be photolithography, wet etching, ion etching, etc., and is not limited thereto. For example, NaOH solution can be used to texturize the front and back sides of the semiconductor substrate. Since the corrosion of NaOH solution is anisotropic, a positive pyramid structure textured surface can be prepared.

[0094] Optionally, prior to a texturing process, a step of cleaning the semiconductor substrate 300 may be included to remove metal and organic contaminants from the surface.

[0095] In some embodiments, a secondary texturing process is performed on the surface texture structure within the first trench 600 and the second trench 700. This secondary texturing process includes, but is not limited to, photolithography patterning, wet etching, and ion etching. Ion etching includes focused ion beam (FIB) direct etching and electron beam direct etching. The following uses FIB direct etching and electron beam direct etching as examples to prepare polarized structures:

[0096] FIB direct etching method:

[0097] The FIB system uses a liquid metal ion source to heat and generate a metal ion beam. The metal ions, precisely focused by an electron lens, form a scanning grating under the action of deflection coils. The ion beam can be used to etch patterns (such as cones, circles, cylinders, etc.) onto the sample via sputtering. The etching process can also be accomplished by replacing the ion beam with an electron beam.

[0098] Electron beam direct etching:

[0099] A mask layer of a preset shape (such as an arc-shaped pit, sphere, cone, inverted pyramid, column, or pen shape) is coated on the sample surface. When bombarded by an ion beam, the areas not protected by the mask layer are etched, while the areas with the mask layer remain unchanged. This method achieves pattern etching.

[0100] Conventional surface texture structures are "positive pyramid structures". This application transforms the "positive pyramid structure" into arc-shaped pits, spheres, cones, inverted pyramids, columns, or pen-shaped structures through a secondary texturing process. These structures have a small aspect ratio, which can reduce surface recombination of the battery, increase the number of light refractions, make the light path longer, enhance the light trapping effect, and thus improve the photoelectric conversion efficiency of the battery.

[0101] In some embodiments, the height of at least one of the first, second, third, and fourth polarizing structures is 50 nm to 1800 nm, and the specific height can be 50 nm, 100 nm, 500 nm, 700 nm, 1000 nm, 1500 nm, 1800 nm, etc. The width of at least one of the first, second, third, and fourth polarizing structures is 40 nm to 1500 nm, and the specific width can be 40 nm, 100 nm, 500 nm, 1000 nm, 1200 nm, 1500 nm, etc. Specifically, the width of the polarizing structures in this application refers to the maximum width. For example, for a cone-shaped polarizing structure, its width refers to the width of the bottom of the cone, and for a pen-shaped polarizing structure, its width refers to the width of the end of the pen. The height-to-width ratio of the first polarizing structure and / or the second polarizing structure is (0.3-2.0):1. Specifically, for a columnar polarizing structure, the height-to-width ratio is (1.5-2.0):1; for a pencil-shaped polarizing structure, the height-to-width ratio is (0.5-1.8):1; for a spherical polarizing structure, the height-to-width ratio is (0.8-1.20):1; and for a conical polarizing structure, the height-to-width ratio is (0.3-1.5):1. For a concave polarizing structure with an arc-shaped surface, its height is represented by its depth, with a depth-to-width ratio of (0.4–0.6):1. For an inverted pyramid-shaped polarizing structure, its height is represented by its depth, with a depth-to-width ratio of (0.5–0.8):1. When the aspect ratio of the polarizing structure is too small, the light absorption capacity cannot meet the requirements. When the aspect ratio is too large, the specific surface area of ​​the light-trapping structure under the polarizing structure increases rapidly, leading to an increase in the number of surface recombination sites. The conventional "positive pyramid" structure typically has a height of 1–5 μm, which is relatively large in size and surface area, resulting in significant metal recombination between the electrode and the semiconductor substrate, which is not conducive to improving the photoelectric conversion efficiency of the battery. The polarizing structure designed in this application has a height at the micro-nano level, or even at the nanometer level. During sunlight irradiation, the polarizing structure has more light folding and reflection times compared to the "positive pyramid" structure, allowing the battery to utilize more light, thereby increasing the number of light-trapping round trips and enhancing the light-trapping effect.

[0102] In some embodiments, the width of the first trench 600 and / or the second trench 700 is 20µm to 50µm. Specifically, the width of the first trench 600 and / or the second trench 700 can be 20µm, 30µm, 40µm, 50µm, etc. The function of the trench is to accommodate the electrode. The width of the trench should be greater than or equal to the width of the electrode. If the trench width is too large, the size of the semiconductor substrate 300 will increase, which will restrict the development of the battery. If the trench width is too small, it cannot accommodate the electrode and will not play a role in improving the light flux. The height of the first trench 600 is 5% to 90% of the height of the first electrode 100, and the height of the second trench 700 is 5% to 90% of the height of the second electrode 500. Specifically, the height of the trench 200 can be 20µm to 50µm of the height of the first electrode 600. The height of the first trench 600 can be 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, etc., which are the heights of the first and second electrodes 500. Generally, the heights of the first trench 600 and / or the second trench 700 are 50nm to 1μm. The higher the heights of the first trench 600 and the second trench 700 are within the selectable range, the less light will be blocked by the electrodes. Since the battery assembly will be soldered later, the upper limit of the height of the first trench 600 is set to 90% of the height of the first electrode 100, and the upper limit of the height of the second trench 700 is set to 90% of the height of the second electrode 500.

[0103] S30, a first passivation layer 200 and a second passivation layer 400 are deposited on the front and back sides of the semiconductor substrate 300 after secondary texturing, respectively.

[0104] In some embodiments, the first passivation layer 200 includes any one or more combinations of a silicon nitride layer, a silicon oxynitride layer, and an aluminum oxide / silicon nitride stack. Of course, the first passivation layer 200 can also be other types of passivation layers. This application does not limit the specific material of the first passivation layer 200. For example, in other embodiments, the first passivation layer 200 can also be a stack of silicon dioxide and silicon nitride. The aforementioned front passivation layer can produce a good passivation effect on the silicon substrate, which helps to improve the conversion efficiency of the battery.

[0105] In some embodiments, the first passivation layer 200 can be deposited using plasma-enhanced chemical vapor deposition (PECVD). Other methods, such as organic chemical vapor deposition (OCVD), can also be used. This application does not limit the specific implementation of the first passivation layer 200.

[0106] In some embodiments, the second passivation layer 400 includes any one or more combinations of a silicon nitride layer, a silicon oxynitride layer, and an aluminum oxide / silicon nitride stacked structure. Of course, the second passivation layer 400 can also employ other types of passivation layers. This application does not limit the specific material of the second passivation layer 400; for example, in other embodiments, the second passivation layer 400 can also be a stack of silicon dioxide and silicon nitride. The aforementioned back-side passivation layer can produce a good passivation effect on the silicon substrate, which helps to improve the conversion efficiency of the battery.

[0107] In some embodiments, the second passivation layer 400 can be deposited using plasma-enhanced chemical vapor deposition (PECVD). Other methods, such as organic chemical vapor deposition (OCVD), can also be used. This application does not limit the specific implementation of the second passivation layer 400.

[0108] S40, a first electrode 100 is formed in the first trench 600 where the first passivation layer 200 is formed, a third polarizing structure is formed on the sidewall of the first electrode 100, a second electrode 500 is formed in the second trench 700 where the second passivation layer 400 is formed, and a fourth polarizing structure is formed on the sidewall of the second electrode 500, thereby obtaining a solar cell.

[0109] In some embodiments, a first electrode 100 on the front side and a second electrode 500 on the back side are formed by screen printing and sintering. For example, conductive paste can be printed in the first trench 600 and the second trench 700 of the semiconductor substrate 300 by screen printing technology, and then dried and sintered to form the first electrode 100 and the second electrode 500. After sintering, the first electrode 100 can penetrate the passivation layer and be electrically connected to the semiconductor substrate 300.

[0110] In some embodiments, the screen printing plate needs to be aligned with the positions of the first groove 600 and the second groove 700.

[0111] It should be noted that the specific materials of the first electrode 100 and the second electrode 500 are not limited in the embodiments of this application. The first electrode and the second electrode can be formed using the same or different materials. Specifically, the first electrode 100 can be a silver electrode, and the second electrode 500 can be an aluminum electrode, or both the first electrode 100 and the second electrode 500 can be silver electrodes.

[0112] In some embodiments, the method for fabricating a polarizing structure on the electrode sidewall includes a template sacrifice method or a photolithography method. The following example uses the template sacrifice method to fabricate a third polarizing structure on the sidewall of the first electrode:

[0113] After forming the first polarizing structure in step S20, a reverse template for forming the desired metallic polarizing structure is generated on the inner wall of the trench (i.e., the first polarizing structure) through methods such as ion spraying or chemical growth. The template is typically made of easily decomposable materials such as polymers (e.g., polyethyleneimine) or organometallic frameworks (e.g., ZIF-67, MOF-74). The electrode is then placed into the trench via screen printing, and a polarizing structure is formed with the assistance of a template agent (e.g., hexadecyltrimethylammonium bromide). The template agent is removed by heat treatment to obtain the third polarizing structure. It is understood that the polarizing structure formed on the electrode sidewall may or may not be the same as the polarizing structure at the trench, as long as its morphology, height, width, and aspect ratio meet the conditions defined in this application.

[0114] Figure 6 Another flowchart of the method for fabricating a solar cell provided in the embodiments of this application is shown below. Figure 6 As shown in the embodiment of this application, another method for preparing a solar cell includes the following steps:

[0115] S10, a semiconductor substrate 300 is provided, and a plurality of first trenches 600 arranged at intervals are formed on the front side of the semiconductor substrate 300, and a plurality of second trenches 700 arranged at intervals are formed on the back side of the semiconductor substrate 300.

[0116] S20, a texturing process is performed on the front and back sides of the semiconductor substrate to form a surface texture structure, and a secondary texturing process is performed on the surface texture structure in the first trench 600 and the second trench 700, so that the surface texture structure in the first trench 600 is transformed into a first polarizing structure, and the surface texture structure in the second trench 700 is transformed into a second polarizing structure.

[0117] S30, deposit a first passivation layer 200 and a second passivation layer 400 on the front and back sides of the semiconductor substrate 300 after secondary texturing, respectively.

[0118] S40, a first electrode 100 is formed in the first trench 600 where the first passivation layer 200 is formed, a third polarizing structure is provided on at least one sidewall of the first electrode 100, a fourth polarizing structure is formed on at least one sidewall of the second electrode 500, a first gap 800 is formed between the first electrode 100 and at least one sidewall of the first trench 600, a first nano-light-trapping layer 110 is formed in the first gap 800, a second electrode 500 is formed in the second trench 700 where the second passivation layer 400 is formed, a second gap 900 is provided between the second electrode 500 and at least one sidewall of the second trench 700, a second nano-light-trapping layer 120 is formed in the second gap 900, and a solar cell is obtained.

[0119] Unlike Embodiment 1, step S40 further includes: during the screen printing process, a first gap 800 is formed between the first electrode 100 and at least one sidewall of the first trench 600, and a second gap 900 is provided between the second electrode 500 and at least one sidewall of the second trench 700. The first gap 800 is filled with a nano light-trapping layer 110, and the second gap 900 is filled with a second nano light-trapping layer 120. The nano mask layer is filled into the gaps by any one of the following methods: micro-push injection, lifting, evaporation, and spin coating. The nano light-trapping suspension includes a suspension containing at least one of polystyrene, silica, zinc oxide, gold, and silver.

[0120] Understandably, when polarizing structures are formed both inside the trench and on the sidewalls of the electrode, the nano-light-trapping layer is located between the polarizing structure formed by the electrode and the polarizing structure formed inside the trench.

[0121] Taking polystyrene as an example, the first nano-light-trapping layer 110 and the second nano-light-trapping layer 120 are prepared using the micro-injection molding method. The specific steps include:

[0122] Step 1: Preparation of spherical suspension:

[0123] Styrene monomer was pre-cleaned by washing it four times with 200 mL of 5 wt% sodium hydroxide solution, followed by washing with deionized water until the monomer solution was neutral. An appropriate amount of anhydrous CaCl2 was added, and the mixture was allowed to stand for about half an hour to allow the water to be fully absorbed. For polystyrene microspheres larger than 1 μm, dispersion polymerization was used. Appropriate amounts of polyvinylpyrrolidone (PVP), ethanol, deionized water, and the cleaned monomer were poured into a three-necked flask equipped with a magnetic stirrer. Nitrogen gas was introduced, and the flask was placed in an oil bath with a stirring speed of 500 rpm and a temperature of 70 °C. When the temperature stabilized at 70 °C, the nitrogen gas inlet tube was removed, and a weighed azobisisobutyronitrile (AIBN) was added. The inlet tube was promptly reinserted, and stirring and nitrogen gas were maintained. The reaction was allowed to proceed for 16 hours, then cooled to terminate the reaction, yielding the emulsion product. Polystyrene microspheres smaller than 1 μm were prepared by emulsion polymerization. The obtained PS microsphere emulsion can be centrifuged and washed multiple times to obtain a polystyrene microsphere suspension with uniform particle size.

[0124] Step 2: Preparation of the nano-light-trapping layer

[0125] Step 2.1: Place the substrate material in the carrier beforehand and connect the syringe to the micro-pump syringe system.

[0126] Step 2.2: Adjust the contact state between the syringe and the gap between the electrode and the groove so that the syringe needle tip and the bottom of the gap are just in contact, and then start the micro-push syringe system to inject polystyrene colloid.

[0127] Step 2.3: Close the micro-pump injector system until the filling is complete, thus forming a dense polystyrene monolayer film. This monolayer film is a light-trapping layer composed of an array of films, nanospheres, or nanocubes of varying particle sizes, such as... Figure 7 As shown, the nano-light trapping layer is an array of nanosphere-shaped monolayer films. The nano-light trapping layer exists on one side of the first electrode 100. During sunlight irradiation, it can enhance light absorption, thereby improving the photoelectric conversion efficiency of the battery.

[0128] This application creates trenches on the front and / or back sides of a battery semiconductor substrate, places electrodes within the trenches to reduce light shading, and simultaneously creates a polarizing structure and / or a nano-light-trapping layer within the trenches to enhance light absorption, thereby improving the photoelectric conversion efficiency of the battery.

[0129] like Figure 8 The diagram shows a conventional heterojunction solar cell structure, including a semiconductor substrate 300. On the front side of the semiconductor substrate 300, from bottom to top, are sequentially arranged a first amorphous silicon film layer 130, a P-type amorphous silicon doped layer 140, a first TCO conductive layer 150, and a first electrode 100. On the back side of the semiconductor substrate 300, from top to bottom, are sequentially arranged a second amorphous silicon layer 160, an N-type amorphous silicon doped layer 170, a second TCO conductive layer 180, and a second electrode 500. The first electrode 100 and the second electrode 500 are conventionally obtained by screen printing twice. While using a two-stage printing method can achieve a larger aspect ratio for the electrodes, thereby improving their conductivity, the high aspect ratio leads to significant light shading during illumination, reducing the luminous flux entering the cell. This is one of the reasons for the low short-circuit current of existing heterojunction cells. Furthermore, increasing the electrode aspect ratio reduces the contact area between the electrode and the TCO conductive film, resulting in a significant decrease in the collection of charge carriers. All of these factors contribute to the low light conversion efficiency of the fabricated solar cells, hindering the development of heterojunction cells.

[0130] The solar cell of this application can be a heterojunction cell, and the first passivation layer includes an amorphous silicon passivation layer, which may include, but is not limited to, an intrinsic amorphous silicon layer, a doped amorphous silicon layer, etc.

[0131] In some embodiments, the intrinsic amorphous silicon layer may be located on the substrate surface of the semiconductor substrate, the doped amorphous silicon layer may be located on the surface of the intrinsic amorphous silicon layer, and the TCO conductive layer may be located on the surface of the doped amorphous silicon layer.

[0132] Specifically, such as Figure 9The diagram shown is a structural schematic of a heterojunction solar cell provided in an embodiment of this application. The heterojunction solar cell includes, from top to bottom, a first electrode 100, a first TCO conductive layer 150, a P-type amorphous silicon doped layer 140, a first amorphous silicon film layer 130, a semiconductor substrate 300, a second amorphous silicon film layer 160, an N-type amorphous silicon doped layer 170, a second TCO conductive layer 180, and a second electrode 500.

[0133] The semiconductor substrate 300 has a plurality of spaced first trenches 600 on its front side, the first electrode 100 is disposed in the first trenches 600, and the surface of the semiconductor substrate 300 located in the first trenches 600 that contacts the first amorphous silicon film layer has a first polarization structure.

[0134] The semiconductor substrate 300 has a plurality of second trenches 700 arranged at intervals on its back side. The second electrode 500 is disposed in the second trenches 700. The surface of the semiconductor substrate 300 located in the second trenches 700 that contacts the second amorphous silicon film layer is provided with a second polarization structure.

[0135] A first gap 800 is provided between the first electrode 100 and at least one sidewall of the first trench 600, and a second gap 900 is provided between the second electrode 500 and at least one sidewall of the second trench 700. The first gap 800 and the second gap 900 are filled with a nanomask layer 110.

[0136] This application discloses a method for fabricating a heterojunction solar cell, which specifically includes the following steps:

[0137] S10, a semiconductor substrate 300 is provided, and a plurality of first trenches 600 arranged at intervals are formed on the front side of the semiconductor substrate 300, and a plurality of second trenches 700 arranged at intervals are formed on the back side of the semiconductor substrate 300.

[0138] S20, the front and back sides of the semiconductor substrate 300 are textured once to form a surface texture structure, and the surface texture structure in the first trench 600 and the second trench 700 is textured a second time, so that the surface texture structure in the first trench 600 is transformed into a first polarization structure and the surface texture structure in the second trench 700 is transformed into a second polarization structure.

[0139] S30, a first amorphous silicon film layer 130 is deposited on the front side of the semiconductor substrate 300 after secondary texturing, and a P-type amorphous silicon doped layer 140 is deposited on the first amorphous silicon film layer 130. A first TCO conductive layer 150 is then deposited on the P-type amorphous silicon doped layer 140 to obtain a first passivation layer 200.

[0140] In some embodiments, the first amorphous silicon film 130 can be deposited by any one of plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced chemical vapor deposition (PECVD), and reactive ion deposition (RID). Preferably, plasma-enhanced chemical vapor deposition (PECVD) is used.

[0141] The thickness of the first amorphous silicon film layer 130 is 3nm to 10nm, for example, it can be 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, etc.

[0142] A p-type amorphous silicon doped layer 140 can be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Correspondingly, the equipment used for deposition can be physical vapor deposition (PVD) equipment, atomic layer deposition (ALD) equipment, plasma chemical vapor deposition (PECVD) equipment, low-pressure chemical vapor deposition (LPCVD) equipment, etc.

[0143] Step S30 includes at least the following two implementation methods:

[0144] One-step deposition method: A first amorphous silicon layer 130 is formed on the front side of the semiconductor substrate 300 and doping is performed simultaneously to form the P-type amorphous silicon doped layer 140;

[0145] Two-step deposition method: A first amorphous silicon layer 130 is deposited on the front side of the semiconductor substrate 300, and then the first amorphous silicon layer 130 is doped to form a P-type amorphous silicon doped layer 140.

[0146] The doping process can employ one or more methods, including high-temperature diffusion, slurry doping, or ion implantation. The dopant element in the P-type amorphous silicon doped layer 140 can be a Group 3 element such as boron, gallium, or indium. Specifically, the semiconductor substrate is placed in a tube diffusion furnace, using a liquid boron tribromide source as the diffusion source (or doping source), and the temperature of the isothermal zone is maintained at approximately 850°C. Boron diffusion is performed on the semiconductor substrate for a certain diffusion time (e.g., 40 minutes), resulting in a doped junction depth of 0.2 μm to 1.0 μm, thus forming the doped layer. The dopant element in the N-type amorphous silicon doped layer 170 can be a Group 5 element such as phosphorus or arsenic. The thickness of the N-type amorphous silicon doped layer 170 is 5 nm to 10 nm, specifically 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc., and the thickness can be set according to actual requirements.

[0147] Specifically, the thickness of the P-type amorphous silicon doped layer 140 is 20nm to 300nm, for example, it can be 20nm, 50nm, 80nm, 100nm, 160nm, 180nm, 200nm, 250nm, 300nm, etc.

[0148] The first amorphous silicon film layer 130 and the P-type amorphous silicon doped layer 140 serve to passivate the semiconductor substrate 300, thereby obtaining a higher open-circuit voltage and reducing the recombination rate on the electrode surface.

[0149] The first TCO conductive layer 150 is a transparent conductive thin film material, which can be formed by reactive plasma deposition (RPD) or physical vapor deposition (PVD).

[0150] The thickness of the first TCO conductive layer 150 is 70nm to 110nm, for example, it can be 70nm, 80nm, 90nm, 100nm, 110nm, etc. The transmittance is above 98%, and the sheet resistance is 50Ω to 100Ω, for example, it can be 50Ω, 60Ω, 70Ω, 80Ω, 90Ω, 100Ω, etc.

[0151] The first TCO conductive layer 150 can be an oxide, nitride, doped oxide, or mixed oxide, etc. Specifically, the oxide can be In2O3, SnO2, ZnO, or CdO, the nitride can be TiN, and the doped oxide can be In2O3. 3: Sn, ZnO:In, ZnO:Ga, ZnO:Al, SnO2:F, SnO2:Ta, and mixed oxides can be In2O 3- ZnO, Cd In2O4, Cd2SnO4, Zn2SnO4.

[0152] S40, a second amorphous silicon film layer 160 is deposited on the back side of the semiconductor substrate 300 after secondary texturing, and an N-type amorphous silicon doped layer 170 is deposited on the second amorphous silicon film layer 160. A second TCO conductive layer 180 is then deposited on the N-type amorphous silicon doped layer 170 to obtain a second passivation layer 500.

[0153] Heterojunction solar cells are symmetrical in structure, which facilitates the reduction of process equipment. That is, the preparation process, thickness and function of the second amorphous silicon film layer 160 are the same as those of the first amorphous silicon film layer 130. The preparation method, material and thickness of the first TCO conductive layer 150 and the second TCO conductive layer 180 are also the same, which will not be described in detail here.

[0154] S50, a first electrode 100 is formed in the first trench 600 where a first TCO conductive layer is formed, a second electrode 500 is formed on the surface where a second TCO conductive layer is formed, a third polarizing structure is provided on at least one sidewall of the first electrode 100, a fourth polarizing structure is formed on at least one sidewall of the fourth electrode, a first gap 800 is formed between the first electrode 100 and at least one sidewall of the first trench 600, a first nano-light-trapping layer 110 is formed in the first gap 800, a second electrode 500 is formed in the second trench 700 where a second passivation layer 400 is formed, a second gap 900 is provided between the second electrode 500 and at least one sidewall of the second trench 700, a second nano-light-trapping layer 120 is formed in the second gap 900, and a solar cell is obtained.

[0155] For heterojunction solar cells, this application creates trenches on the semiconductor substrate before texturing. The trenches increase the contact area between the electrode and the TCO conductive layer. The TCO conductive layer has high mobility and light transmittance. Increasing the contact area between the electrode and the TCO conductive layer can promote the transport and collection of charge carriers, thereby improving the photoelectric conversion efficiency of the solar cell.

[0156] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0157] Although this application discloses preferred embodiments as described above, it is not intended to limit the claims. Any person skilled in the art can make several possible changes and modifications without departing from the concept of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A solar cell, characterized in that, The solar cell includes a first electrode, a first passivation layer, a semiconductor substrate, a second passivation layer, and a second electrode arranged sequentially from top to bottom. The semiconductor substrate has a plurality of spaced first trenches on its front side. The first electrode is disposed in the first trench. The surface of the semiconductor substrate in the first trench that contacts the first passivation layer is provided with a first polarization structure and / or at least one sidewall of the first electrode is provided with a third polarization structure. A first gap is provided between the first electrode and at least one sidewall of the first trench, and the first gap is filled with a first nano-light trapping layer.

2. The solar cell according to claim 1, characterized in that, The back side of the semiconductor substrate has a plurality of spaced second trenches, the second electrode is disposed in the second trench, the surface of the semiconductor substrate in contact with the second passivation layer in the second trench is provided with a second polarization structure and / or at least one sidewall of the second electrode is provided with a fourth polarization structure; a second gap is provided between the second electrode and at least one sidewall of the second trench, and the second gap is filled with a second nano-light trapping layer.

3. The solar cell according to claim 2, characterized in that, The morphology of at least one of the first polarizing structure, the second polarizing structure, the third polarizing structure, and the fourth polarizing structure includes any one of the following: arc-shaped pit, spherical, conical, columnar, and pen-shaped.

4. The solar cell according to claim 3, characterized in that, The height of at least one of the first, second, third, and fourth polarizing structures is 50 nm to 1800 nm, and the width of at least one of the first, second, third, and fourth polarizing structures is 40 nm to 1500 nm. The height-to-width ratio of the first polarizing structure is (0.3 to 2.0):1, the height-to-width ratio of the second polarizing structure is (0.3 to 2.0):1, the height-to-width ratio of the third polarizing structure is (0.3 to 2.0):1, and the height-to-width ratio of the fourth polarizing structure is (0.3 to 2.0):

1.

5. The solar cell according to claim 2, characterized in that, The width of the first trench and / or the second trench is 20um to 50um, and the height of the first trench is 5% to 90% of the height of the first electrode and / or the height of the second trench is 5% to 90% of the height of the second electrode.

6. The solar cell according to claim 2, characterized in that, The solar cell includes at least one of the following technical features a to c: a. The thickness of the first nano-light-trapping layer and / or the second nano-light-trapping layer is 50 nm to 1000 nm; b. The first nano-light-trapping layer and / or the second nano-light-trapping layer comprises any one of polystyrene, silicon dioxide, zinc oxide, gold, and silver; c. The first nano-light-trapping layer and / or the second nano-light-trapping layer are monolayer structures.

7. The solar cell according to claim 2, characterized in that, The width of the first gap and / or the second gap is 50nm~1000nm.

8. The solar cell according to claim 1, characterized in that, The first passivation layer includes an amorphous silicon passivation layer.

9. A method for preparing a solar cell, characterized in that, Includes the following steps: A semiconductor substrate is provided, and a plurality of first trenches arranged at intervals are formed on the front side of the semiconductor substrate; The front side of the semiconductor substrate is texturized once to form a surface texture structure, and the surface texture structure in the first trench is texturized a second time to transform the surface texture structure in the first trench into a first polarizing structure. A first passivation layer is deposited on the front side of the semiconductor substrate after secondary texturing, and a first electrode is formed in the first trench where the first passivation layer is formed; A first gap is formed between the first electrode and at least one sidewall of the first trench. A nano-light-trapping suspension is filled into the first gap using any one of the following methods: micro-push injection, lifting, evaporation, and spin coating, so that a first nano-light-trapping layer is formed in the first gap, thereby obtaining a solar cell.

10. The preparation method according to claim 9, characterized in that, The method further includes: A plurality of spaced second trenches are formed on the back side of the semiconductor substrate; The back side of the semiconductor substrate is texturized once to form a surface texture structure, and the surface texture structure in the second trench is texturized a second time to transform the surface texture structure in the second trench into a second polarization structure. A second passivation layer is deposited on the back side of the semiconductor substrate after secondary texturing, and a second electrode is formed in the second trench where the second passivation layer is formed; A second void is formed between the second electrode and at least one sidewall of the second trench. The nano-light-trapping suspension is filled into the second void using any one of the following methods: micro-push injection, lifting, evaporation, and spin coating, so that a second nano-light-trapping layer is formed in the second void.

11. The preparation method according to claim 10, characterized in that, The method further includes: A third polarizing structure is formed on at least one sidewall of the first electrode and / or a fourth polarizing structure is deposited on at least one sidewall of the second electrode.

12. The preparation method according to claim 11, characterized in that, The morphology of at least one of the first polarizing structure, the second polarizing structure, the third polarizing structure, and the fourth polarizing structure includes any one of the following: arc-shaped pit, spherical, conical, columnar, and pen-shaped.

13. The preparation method according to claim 11, characterized in that, The height of at least one of the first, second, third, and fourth polarizing structures is 50 nm to 1800 nm, and the width of at least one of the first, second, third, and fourth polarizing structures is 40 nm to 1500 nm. The height-to-width ratio of the first polarizing structure is (0.3 to 2.0):1, the height-to-width ratio of the second polarizing structure is (0.3 to 2.0):1, the height-to-width ratio of the third polarizing structure is (0.3 to 2.0):1, and the height-to-width ratio of the fourth polarizing structure is (0.3 to 2.0):

1.

14. The preparation method according to claim 9 or 10, characterized in that, The nano-light-trapping suspension includes a suspension containing at least one of polystyrene, silica, zinc oxide, gold, and silver.

15. A photovoltaic module, characterized in that, The photovoltaic module includes a plurality of solar cell strings, each of the solar cell strings including a solar cell according to any one of claims 1 to 8 or a solar cell prepared by any one of claims 9 to 14.

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