Display panel

Abstract

There is provided a display panel including: a base layer including a display area including a transmissive area and a non-display area adjacent to the display area; a first insulating layer; a transistor on the first insulating layer; a third insulating layer covering the transistor; a first connection electrode connected to the semiconductor pattern through a contact hole defined in the third insulating layer; a fourth insulating layer covering the first connection electrode; a pixel defining layer including a display opening that does not overlap the transmissive region; and a light emitting element, in which the fourth insulating layer includes a first insulating opening overlapping the transmissive region, and the pixel defining layer includes a transmissive opening overlapping the first insulating opening.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0118431 filed in the Korean Intellectual Property Office on September 6, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Aspects of some embodiments of the present disclosure relate to a transparent display panel. Background Art

[0003] The display panel includes a plurality of pixels and a driving circuit (eg, a scan driving circuit and a data driving circuit) for controlling the plurality of pixels. Each of the plurality of pixels includes a display element and a pixel driving circuit for controlling the display element. The pixel driving circuit may include a plurality of organically connected transistors.

[0004] In recent years, with the development of technology, a transparent display panel has been developed, in which a transmissive area within a display area is transparent. Therefore, the display panel needs to be designed to increase the transmittance of the transparent area within the display area.

[0005] The above information disclosed in this background section is only for enhancement of understanding of the background technology and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the invention

[0006] Aspects of some embodiments of the present disclosure relate to a transparent display panel, and to a display panel including a circuit element layer having relatively improved transparency of a display area.

[0007] Aspects of some embodiments of the present disclosure include a transparent display panel for increasing the transparency of a transmissive region within a display region.

[0008] According to some embodiments, a display panel includes: a base layer, including a display area including a transmission area and a non-display area adjacent to the display area; a light shielding pattern on the base layer; a first insulating layer covering the light shielding pattern; a transistor overlapping the light shielding pattern and including a semiconductor pattern on the first insulating layer and a gate on the semiconductor pattern; a second insulating layer between the semiconductor pattern and the gate; a third insulating layer covering the transistor; a first connecting electrode on the third insulating layer and connected to the semiconductor pattern through a contact hole defined in the third insulating layer; a fourth insulating layer covering the first connecting electrode; a pixel defining layer including a display opening that does not overlap with the transmission area and is on the fourth insulating layer; and a light emitting element on the fourth insulating layer and including a first electrode, a second electrode and a light emitting layer, the first electrode being exposed through the display opening and connected to the first connecting electrode, and the light emitting layer being between the first electrode and the second electrode, wherein the fourth insulating layer includes a first insulating opening overlapping with the transmission area, and the pixel defining layer includes a transmission opening overlapping with the first insulating opening.

[0009] According to some embodiments, in a plane, a width of the first insulating opening may be greater than a width of the transmissive opening.

[0010] According to some embodiments, a side surface of the fourth insulating layer defining the first insulating opening may be in contact with the pixel defining layer.

[0011] According to some embodiments, the fourth insulating layer may include silicon nitride, and the pixel defining layer may include photosensitive polyimide (PSPI).

[0012] According to some embodiments, in the transmissive region, the third insulating layer may be exposed from the pixel defining layer through the transmissive opening.

[0013] According to some embodiments, the third insulation layer may include a second insulation opening overlapping the first insulation opening, and a side surface of the fourth insulation layer defining the first insulation opening and a side surface of the third insulation layer defining the second insulation opening may contact the pixel defining layer.

[0014] According to some embodiments, in the transmissive region, the first insulating layer may be exposed from the pixel defining layer through the transmissive opening.

[0015] According to some embodiments, the first insulation layer may include a third insulation opening overlapping the second insulation opening, and a side surface of the first insulation layer defining the third insulation opening may contact the pixel defining layer.

[0016] According to some embodiments, in the transmissive region, the base layer may be exposed from the pixel defining layer through the transmissive opening.

[0017] According to some embodiments, the display panel may further include a data line connected to the transistor, wherein the data line may be at the same layer as the light shielding pattern.

[0018] According to some embodiments, the area of ​​the display opening may be smaller than the area of ​​the transmissive opening.

[0019] According to some embodiments, the display panel may further include a fifth insulating layer between the fourth insulating layer and the pixel defining layer, wherein the fifth insulating layer may include an upper insulating opening overlapping the first insulating opening, and a side surface of the fifth insulating layer defining the upper insulating opening may contact the pixel defining layer.

[0020] According to some embodiments, an upper surface of the fourth insulation layer adjacent to a side surface of the fourth insulation layer defining the first insulation opening may be exposed from the fifth insulation layer through the upper insulation opening, and the upper surface may contact the pixel defining layer.

[0021] According to some embodiments, the fifth insulating layer may include photosensitive polyimide (PSPI).

[0022] According to some embodiments, the display panel may further include a second connection electrode on the fourth insulating layer, covered by the fifth insulating layer, and connected to the first connection electrode through a contact hole defined in the fourth insulating layer.

[0023] According to some embodiments, the first insulating layer may include a first layer including silicon nitride and a second layer including silicon oxide, the second insulating layer may include silicon oxide, and the third insulating layer may include silicon oxynitride.

[0024] According to some embodiments, each of the light shielding pattern and the gate may include a first layer including titanium and a second layer including copper, the semiconductor pattern may include indium gallium zinc oxide (IGZO), and the first connecting electrode may include a first layer including titanium, a second layer including copper, and a third layer including indium tin oxide (ITO).

[0025] According to some embodiments, the first electrode may include a first layer including indium tin oxide (ITO), a second layer including silver, and a third layer including ITO.

[0026] According to some embodiments, the display panel may further include an encapsulation layer covering the light emitting element and including inorganic layers and organic layers between the inorganic layers.

[0027] According to some embodiments, an object on the rear side of the display panel may be visible from the front surface of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0029] Figure 1A is a perspective view of a display panel according to some embodiments of the present disclosure.

[0030] Figure 1B is a perspective view of a curved display panel according to some embodiments of the present disclosure.

[0031] Figure 2 is a cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0032] Figure 3A is a plan view of a display panel according to some embodiments of the present disclosure.

[0033] Figure 3B is an enlarged plan view of a display area of ​​a display panel according to some embodiments of the present disclosure.

[0034] Figure 4 is an equivalent circuit diagram of a pixel according to some embodiments of the present disclosure.

[0035] Figure 5 It is along Figure 3B A cross-sectional view taken along line II'.

[0036] Fig. 6A It is along Figure 3B A cross-sectional view taken along line II-II'.

[0037] Figure 6B is a cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0038] Figure 6C is a cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0039] 7A to 7H It shows that the layout is distinguished according to each layer. Figure 3B A plan view of the stacking order of the conductive patterns in the region QQ'.

[0040] FIG. 8A to FIG. 8C is a cross-sectional view according to a comparative example. DETAILED DESCRIPTION

[0041] In this specification, the expression that a first component (or region, layer, part, portion, etc.) is "on" a second component, "connected to" a second component, or "coupled to" a second component means that the first component is directly on the second component, directly connected to the second component, or directly coupled to the second component, or means that a third component is placed between the first component and the second component.

[0042] The same reference numerals denote the same components. In addition, in the drawings, in order to effectively describe the technical content, the thickness, proportion and size of the components are exaggerated. The expression "and / or" includes one or more combinations that the relevant components can define.

[0043] Although the terms "first", "second", etc. can be used to describe various components, the components should not be limited by the terms. The terms are only used to distinguish one component from another component. For example, without departing from the correct scope of the present disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0044] Furthermore, the terms “below,” “beneath,” “on,” “over,” etc. are used to describe the relationship between components shown in the drawings. Conceptually relative terms are described based on directions shown in the drawings.

[0045] It will be understood that the terms "comprises", "includes", "having", etc. indicate the presence of the features, quantities, steps, operations, elements or components, or combinations thereof, described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements or components, or combinations thereof.

[0046] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an overly idealized or overly formal sense unless explicitly defined herein.

[0047] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0048] Figure 1A is a perspective view of a display panel according to some embodiments of the present disclosure. Figure 1B is a perspective view of a curved display panel according to some embodiments of the present disclosure. Figure 2 is a cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0049] Figure 1A and Figure 1B The electronic devices ED and ED-1 shown in FIG. 4 may each include a display panel DP and a housing HU accommodating at least a portion of the display panel DP. For example, a portion of a lower end of the display panel DP may be accommodated in the housing HU.

[0050] The display panel DP as a light-emitting display panel can be one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system (MEMS) display panel, an electrowetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel and a quantum dot display panel, and is not particularly limited thereto according to the embodiments of the present disclosure.

[0051] Reference Figure 1A , the display panel DP may display an image through the front surface DU. The upper surface of the member positioned at the uppermost side of the display panel DP may be defined as the front surface DU of the display panel DP. According to the present disclosure, Figure 2 An upper surface of the window panel WD shown in may be defined as a front surface DU of the display panel DP.

[0052] According to some embodiments, the front surface DU is parallel to a plane defined by the first direction DR1 and the second direction DR2. A normal direction of the front surface DU (i.e., a thickness direction of the display panel DP) represents a third direction DR3. Hereinafter, a front surface (or upper surface) and a rear surface (or lower surface) of a layer or unit to be described in more detail below are distinguished by the third direction DR3.

[0053] The display panel DP according to some embodiments may be a transparent display panel DP. The transparent display panel DP may display information in a state in which an object PD positioned at the rear side of the display panel DP (e.g., an object PD facing the rear surface DB of the display panel DP) is transparently transmitted on the front surface DU of the display panel DP. Therefore, the user can recognize the object PD positioned at the rear side of the display panel DP through the front surface DU of the display panel DP. The information is an image, content, a playback screen, an application execution screen, a web browser screen, and various graphic objects, but is not limited to any of them. Figure 1A A vase is shown as an example of the object PD, but according to an embodiment of the present disclosure, it is not limited thereto, and the object PD is not limited to any one as long as the object PD has a definite shape.

[0054] The housing HU can protect the display panel DP from external impact or intrusion of foreign objects. The housing HU can be made of a material such as plastic or metal. However, this is only an example, and the material is not limited thereto, as long as the material can protect the display panel DP from external impact or intrusion of foreign objects. In the electronic device ED according to some embodiments, the housing HU is omitted, but in the electronic device ED according to other embodiments, the display panel DP can be rolled by a separate hinge member and disposed inside the housing HU, which is not limited to the embodiments of the present disclosure.

[0055] Reference Figure 1BAccording to some embodiments, the electronic device ED-1 may be bent in the second direction DR2 relative to the virtual axis AX extending in the first direction DR1. Therefore, the display panel DP may be bent with a curvature (e.g., a set or predetermined curvature), and the housing HU may have a curvature corresponding to the curvature of the display panel DP. The embodiments of the present disclosure are not limited thereto, and the virtual axis AX may extend in the second direction DR2, or the display panel DP may be bent relative to a plurality of axes extending in different directions.

[0056] In addition, the display panel DP may be a rollable display panel, a foldable display panel, or a slidable display panel, and in an operating state, the entire display panel DP may be positioned inside the housing HU. Therefore, the display panel DP may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas indicating different directions.

[0057] Reference Figure 2 According to some embodiments of the present disclosure, the display panel DP includes a base layer BS, a circuit element layer DP-CL positioned on the base layer BS, a display element layer DP-OLED, an encapsulation layer TFE, a light control layer OSL, and a window panel WD. The display panel DP may also include a functional layer such as an anti-reflection layer or a refractive index adjustment layer. The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. The insulating layer to be described below may include an organic layer and / or an inorganic layer.

[0058] The base layer BS may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may be a polyimide resin layer, and the material of the synthetic resin layer is not particularly limited thereto. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. In addition, the base layer BS may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc.

[0059] The circuit element layer DP-CL forms an insulating layer, a semiconductor layer, and a conductive layer through processes such as coating and deposition. Then, the insulating layer, the semiconductor layer, and the conductive layer can be selectively patterned through photolithography and etching processes. Semiconductor patterns, conductive patterns, signal lines, etc. are formed through these processes. Patterns arranged in the same layer are formed by the same process.

[0060] The circuit element layer DP-CL includes a driving circuit or a signal line for driving the pixel PX. The display element layer DP-OLED may include a light emitting element OLED (see FIG. Figure 5 ) and pixel definition layer PDL (see Figure 5 ).

[0061] The encapsulation layer TFE may be positioned on the display element layer DP-OLED to protect the light emitting element OLED. The encapsulation layer TFE may include an inorganic layer and an organic layer positioned between the inorganic layers. The inorganic layer may protect the light emitting element OLED from moisture and oxygen, and the organic layer may protect the light emitting element OLED from foreign matter such as dust particles.

[0062] The light control layer OSL may include a color control layer that can change the optical properties of the source light beam generated by the light emitting element OLED. The color control layer may include quantum dots, and the light control layer OSL may include a color filter that selectively transmits the light beam through the color control layer. According to some embodiments, the light control layer OSL may be omitted.

[0063] The window panel WD may be positioned on the display panel DP and may transmit an image provided by the display panel DP to the outside. The window panel WD may include a base layer and a functional layer arranged on the base layer. The functional layer may include a protective layer, an anti-fingerprint layer, etc. The base layer of the window panel WD may be made of glass, sapphire, or plastic.

[0064] Figure 3A is a plan view of a display area according to some embodiments of the present disclosure. Figure 3B is an enlarged plan view of a display area of ​​a display panel according to some embodiments of the present disclosure.

[0065] Reference Figure 3A and Figure 3B , the display panel DP according to some embodiments may include pixels arranged in a unit area PU, a gate driving circuit GDC connected to the pixels, and signal lines.

[0066] The display panel DP may include a display area DA and a non-display area NDA. The light emitting layer EML (see FIG. 1 ) of the pixel positioned in the unit area PU Figure 5 ) is positioned in the display area DA, and the light emitting layer EML is not positioned in the non-display area NDA. The non-display area NDA may surround the display area DA. According to some embodiments of the present disclosure, the non-display area NDA may be omitted or may be positioned only on one side of the display area DA.

[0067] A plurality of unit areas PU may be provided within the display area DA. The unit areas PU may be arranged in the first direction DR1 and the second direction DR2. The unit area PU may include a light emitting area, through which the display panel DP provides information to the user, a transmissive area that increases the transparency of the display panel DP so that an object PD positioned at the rear side of the display panel DP may be transmitted to the user, and a signal line connected to the pixel is arranged in the wiring area.

[0068] Figure 3B An aspect of two unit regions PU (ie, a first unit region PU1 and a second unit region PU2 ) arranged in the second direction DR2 among the unit regions PU according to some embodiments is shown.

[0069] The first unit region PU1 may include light emitting regions PXA1-1, PXA1-2, and PXA1-3 spaced apart from each other in the first direction DR1, a first transmission region TA1 spaced apart from the light emitting regions PXA1-1, PXA1-2, and PXA1-3 in the second direction DR2, and a first wiring region LA1 spaced apart from the 1-1 light emitting region PXA1-1 and the first transmission region TA1 in the first direction DR1 and extending in the second direction DR2.

[0070] The second unit region PU2 may include light emitting regions PXA2-1, PXA2-2, and PXA2-3 spaced apart from each other in the first direction DR1, second transmission regions TA2 spaced apart from the light emitting regions PXA2-1, PXA2-2, and PXA2-3 in the second direction DR2, and second wiring regions LA2 spaced apart from the 2-1st light emitting region PXA2-1 and the second transmission region TA2 in the first direction DR1 and extending in the second direction DR2. The non-light emitting region NPXA may surround the light emitting region and the wiring region.

[0071] According to some embodiments, the first wiring area LA1 and the second wiring area LA2 may be connected to each other and may extend in the second direction DR2. Signal lines commonly connected to pixels arranged in the light emitting area may be arranged in the first wiring area LA1 and the second wiring area LA2. For example, the reference lines may be arranged in the wiring areas LA1 and LA2. Fig.7D The sensing lines SSL, the power lines EDL and the scan lines SCL are described.

[0072] According to the present disclosure, the wavelengths of the source light beams provided by the light emitting regions PXA1-1, PXA1-2, PXA1-3, PXA2-1, PXA2-2, and PXA2-3 may be different from each other. The light emitting regions PXA1-1, PXA1-2, PXA1-3, PXA2-1, PXA2-2, and PXA2-3 may be formed by a pixel defining layer PDL (see Figure 5 ) in the display opening PDL-OP (see Figure 5 ), the transmission areas TA1 and TA2 may be formed by a transmission opening T-OP (see FIG. Fig. 6A ) is defined. The area of ​​the display opening PDL-OP may be smaller than the area of ​​the transmission opening T-OP. A description related thereto will be made below.

[0073] Return to reference Figure 3AThe gate driving circuit GDC may be positioned in the non-display area NDA. The gate driving circuit GDC may be integrated into the display panel DP through an oxide silicon gate (OSG) driving circuit process or an amorphous silicon gate (ASG) driving circuit process.

[0074] Figure 4 is an equivalent circuit diagram of a pixel according to some embodiments of the present disclosure.

[0075] Figure 4 shows the relationship between the unit area PU (see Figure 3A )Aspects of the circuit diagram associated with a pixel PXij in ).

[0076] Reference Figure 4 , the pixel PXij may include a pixel circuit PC and a light emitting element OLED. The pixel circuit PC may include a plurality of transistors T1 to T3 and a capacitor Cst.

[0077] The plurality of transistors T1 to T3 may be formed by a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process. Each of the first transistor T1 to the third transistor T3 may include one of a silicon semiconductor and an oxide semiconductor. In this case, the oxide semiconductor may include a crystalline or amorphous oxide semiconductor, and the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc., but the embodiments of the present disclosure are not limited thereto.

[0078] Hereinafter, it will be described that the first transistor T1 to the third transistor T3 are N-type, but the embodiments of the present disclosure are not limited thereto, and each of the first transistor T1 to the third transistor T3 may be a P-type transistor or an N-type transistor according to a signal applied thereto. In this case, the source and the drain of the P-type transistor may correspond to the drain and the source of the N-type transistor, respectively.

[0079] Figure 4 Aspects of a pixel PXij connected to an i-th scan line SCLi, an i-th sensing line SSLi, a j-th data line DLj, and a j-th reference line IRj according to some embodiments are shown.

[0080] Figure 4 The pixel PXij shown in FIG. 1 may be included in the unit area PU (see Figure 3A) corresponds to one of the pixels in the pixel circuit. The pixel circuit PC may include a first transistor T1 (driving transistor), a second transistor T2 (switching transistor), a third transistor T3 (sensing transistor) and a capacitor Cst. However, the pixel circuit PC may also include additional transistors and additional capacitors, and the embodiments of the present disclosure are not limited thereto. That is, according to various embodiments, the pixel circuit PC may include additional components or fewer components without departing from the spirit and scope of the embodiments of the present disclosure.

[0081] The first to third transistors T1 to T3 may include sources S1 , S2 , and S3 , drains D1 , D2 , and D3 , and gates G1 , G2 , and G3 , respectively.

[0082] The light emitting element OLED may be an organic light emitting element or an inorganic light emitting element including an anode (first electrode) and a cathode (second electrode). The anode of the light emitting element OLED may receive a first voltage ELVDD through a first transistor T1, and the cathode of the light emitting element OLED may receive a second voltage ELVSS. The light emitting element OLED may emit a light beam by receiving the first voltage ELVDD and the second voltage ELVSS.

[0083] The first transistor T1 may include a drain electrode D1 receiving the first voltage ELVDD, a source electrode S1 connected to the anode of the light emitting element OLED, and a gate electrode G1 connected to the capacitor Cst. The first transistor T1 may control a driving current flowing from the first voltage ELVDD through the light emitting element OLED in response to a voltage value stored in the capacitor Cst.

[0084] The second transistor T2 may include a drain D2 connected to the jth data line DLj, a source S2 connected to the capacitor Cst, and a gate G2 receiving the i-th write scan signal SCi. The second transistor T2 supplies the data voltage Vd to the first transistor T1 in response to the i-th write scan signal SCi.

[0085] The third transistor T3 may include a source S3 connected to the jth reference line IRj, a drain D3 connected to the anode of the light emitting element OLED, and a gate G3 receiving the i-th sampling scan signal SSi. The jth reference line IRj may receive a reference voltage Vr.

[0086] The capacitor Cst may store various voltage differences according to an input signal. For example, the capacitor Cst may store a voltage corresponding to a difference between a voltage received from the second transistor T2 and the first voltage ELVDD.

[0087] In the present disclosure, the equivalent circuit of the pixel PXij is not limited to Figure 4According to some embodiments of the present disclosure, the pixel PXij may be implemented in various forms to allow the light emitting element OLED to emit a light beam.

[0088] Figure 5 It is along Figure 3B A cross-sectional view taken along line II'. Fig. 6A It is along Figure 3B A cross-sectional view taken along line II-II'. Figure 6B is a cross-sectional view of a display panel according to some embodiments of the present disclosure. Figure 6C is a cross-sectional view of a display panel according to some embodiments of the present disclosure. Figure 5 Only some of the components of the display panel DP are shown, and the light control layer OSL and the window panel WD are omitted.

[0089] Reference Figure 5 , the display panel DP may include a base layer BS, a circuit element layer DP-CL positioned on the base layer BS, a display element layer DP-OLED, and an encapsulation layer TFE.

[0090] The base layer BS may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin and perylene resin. In addition, the base layer BS may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc.

[0091] The circuit element layer DP-CL forms an insulating layer, a semiconductor layer, and a conductive layer through processes such as coating and deposition. Then, the insulating layer, the semiconductor layer, and the conductive layer can be selectively patterned through photolithography and etching processes. Semiconductor patterns, conductive patterns, signal lines, etc. are formed through these processes. Patterns arranged in the same layer are formed by the same process.

[0092] The circuit element layer DP-CL includes a driving circuit or a signal line constituting the pixel PX. The display element layer DP-OLED may include a light emitting element OLED (see Figure 4 ) and pixel defining layer PDL.

[0093] The circuit element layer DP-CL may include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50 and a conductive pattern. According to some embodiments, the first insulating layer 10 to the fourth insulating layer 40 may be an inorganic layer including a single layer or multiple layers, and the fifth insulating layer 50 may be an organic layer.

[0094] The light shielding pattern BML may be positioned on the base layer BS. According to some embodiments, the light shielding pattern BML may be connected to the semiconductor pattern of the first transistor T1 stacked therewith, may receive a signal applied to the semiconductor pattern, and may form a synchronization structure under the semiconductor pattern. According to some embodiments, the light shielding pattern BML may include sequentially stacked metal layers. For example, the first layer of the light shielding pattern BML may include titanium, and the second layer may include copper.

[0095] The first insulating layer 10 may be positioned on the base layer BS and cover the light shielding pattern BML. According to some embodiments, the first insulating layer 10 may include sequentially stacked inorganic layers. For example, the first layer of the first insulating layer 10 may include silicon nitride, and the second layer may include silicon oxide.

[0096] The semiconductor pattern of the first transistor T1 may be positioned on the first insulating layer 10. The semiconductor pattern may include a source S1, a channel region A1 (or an active region or an active pattern), and a drain D1. According to some embodiments, the semiconductor pattern may include indium gallium zinc oxide (IGZO).

[0097] The second insulating layer 20 may be positioned between the semiconductor pattern and the gate G1. The second insulating layer 20 may expose a region of the semiconductor pattern except the active pattern A1. The second insulating layer 20 may be patterned using the gate G1 as a mask. According to some embodiments, the second insulating layer 20 may include silicon oxide.

[0098] The gate G1 may be positioned on the second insulating layer 20. According to some embodiments, the gate G1 may include sequentially stacked metal layers. For example, the first layer of the gate G1 may include titanium, and the second layer may include copper.

[0099] The third insulating layer 30 may be positioned on the first insulating layer 10 and the second insulating layer 20, and may cover the gate G1 and the semiconductor pattern exposed from the gate G1. According to some embodiments, the third insulating layer 30 may include silicon oxynitride.

[0100] The first connection electrode CNE1 may be positioned on the third insulating layer 30. The first connection electrode CNE1 may be connected to the source electrode S1 through a contact hole defined in the third insulating layer 30. According to some embodiments, the first connection electrode CNE1 may include a metal layer and a metal oxide layer stacked sequentially. For example, the first layer of the first connection electrode CNE1 may include titanium, the second layer may include copper, and the third layer may include indium tin oxide (ITO).

[0101] The fourth insulating layer 40 may be positioned on the third insulating layer 30 and cover the first connection electrode CNE1. According to some embodiments, the fourth insulating layer 40 may include silicon nitride. Compared with a layer including silicon oxide and / or silicon oxynitride, a layer including silicon nitride has a dense film quality, thereby reducing transmittance. Therefore, in order to increase the transmittance in the transparent display panel DP as in the present disclosure, it is necessary to remove silicon nitride from the transmission areas TA1 and TA2.

[0102] The second connection electrode CNE2 may be positioned on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole defined in the fourth insulating layer 40. According to some embodiments, the second connection electrode CNE2 may include the same material as that of the first connection electrode CNE1. In the display panel DP according to some embodiments, the second connection electrode CNE2 may be omitted, but embodiments according to the present disclosure are not limited thereto.

[0103] The fifth insulating layer 50 may be positioned on the fourth insulating layer 40 and cover the second connection electrode CNE2. According to some embodiments, the fifth insulating layer 50 may include an organic material. For example, the fifth insulating layer 50 may include photosensitive polyimide (PSPI).

[0104] The display element layer DP-OLED may be positioned on the fifth insulating layer 50. The display element layer DP-OLED may include a light emitting element OLED and a pixel defining layer PDL. The light emitting element OLED may include a first electrode AE, a light emitting layer EML, and a second electrode CE. The light emitting element OLED according to some embodiments may further include a hole control layer HCL and an electron control layer ECL.

[0105] The pixel defining layer PDL may be positioned on the fifth insulating layer 50 and cover the second connection electrode CNE2. The pixel defining layer PDL may include an organic material. For example, the pixel defining layer PDL may include PSPI. The pixel defining layer PDL may include a display opening PDL-OP. A plurality of display openings PDL-OP of the pixel defining layer PDL may be provided, and the display opening PDL-OP may be formed by Figure 3B The light emitting region described in the above is defined. The region where the pixel defining layer PDL is disposed may be defined as a non-light emitting region.

[0106] The first electrode AE ​​of the light emitting element OLED is positioned on the fifth insulating layer 50. The display opening PDL-OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE. According to some embodiments, the first electrode AE ​​may include a metal layer and a metal oxide layer stacked in sequence. For example, the first layer of the first electrode AE ​​may include indium tin oxide (ITO), the second layer may include silver, and the third layer may include indium tin oxide (ITO).

[0107] The hole control layer HCL may be commonly positioned in the light emitting region and the non-light emitting region. Common layers such as the hole control layer HCL may be commonly arranged in pixels. In this specification, a layer formed as a common layer may be entirely arranged in the display area DA (see Figure 3A ) and non-display area NDA (see Figure 3A ). The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0108] The light emitting layer EML is positioned on the hole control layer HCL. The light emitting layer EML may be commonly arranged in the light emitting region and the non-light emitting region. The light emitting layer EML may generate a source light beam. The light emitting layer EML may include an organic light emitting material or an inorganic light emitting material. According to some embodiments, the source light beams generated by the pixels arranged in one unit region PU may have different colors.

[0109] The electron control layer ECL is positioned on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and an electron injection layer. The second electrode CE is positioned on the electron control layer ECL. According to some embodiments, the second electrode CE may be described as a cathode. The hole control layer HCL, the light emitting layer EML, and the electron control layer ECL may be defined as a common layer.

[0110] The encapsulation layer TFE may be positioned on the display element layer DP-OLED to protect the light emitting element OLED. The encapsulation layer TFE may include an inorganic layer and an organic layer positioned between the inorganic layers. The inorganic layer may protect the light emitting element OLED from moisture and oxygen, and the organic layer may protect the light emitting element OLED from foreign matter such as dust particles.

[0111] The inorganic layer may prevent external moisture or oxygen from penetrating into the light emitting layer EML. The inorganic layer may include silicon nitride, silicon oxide, or a composite obtained by combining them. The inorganic layer may be formed by a deposition process.

[0112] The organic layer may provide a planarized surface on the inorganic layer. Curves formed in the upper surface of the inorganic layer or particles present on the inorganic layer may be covered by the organic layer, thereby preventing the surface condition of the upper surface of the inorganic layer from affecting the components formed on the organic layer. The organic layer may include an organic material.

[0113] Reference Fig. 6A In the display panel DP according to some embodiments, at least some of the insulating layers arranged in the first transmission area TA1 (hereinafter also simply referred to as “transmission area TA1”) may be removed to relatively improve the transmittance of the transmission area TA1.

[0114] According to some embodiments, the base layer BS, the first insulating layer 10, and the third insulating layer 30 may be arranged in the transmission area TA1. The fourth insulating layer 40 may include a first insulating opening 40-OP overlapping the transmission area TA1. The first insulating opening 40-OP may be defined by a side surface 40-S of the fourth insulating layer 40, which is formed as a portion of the fourth insulating layer 40 overlapping the transmission area TA1 is passed through. The first insulating opening 40-OP may be formed by removing the fourth insulating layer 40 through a dry etching process. The fifth insulating layer 50 may include an upper insulating opening overlapping the first insulating opening 40-OP.

[0115] In the pixel definition layer PDL, it is possible to define Figure 3B The display openings PDL-OP corresponding to the light emitting areas PXA1-1, PXA1-2 and PXA1-3 described in Figure 5 ) and Figure 3B The transmission opening T-OP corresponds to the transmission area TA1 described in the figure. The transmission opening T-OP may overlap with the first insulating opening 40-OP. The transmission opening T-OP may be defined by a side surface PDL-S of the pixel defining layer PDL, which is formed as a portion of the pixel defining layer PDL overlapping the transmission area TA1 is passed through.

[0116] According to some embodiments, in the second direction DR2 , the width of the first insulating opening 40 -OP may be greater than the width of the transmissive opening T-OP.

[0117] According to some embodiments, the side surface 40-S of the fourth insulating layer 40 defining the first insulating opening 40-OP may be covered by the pixel defining layer PDL. That is, the side surface 40-S of the fourth insulating layer 40 may be in contact with the pixel defining layer PDL. In addition, the upper surface 40-U of the fourth insulating layer 40 exposed from the fifth insulating layer 50 may also be in contact with the pixel defining layer PDL. According to some embodiments, the fourth insulating layer 40 may be spaced apart from the transmission area TA1.

[0118] According to some embodiments, the upper surface 30-E of the third insulating layer 30 may be exposed from the fourth insulating layer 40 and the pixel defining layer PDL through the first insulating opening 40-OP and the transmissive opening T-OP. Common layers included in the encapsulation layer TFE and / or the light emitting element OLED may be arranged on the upper surface 30-E of the third insulating layer 30.

[0119] The above description of the transmissive area TA1 can be commonly applied to Figure 3AThus, in a plane, a plurality of openings spaced apart from each other in the first direction DR1 and the second direction DR2 may be defined in the fourth insulating layer 40 and the pixel defining layer PDL. The openings may be arranged in the first direction DR1 and the second direction DR2 in a plane.

[0120] According to the present disclosure, the fourth insulating layer 40 including silicon nitride may not be positioned in the transmission area TA1 of the transparent display panel DP. Therefore, the transmittance of the transmission area TA1 may be relatively improved. In addition, since the side surface 40-S of the fourth insulating layer 40 defining the first insulating opening 40-OP is covered by the pixel defining layer PDL, the phenomenon that the fourth insulating layer 40 is peeled off from the third insulating layer 30 in the area adjacent to the transmission area TA1 may be reduced. Therefore, a display panel DP having relatively improved transmittance and relatively improved reliability may be provided.

[0121] Reference Figure 6B , in the display panel DP-A according to some embodiments, at least some of the insulating layers arranged in the transmission area TA1 may be removed to relatively improve the transmittance of the transmission area TA1.

[0122] According to some embodiments, the base layer BS and the first insulating layer 10 may be arranged in the transmission area TA1. The fourth insulating layer 40 may include a first insulating opening 40-OP overlapping the transmission area TA1. The first insulating opening 40-OP may be defined by a side surface 40-S of the fourth insulating layer 40, which is formed as a portion of the fourth insulating layer 40 overlapping the transmission area TA1 is passed through.

[0123] According to some embodiments, the third insulating layer 30 may include a second insulating opening 30-OP overlapping the transmission area TA1. The second insulating opening 30-OP may overlap the first insulating opening 40-OP. The second insulating opening 30-OP may be defined by a side surface 30-S of the third insulating layer 30, which is formed as a portion of the third insulating layer 30 overlapping the transmission area TA1 is passed through.

[0124] In the pixel definition layer PDL, it is possible to define Figure 3B The display openings PDL-OP corresponding to the light emitting areas PXA1-1, PXA1-2 and PXA1-3 described in Figure 5 ) and Figure 3BThe transmission opening T-OP corresponds to the transmission area TA1 described in the figure. The transmission opening T-OP may overlap the first insulating opening 40-OP and the second insulating opening 30-OP. The transmission opening T-OP may be defined by a side surface PDL-S of the pixel defining layer PDL, which is formed as a portion of the pixel defining layer PDL overlapping the transmission area TA1 is passed through.

[0125] According to some embodiments, in the second direction DR2 , the width of the first insulating opening 40 -OP may be greater than the width of the transmissive opening T-OP and the width of the second insulating opening 30 -OP.

[0126] According to some embodiments, the side surface 40-S of the fourth insulating layer 40 defining the first insulating opening 40-OP and the side surface 30-S of the third insulating layer 30 defining the second insulating opening 30-OP may be covered by the pixel defining layer PDL. That is, the side surface 40-S of the fourth insulating layer 40 and the side surface 30-S of the third insulating layer 30 may be in contact with the pixel defining layer PDL. In addition, the upper surface 40-U of the fourth insulating layer 40 exposed from the fifth insulating layer 50 may also be in contact with the pixel defining layer PDL. According to some embodiments, the fourth insulating layer 40 may be spaced apart from the transmission area TA1.

[0127] According to some embodiments, the upper surface 10 -E of the first insulating layer 10 may be exposed from the third insulating layer 30 and the pixel defining layer PDL through the second insulating opening 30 -OP and the transmissive opening T-OP.

[0128] Reference Figure 6C , in the display panel DP-B according to some embodiments, at least some of the insulating layers arranged in the transmission area TA1 may be removed to relatively improve the transmittance of the transmission area TA1.

[0129] According to some embodiments, the base layer BS may be positioned in the transmission area TA1. The fourth insulating layer 40 may include a first insulating opening 40-OP overlapping the transmission area TA1. The first insulating opening 40-OP may be defined by a side surface 40-S of the fourth insulating layer 40, which is formed as a portion of the fourth insulating layer 40 overlapping the transmission area TA1 is passed through.

[0130] The third insulating layer 30 may include a second insulating opening 30-OP overlapping the transmission area TA1. The second insulating opening 30-OP may overlap the first insulating opening 40-OP. The second insulating opening 30-OP may be defined by a side surface 30-S of the third insulating layer 30, which is formed as a portion of the third insulating layer 30 overlapping the transmission area TA1 is passed through.

[0131] According to some embodiments, the first insulating layer 10 may include a third insulating opening 10-OP overlapping the transmission area TA1. The third insulating opening 10-OP may overlap the first insulating opening 40-OP and the second insulating opening 30-OP. The third insulating opening 10-OP may be defined by a side surface 10-S of the first insulating layer 10, which is formed as a portion of the first insulating layer 10 overlapping the transmission area TA1 is passed through.

[0132] In the pixel definition layer PDL, it is possible to define Figure 3B The display openings PDL-OP corresponding to the light emitting areas PXA1-1, PXA1-2 and PXA1-3 described in Figure 5 ) and Figure 3B The transmission opening T-OP corresponds to the transmission area TA1 described in the figure. The transmission opening T-OP may overlap with the first to third insulating openings 40-OP to 10-OP. The transmission opening T-OP may be defined by a side surface PDL-S of the pixel defining layer PDL, which is formed as a portion of the pixel defining layer PDL overlapping the transmission area TA1 is passed through.

[0133] According to some embodiments, the side surface 40-S of the fourth insulating layer 40 defining the first insulating opening 40-OP, the side surface 30-S of the third insulating layer 30 defining the second insulating opening 30-OP, and the side surface 10-S of the first insulating layer 10 defining the third insulating opening 10-OP may be covered by the pixel defining layer PDL. That is, the side surface 40-S of the fourth insulating layer 40, the side surface 30-S of the third insulating layer 30, and the side surface 10-S of the first insulating layer 10 may be in contact with the pixel defining layer PDL. In addition, the upper surface 40-U of the fourth insulating layer 40 exposed from the fifth insulating layer 50 may also be in contact with the pixel defining layer PDL. According to some embodiments, the fourth insulating layer 40 may be spaced apart from the transmission area TA1.

[0134] According to some embodiments, the upper surface BS-E of the base layer BS may be exposed from the first insulating layer 10 and the pixel defining layer PDL through the third insulating openings 10 -OP and the transmissive openings T-OP.

[0135] 7A to 7H It shows that the layout is distinguished according to each layer. Figure 3B A plan view of the stacking order of the conductive patterns in the region QQ'. 7A to 7H The layout is shown according to each layer. Figure 3B 1-1, PXA1-2, and PXA1-3 and the conductive patterns in the first wiring area LA1 described in the drawings. 7A to 7HThe description includes the arrangement in a unit area PU (see Figure 3A ) in the three pixels of the pixel circuit PC (see Figure 4 ). Figure 5 and Fig. 6A The construction described in is described.

[0136] Reference Fig. 7A According to some embodiments of the display panel DP (see Figure 5 ) may include a first conductive layer MSL1. The first conductive layer MSL1 may be positioned on the base layer BS (see Fig. 6A ) and can be covered by the first insulating layer 10 (see Fig. 6A )cover.

[0137] The first conductive layer MSL1 may include a first line E-1, a first reference line IL1, a first power line EBR, a first light shielding pattern BML1, a second light shielding pattern BML2, and a third light shielding pattern BML3, and a first data line DL1, a second data line DL2, and a third data line DL3. The first conductive layer MSL1 may include sequentially stacked metal layers. For example, a first layer of the first conductive layer MSL1 may include titanium, and a second layer may include copper.

[0138] Each of the first line E-1, the first reference line IL1, the first power line EBR, and the first, second, and third data lines DL1, DL2, and DL3 may extend in the first direction DR1. The first light shielding pattern BML1, the second light shielding pattern BML2, and the third light shielding pattern BML3 may be spaced apart from each other in the first direction DR1. The first line E-1 may be spaced apart from the first power line EBR in the second direction DR2, and the first reference line IL1 is disposed between the first line E-1 and the first power line EBR. The first power line EBR may be positioned between the first reference line IL1 and the first, second, and third light shielding patterns BML1, BML2, and BML3.

[0139] Among the first, second and third data lines DL1, DL2 and DL3, the second data line DL2 may be positioned closest to the first, second and third light shielding patterns BML1, BML2 and BML3, and the third data line DL3 may be positioned between the first and second data lines DL1 and DL2.

[0140] Reference Figure 7B According to some embodiments of the display panel DP (see Figure 5 ) may include a second conductive layer MSL2. The second conductive layer MSL2 may be positioned on the first insulating layer 10 and may be surrounded by a second insulating layer 20 (see Fig. 6A ) and the third insulating layer 30 (see Fig. 6A )cover.

[0141] The second conductive layer MSL2 may include a first active pattern A1, a second active pattern A2, and a third active pattern A3 included in three pixels. A portion of the first active pattern A1 may overlap the first power line EBR, and another portion of the first active pattern A1 may overlap a corresponding light shielding pattern among the first light shielding pattern BML1, the second light shielding pattern BML2, and the third light shielding pattern BML3. The second conductive layer MSL2 may include indium gallium zinc oxide (IGZO).

[0142] Reference Figure 7C According to some embodiments of the display panel DP (see Figure 5 ) may include a third conductive layer MSL3. The third conductive layer MSL3 may be positioned on the first insulating layer 10 and the second insulating layer 20. Figure 7C Together, it shows the Figure 5 The contact hole CNT of at least one of the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30 described in FIG.

[0143] The contact holes CNT overlapping the first conductive layer MSL1 and the second conductive layer MSL2 can be defined by penetrating the first insulating layer 10, the contact holes CNT overlapping the second conductive layer MSL2 and the third conductive layer MSL3 can be defined by penetrating the second insulating layer 20, and the contact holes CNT overlapping the third conductive layer MSL3 and the fourth conductive layer MSL4 (see FIG. Fig.7D ) can be defined by penetrating the third insulating layer 30, and the contact hole overlapping the first conductive layer MSL1 and the fourth conductive layer MSL4 among the contact holes CNT can be defined by penetrating the first insulating layer 10 and the third insulating layer 30.

[0144] The third conductive layer MSL3 may include a second line E-2, a sensing pattern SS-P, power supply patterns ED1 and ED2, a first lower capacitor pattern CS1-1, a second lower capacitor pattern CS2-1, and a third lower capacitor pattern CS3-1, and a scan pattern SC-P. The third conductive layer MSL3 may include sequentially stacked metal layers. For example, a first layer of the third conductive layer MSL3 may include titanium, and a second layer may include copper.

[0145] A region of the first active pattern A1 overlapping the first lower capacitor pattern CS1-1, the second lower capacitor pattern CS2-1, and the third lower capacitor pattern CS3-1 may be defined as a first transistor T1 (see Figure 4 ), a region of the second active pattern A2 overlapping the scan pattern SC-P may be defined as a second transistor T2 (see Figure 4), a region of the third active pattern A3 overlapping the sensing pattern SS-P may be defined as a third transistor T3 (see Figure 4 )'s gate G3.

[0146] Portions of the first lower capacitor pattern CS1-1, the second lower capacitor pattern CS2-1, and the third lower capacitor pattern CS3-1 that do not overlap the first active pattern A1 may overlap with the first upper capacitor pattern CS1-2, the second upper capacitor pattern CS2-2, and the third upper capacitor pattern CS3-2 to be described below in one-to-one correspondence, thereby forming Figure 4 The first lower capacitor pattern CS1-1, the second lower capacitor pattern CS2-1, and the third lower capacitor pattern CS3-1 may be connected to the corresponding second active pattern A2 through the contact holes CNT.

[0147] The second wire E-2 may extend in the first direction DR1 and may overlap the first wire E-1. The second wire E-2 may be connected to the first wire E-1 through the contact hole CNT.

[0148] The sensing pattern SS-P may extend in the first direction DR1 and may be positioned between the first reference line IL1 and the first power line EBR on a plane.

[0149] The scan pattern SC-P may extend in the first direction DR1 and may be positioned between the first, second, and third lower capacitor patterns CS1-1, CS2-1, and CS3-1 and the first, second, and third data lines DL1, DL2, and DL3 on a plane.

[0150] The first power pattern ED1 and the second power pattern ED2 may overlap the first power line EBR on a plane. The first power pattern ED1 and the second power pattern ED2 may be spaced apart from each other in the first direction DR1. The first power pattern ED1 and the second power pattern ED2 may be arranged in each pixel. Thus, the first power pattern ED1 and the second power pattern ED2 may be arranged in a unit area PU (see Figure 3A ) are arranged in the first power pattern ED1 and the second power pattern ED2 may be connected to the first power line EBR through the contact hole CNT.

[0151] Reference Fig.7D According to some embodiments of the display panel DP (see Figure 5 ) may include a fourth conductive layer MSL4. The fourth conductive layer MSL4 may be positioned on the third insulating layer 30 and may be surrounded by a fourth insulating layer 40 (see Fig. 6A )cover.

[0152] The fourth conductive layer MSL4 may include a third line E-3, a second reference line IL2, a second power line EB-P, a first upper capacitor pattern CS1-2, a second upper capacitor pattern CS2-2, and a third upper capacitor pattern CS3-2, a first connection pattern A-P1, a second connection pattern A-P2, and a third connection pattern A-P3, and a first data pattern DL-P1, a second data pattern DL-P2, and a third data pattern DL-P3. The fourth conductive layer MSL4 may include sequentially stacked metal layers. For example, the first layer of the fourth conductive layer MSL4 may include titanium, the second layer may include copper, and the third layer may include indium tin oxide (ITO).

[0153] The third wire E-3 may overlap the second wire E-2 and may extend in the first direction DR1. The third wire E-3 may be connected to the first wire E-1 and the second wire E-2 through the contact hole CNT. The first wire E-1 to the third wire E-3 may be provided in multiple layers and connected to each other, thereby reducing resistance. The description related thereto may be commonly applied to conductive patterns arranged in multiple layers and connected to each other.

[0154] The second reference line IL2 may overlap the first reference line IL1 and may extend in the first direction DR1. The second reference line IL2 may be connected to the first reference line IL1 through the contact hole CNT.

[0155] The second power line EB-P may overlap the first power line EBR and the first and second power patterns ED1 and ED2, and may extend in the first direction DR1. The second power line EB-P may be connected to the first power line EBR and the first and second power patterns ED1 and ED2 through a contact hole CNT. In addition, the second power line EB-P may be connected to one side of the first active pattern A1 through a contact hole CNT.

[0156] The first upper capacitor pattern CS1-2, the second upper capacitor pattern CS2-2, and the third upper capacitor pattern CS3-2 may overlap the first lower capacitor pattern CS1-1, the second lower capacitor pattern CS2-1, and the third lower capacitor pattern CS3-1, respectively, and may be connected through the contact holes CNT. In addition, each of the first upper capacitor pattern CS1-2, the second upper capacitor pattern CS2-2, and the third upper capacitor pattern CS3-2 may be connected to the other side of the first active pattern A1 through the corresponding contact hole CNT.

[0157] The first connection pattern A-P1 may connect the second active pattern A2 and the first lower capacitor pattern CS1-1 through the contact hole CNT. The second connection pattern A-P2 may connect the second active pattern A2 and the second lower capacitor pattern CS2-1 through the contact hole CNT. The third connection pattern A-P3 may connect the third active pattern A3 and the third lower capacitor pattern CS3-1 through the contact hole CNT.

[0158] The first data pattern DL-P1 may connect the second active pattern A2 and the first data line DL1 through the contact hole CNT. The second data pattern DL-P2 may connect the second active pattern A2 and the second data line DL2 through the contact hole CNT. The third data pattern DL-P3 may connect the second active pattern A2 and the third data line DL3 through the contact hole CNT.

[0159] exist Figure 3B The first and second wiring areas LA1 and LA2 described in the accompanying drawings may include sensing lines SSL, power lines EDL, and scan lines SCL extending in the second direction DR2 and spaced apart from each other in the first direction DR1.

[0160] The sensing line SSL may be connected to the sensing pattern SS-P through the contact hole CNT. The scan line SCL may be connected to the scan pattern SC-P through the contact hole CNT. The power line EDL may be connected to the first power line EBR through the contact hole CNT.

[0161] Fig. 7E Shown through the Figure 5 The fourth contact hole CNT4 of the fourth insulating layer 40 described in Figure 7F Shown through the Figure 5 The fourth insulating layer 40 may include silicon nitride, and the fifth insulating layer 50 may include PSPI.

[0162] A fourth contact hole CNT4 may be defined in the fourth insulating layer 40 overlapping the first, second, and third upper capacitor patterns CS1-2, CS2-2, and CS3-2. In addition, at least one fourth contact hole CNT4 may be defined in the fourth insulating layer 40 overlapping the third line E-3.

[0163] A fifth contact hole CNT5 may be defined in the fifth insulating layer 50 overlapping the fourth contact hole CNT4 .

[0164] Reference Figure 7G , the fifth conductive layer MSL5 may include Figure 5The first electrodes AE1, AE2 and AE3 in the light emitting element OLED described in the embodiment of the present invention may be used. In addition, the fifth conductive layer MSL5 may include a power pattern EP overlapped with the third line E-3. The fifth conductive layer MSL5 may include sequentially stacked metal layers. For example, the first layer of the fifth conductive layer MSL5 may include indium tin oxide (ITO), the second layer may include silver, and the third layer may include indium tin oxide (ITO).

[0165] The first electrodes AE1, AE2, and AE3 may be spaced apart from each other in the first direction DR1. The first electrodes AE1, AE2, and AE3 may be connected to the first upper capacitor pattern CS1-2, the second upper capacitor pattern CS2-2, and the third upper capacitor pattern CS3-2 through the fourth contact hole CNT4 and the fifth contact hole CNT5, respectively. The first electrodes AE1, AE2, and AE3 may receive a first voltage ELVDD through the power line EDL.

[0166] The power pattern EP may be connected to the third line E-3 through the fourth contact hole CNT4 and the fifth contact hole CNT5. Figure 5 The second electrode CE described in the above may be connected to the power pattern EP. The second electrode CE may receive the second voltage ELVSS. The light emitting element OLED may emit a light beam by receiving the first voltage ELVDD and the second voltage ELVSS.

[0167] Reference Figure 7H , the pixel defining layer PDL may include a first display opening PXA1, a second display opening PXA2, and a third display opening PXA3, and at least a portion of the first electrodes AE1, AE2, and AE3 are exposed through the first display opening PXA1, the second display opening PXA2, and the third display opening PXA3, respectively. The first display opening PXA1, the second display opening PXA2, and the third display opening PXA3 may be exposed to the Figure 3B The first light emitting area PXA1-1, the second light emitting area PXA1-2, and the third light emitting area PXA1-3 described in the embodiment correspond one to one. The pixel defining layer PDL may include PSPI.

[0168] The pixel defining layer PDL may include a power opening E-OP, and at least a portion of the power pattern EP is exposed through the power opening E-OP. Figure 5 The second electrode CE described in EMBODIMENT 3 may be connected to the power pattern EP through the power opening E-OP.

[0169] FIG. 8A to FIG. 8C is a cross-sectional view according to a comparative example. FIG. 8A to FIG. 8C is a comparative example for describing a problem that may occur when the side surface 40 -S of the fourth insulating layer 40 including silicon nitride is not covered by the pixel defining layer PDL, which is different from the present disclosure.

[0170] like Fig. 8A As shown in , according to the first comparative example, the side surface 40-S of the fourth insulating layer 40 including silicon nitride may be exposed from the pixel defining layer PDL. In this case, due to the step of the light emitting layer EML formed by the side surface 40-S of the fourth insulating layer 40, a crack CR may be generated in the second electrode CE entirely formed on the base layer BS. Therefore, the second electrode CE may be disconnected. This may reduce the reliability of the transparent display panel.

[0171] like Figure 8B As shown in FIG. 1 , according to the second comparative example, unlike the present disclosure, the fifth insulating layer 50 including an organic material may cover the side surface 40-S of the fourth insulating layer 40. In the case where the fifth insulating layer 50 having a relatively large thickness covers the side surface 40-S of the fourth insulating layer 40, when the first electrode AE ​​is removed from the transmission area TA by an etching process in a subsequent process (see FIG. 1 ), the first electrode AE ​​is removed from the transmission area TA by an etching process. Figure 5 ), a problem may occur that particles AE-P remain at the end of the fifth insulating layer 50. This may reduce the transparency of the transmission area in the transparent display panel.

[0172] like Figure 8C As shown in , according to the third comparative example, the pixel defining layer PDL may cover the fifth insulating layer 50, and the fifth insulating layer 50 covers the side surface 40-S of the fourth insulating layer 40. In this case, the contact area between the pixel defining layer PDL and the third insulating layer 30 including an inorganic material is reduced, and thus the distal end of the pixel defining layer PDL may be peeled off from the third insulating layer 30.

[0173] like Fig. 6A As described in , according to the display panel DP according to the present disclosure, the upper surface 40-U and the side surface 40-S of the fourth insulating layer 40 including silicon nitride may be exposed from the fifth insulating layer 50 and may be covered by the pixel defining layer PDL. In addition, the pixel defining layer PDL covers the fourth insulating layer 40 including an inorganic material and contacts the third insulating layer 30, so that the contact area between the pixel defining layer PDL and the third insulating layer 30 may be ensured. Therefore, a display panel DP having increased transparency and relatively improved reliability in the transmission areas TA1 and TA2 may be provided.

[0174] According to some embodiments of the present disclosure, a display panel having relatively increased transparency and relatively improved reliability in a transmissive region included in a display region of the display panel may be provided.

[0175] Although the above has been described with reference to aspects of some embodiments of the present disclosure, it will be appreciated that various modifications and changes may be made to the present disclosure by those skilled in the art or persons of ordinary skill in the art without departing from the spirit and technical scope of the present disclosure as described in the appended claims.

[0176] Therefore, the technical scope of the embodiments according to the present disclosure should not be limited to the detailed description of the specification, but should be defined by the appended claims and their equivalents.

Claims

1. A display panel, comprising: A substrate layer including a display area including a transmission area and a non-display area adjacent to the display area; a light shielding pattern on the base layer; a first insulating layer covering the light shielding pattern; a transistor overlapping the light shielding pattern and including a semiconductor pattern on the first insulating layer and a gate on the semiconductor pattern; a second insulating layer, between the semiconductor pattern and the gate; a third insulating layer, covering the transistor; a first connection electrode on the third insulating layer and connected to the semiconductor pattern through a contact hole defined in the third insulating layer; a fourth insulating layer, covering the first connecting electrode; a pixel defining layer, comprising a display opening not overlapping the transmission area and on the fourth insulating layer; as well as a light emitting element on the fourth insulating layer and comprising a first electrode, a second electrode and a light emitting layer, wherein the first electrode is exposed through the display opening and connected to the first connecting electrode, and the light emitting layer is between the first electrode and the second electrode, The fourth insulating layer includes a first insulating opening overlapping the transmission area, and The pixel defining layer includes a transmissive opening overlapping the first insulating opening.

2. The display panel according to claim 1, wherein: In a plane, a width of the first insulating opening is greater than a width of the transmissive opening.

3. The display panel according to claim 1, wherein: A side surface of the fourth insulating layer defining the first insulating opening contacts the pixel defining layer.

4. The display panel according to claim 1, wherein: The fourth insulating layer includes silicon nitride, and The pixel defining layer includes photosensitive polyimide.

5. The display panel according to claim 1, wherein: In the transmission area, the third insulating layer is exposed from the pixel defining layer through the transmission opening.

6. The display panel according to claim 1, wherein: The third insulating layer includes a second insulating opening overlapping the first insulating opening, and A side surface of the fourth insulating layer defining the first insulating opening and a side surface of the third insulating layer defining the second insulating opening are in contact with the pixel defining layer.

7. The display panel according to claim 6, wherein: In the transmission area, the first insulating layer is exposed from the pixel defining layer through the transmission opening.

8. The display panel according to claim 6, wherein: The first insulating layer includes a third insulating opening overlapping the second insulating opening, and A side surface of the first insulating layer defining the third insulating opening is in contact with the pixel defining layer.

9. The display panel according to claim 8, wherein: In the transmission area, the base layer is exposed from the pixel defining layer through the transmission opening.

10. The display panel according to claim 1, further comprising: The data line, connected to the transistor, Wherein, the data line and the light shielding pattern are in the same layer.

11. The display panel according to claim 1, wherein: The display opening has an area smaller than that of the transmission opening.

12. The display panel according to claim 1, further comprising: a fifth insulating layer, between the fourth insulating layer and the pixel defining layer, wherein the fifth insulating layer comprises an upper insulating opening overlapping the first insulating opening, and A side surface of the fifth insulating layer defining the upper insulating opening contacts the pixel defining layer.

13. The display panel according to claim 12, wherein: An upper surface of the fourth insulating layer adjacent to a side surface of the fourth insulating layer defining the first insulating opening is exposed from the fifth insulating layer through the upper insulating opening, and The upper surface contacts the pixel defining layer.

14. The display panel according to claim 12, wherein: The fifth insulating layer includes photosensitive polyimide.

15. The display panel according to claim 12, further comprising: The second connection electrode is on the fourth insulating layer, covered by the fifth insulating layer, and connected to the first connection electrode through a contact hole defined in the fourth insulating layer.

16. The display panel according to claim 1, wherein: The first insulating layer includes a first layer including silicon nitride and a second layer including silicon oxide, The second insulating layer includes silicon oxide, and The third insulating layer includes silicon oxynitride.

17. The display panel according to claim 1, wherein: Each of the light shielding pattern and the gate electrode includes a first layer including titanium and a second layer including copper, The semiconductor pattern includes indium gallium zinc oxide, and The first connection electrode includes a first layer including titanium, a second layer including copper, and a third layer including indium tin oxide.

18. The display panel according to claim 1, wherein: The first electrode includes a first layer including indium tin oxide, a second layer including silver, and a third layer including indium tin oxide.

19. The display panel according to claim 1, further comprising: The encapsulation layer covers the light emitting element and includes an inorganic layer and an organic layer between the inorganic layers.

20. The display panel according to claim 1, wherein: An object on the rear side of the display panel is visible from the front surface of the display panel.

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