Semiconductor device and preparation method thereof, and memory system

Abstract

The invention provides a semiconductor device and a preparation method thereof and a memory system, and the semiconductor device comprises a first semiconductor structure, and the first semiconductor structure comprises a first selection transistor which comprises a first channel layer; a second selection transistor including a gate; the capacitor structure comprises a first electrode layer; two ends of the first electrode layer are respectively connected with the grid electrode of the second selection transistor and the first channel layer of the first selection transistor. The problem of state damage caused by read operation can be avoided.

Description

Semiconductor device and manufacturing method thereof, and memory system Technical Field

[0001] The present application relates to the field of semiconductor device technology, and in particular to a semiconductor device, a manufacturing method thereof, and a memory system. Background Art

[0002] The transistors in a ferroelectric random access memory (FeRAM) with a one-transistor-one-capacitor (1T1C) or 1TXC (X is an integer greater than 1) architecture have both read and write functions. In FeRAM, a read operation requires a write-back operation, but the read operation is destructive and will destroy the state of the FeRAM.

[0003] Summary of the Invention

[0004] In view of this, the present application provides a semiconductor device, a preparation method thereof, and a memory system that can implement non-destructive read operations and no longer require write-back operations, so as to effectively avoid the state destruction problem caused by read operations.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a semiconductor device, including a first semiconductor structure, wherein the first semiconductor structure includes:

[0007] a first selection transistor including a first channel layer;

[0008] a second selection transistor including a gate; and

[0009] The capacitor structure includes a first electrode layer, wherein two ends of the first electrode layer are respectively connected to the gate of the second selection transistor and the first channel layer of the first selection transistor.

[0010] In some embodiments of the present application, the first selection transistor is configured to be turned on or off according to the written content and allow the write voltage to flow into the capacitor structure through the first selection transistor; the second selection transistor is configured to be turned on or off according to the storage content of the capacitor structure and allow the storage content of the capacitor structure to be read.

[0011] In some embodiments of the present application, the first semiconductor structure further includes:

[0012] a first stacking structure having a first side and a second side disposed opposite to each other in the first direction; the capacitor structure being located in the first stacking structure;

[0013] a second stack structure located on a first side of the first stack structure; the first selection transistor is located in the second stack structure; and

[0014] The third stack structure is located on the second side of the first stack structure; the second selection transistor is located in the third stack structure.

[0015] In some embodiments of the present application, the first stacking structure includes:

[0016] at least one second electrode layer;

[0017] A plurality of first insulating layers; two adjacent first insulating layers are stacked and spaced apart in the first direction via the second electrode layer;

[0018] a plurality of first channel structures, located in a stack formed by the second electrode layer and the first insulating layer along the first direction;

[0019] Wherein, each of the first channel structures includes:

[0020] The first electrode layer extends in the first direction; and

[0021] an energy storage layer extending in the first direction and located between the second electrode layer and the first electrode layer;

[0022] The second electrode layer and the first insulating layer are arranged around the energy storage layer, and the energy storage layer is arranged around the first electrode layer; the capacitor structure includes the second electrode layer, the energy storage layer and the first electrode layer.

[0023] In some embodiments of the present application, the second stacking structure includes:

[0024] a second insulating layer, located on the first side of the first stacked structure;

[0025] a word line located on a side of the second insulating layer away from the first stack structure and extending along a second direction perpendicular to the first direction;

[0026] a third insulating layer, located on a side of the word line away from the second insulating layer; and

[0027] a second channel structure extending along the first direction and located in a stack formed by the second insulating layer, the word line, and the third insulating layer;

[0028] The second channel structure is arranged in a one-to-one correspondence with the first channel structure, and the first selection transistor includes the second channel structure and the word line.

[0029] In some embodiments of the present application, each of the second channel structures includes:

[0030] the first channel layer; one end of the first channel layer is connected to the first electrode layer; and

[0031] The first gate insulating layer is located between the word line and the first channel layer.

[0032] In some embodiments of the present application, the first channel layer includes a first drain, a channel region and a first source. The first drain and the first source are located on opposite sides of the channel region in the first direction. The first source is connected to the first electrode layer.

[0033] In some embodiments of the present application, the first semiconductor structure further includes a first bit line;

[0034] The first bit line extends along a third direction perpendicular to the first direction and intersecting the second direction and is located on a side of the second stack structure away from the first stack structure, and the first drain of the second channel structure is connected to the first bit line.

[0035] In some embodiments of the present application, the third stacking structure includes:

[0036] at least one source line located at the first side of the first stacked structure and extending along a second direction perpendicular to the first direction;

[0037] a fourth insulating layer, located on a side of the source line away from the first stack structure; and

[0038] a third channel structure extending along the first direction and located in a stack formed by the source line and the fourth insulating layer;

[0039] Wherein, the third channel structure and the first channel structure are arranged in a one-to-one correspondence.

[0040] In some embodiments of the present application, the third stacking structure further includes a fifth insulating layer, which is located on a side of the source line close to the first stacking structure, and the gate is located within the source line, the fourth insulating layer and the fifth insulating layer.

[0041] In some embodiments of the present application, each of the third channel structures includes:

[0042] The gate is connected to the first electrode layer;

[0043] a second gate insulating layer, covering the gate;

[0044] a second channel layer, disposed around the second gate insulating layer; and

[0045] a second drain electrode, located on a side of the second gate insulating layer away from the first electrode layer and connected to the second channel layer;

[0046] The source line and the fourth insulating layer are arranged around the second channel layer, and the second selection transistor includes the source line and the third channel structure.

[0047] In some embodiments of the present application, the first semiconductor structure further includes a second bit line;

[0048] The second bit line extends along a third direction perpendicular to the first direction and intersecting the second direction and is located on a side of the third stack structure away from the first stack structure, and the second drain of the third channel structure is connected to the second bit line.

[0049] In some embodiments of the present application, two adjacent source lines are separated by a first spacer, the first spacer is located between two adjacent rows of third channel structures arranged along the second direction and is S-shaped, the first spacer extends along the second direction, and the third stacked structure also includes a first air gap, the first air gap is located within the first spacer and between at least part of the two third channel structures in two adjacent rows, and the first air gap extends along the second direction within the first spacer.

[0050] In some embodiments of the present application, two adjacent word lines are spaced apart by a second spacer, the second spacer is located between two adjacent rows of second channel structures arranged along the second direction and is S-shaped, the second spacer extends along the second direction, the second stack structure also includes a second air gap, the second air gap is located within the second spacer and between at least part of the two second channel structures in the two rows, and the second air gap extends along the second direction within the second spacer.

[0051] In some embodiments of the present application, two adjacent first bit lines are spaced apart, the second stacking structure further includes a sixth insulating layer, the first bit line is located in the sixth insulating layer, the second stacking structure further includes a third air gap, the third air gap is located in the sixth insulating layer and is located between at least partially adjacent two first bit lines, and the third air gap extends along the third direction.

[0052] In some embodiments of the present application, two adjacent second bit lines are spaced apart, the third stacking structure further includes a seventh insulating layer, the second bit line is located in the seventh insulating layer, the third stacking structure further includes a fourth air gap, the fourth air gap is located in the seventh insulating layer and is located between at least partially adjacent two second bit lines, and the fourth air gap extends along the third direction.

[0053] In some embodiments of the present application, the first stacking structure has a plurality of spacing structures extending along a third direction perpendicular to the first direction and intersecting the second direction and spaced apart along the second direction, so as to divide the first semiconductor structure into a plurality of spaced apart storage blocks, each of the storage blocks including at least one first selection transistor, the second selection transistor and the capacitor structure.

[0054] In some embodiments of the present application, the semiconductor device further includes:

[0055] The second semiconductor structure has a circuit element for controlling the first semiconductor structure and is located on one side of the first semiconductor structure; the second semiconductor structure is bonded to the first semiconductor structure in the first direction.

[0056] In some embodiments of the present application, the second semiconductor structure is located on a side of the second stack structure away from the first stack structure or on a side of the third stack structure away from the first stack structure.

[0057] In some embodiments of the present application, the second semiconductor structure further includes an interconnect structure layer, which is located between the first semiconductor structure and the circuit element; the semiconductor device further includes a connecting portion, which is located on one side of the first semiconductor structure and connected to the interconnect structure layer, one of the first selection transistor and the second selection transistor is connected to the interconnect structure layer through a bonding structure, and the other of the first selection transistor and the second selection transistor is connected to the connecting portion.

[0058] The present application also provides a method for preparing a semiconductor device, comprising:

[0059] forming a first stacking structure; the first stacking structure having a first side and a second side disposed opposite to each other in the first direction, the first stacking structure including a capacitor structure; and

[0060] A second stacking structure including a first selection transistor and a third stacking structure including a second selection transistor are formed on the first side and the second side of the first stacking structure respectively, and the first channel layer of the first selection transistor is connected to the capacitor structure, and the gate of the second selection transistor is connected to the capacitor structure.

[0061] In some embodiments of the present application, before the step of forming the first stacked structure, the method further includes: providing a substrate;

[0062] The step of forming a first stacking structure includes: forming the first stacking structure on the substrate;

[0063] Among them, one of the second stacking structure and the third stacking structure is located on a side of the first stacking structure away from the substrate; before forming the other of the second stacking structure and the third stacking structure, the method further includes: removing the substrate.

[0064] In some embodiments of the present application, a stacked structure formed by the first stacked structure, the second stacked structure, and the third stacked structure is defined as a first semiconductor structure;

[0065] After forming one of the second stacking structure and the third stacking structure, the method further includes:

[0066] A second semiconductor structure having circuit elements for controlling the first semiconductor structure is formed on a side of the second stack structure or the third stack structure away from the first stack structure, and the second semiconductor structure is bonded to the first semiconductor structure in the first direction.

[0067] In some embodiments of the present application, the step of forming the first stacked structure includes:

[0068] forming at least one second electrode layer and a plurality of first insulating layers alternately stacked in a first direction;

[0069] opening a first channel hole in a stack formed by the second electrode layer and a plurality of first insulating layers;

[0070] A first electrode layer extending in the first direction and an energy storage layer extending in the first direction and located between the second electrode layer and the first electrode layer are formed in the first channel hole to obtain a first channel structure, and a plurality of the second electrode layers and a plurality of the first insulating layers are arranged around the energy storage layer, and the energy storage layer is arranged around the first electrode layer.

[0071] In some embodiments of the present application, the step of forming a second stack structure including a first selection transistor on the first side of the first stack structure includes:

[0072] forming a second insulating layer, a word line, and a third insulating layer in sequence on the first side of the first stack structure;

[0073] forming a plurality of second channel holes on the second stack structure, penetrating the second insulating layer, the word lines, and the third insulating layer and corresponding one-to-one to the first channel structures; and

[0074] A first channel layer and a first gate insulating layer are formed in sequence in the second channel hole from the center of the second channel hole to the hole wall of the second channel hole, and the first channel layer includes a first drain, a channel region and a first source, so that the first drain and the first source are located on opposite sides of the channel region in the first direction and the first source is connected to the first electrode layer.

[0075] In some embodiments of the present application, after forming a second stack structure including a first selection transistor on the first side of the first stack structure, the method further includes:

[0076] A first bit line is formed on a side of the second stack structure away from the first stack structure, and the first bit line is connected to the first drain.

[0077] In some embodiments of the present application, the step of forming a first bit line on a side of the second stack structure away from the first stack structure and connecting the first bit line to the first drain includes: forming a sixth insulating layer on a side of the second stack structure away from the first stack structure, forming a first bit line in the sixth insulating layer and connecting the first bit line to the first drain;

[0078] After forming a first bit line on a side of the second stack structure away from the first stack structure and connecting the first bit line to the first drain, the method further includes forming a third air gap in the sixth insulating layer, the third air gap being located between two at least partially adjacent first bit lines and extending along a third direction.

[0079] In some embodiments of the present application, the step of forming a third stack structure including a second selection transistor on the second side of the first stack structure includes:

[0080] forming a source line and a fourth insulating layer in sequence on the second side of the first stacked structure;

[0081] forming a plurality of third channel holes on the third stacked structure, penetrating the source lines and the fourth insulating layer and corresponding one-to-one to the first channel structures; and

[0082] The gate, a second gate insulating layer covering the gate, and a second channel layer arranged around the second gate insulating layer are formed in sequence in the third channel hole from the center of the third channel hole to the hole wall of the third channel hole, and a second drain is formed on a side of the second gate insulating layer away from the first electrode layer, so that the gate is connected to the first electrode layer and the second drain is connected to the second channel layer.

[0083] In some embodiments of the present application, after the step of forming a third stack structure including a second selection transistor on the second side of the first stack structure, the method further includes:

[0084] A second bit line is formed on a side of the third stack structure away from the first stack structure, and the second bit line is connected to the second drain of the second selection transistor.

[0085] In some embodiments of the present application, the step of forming a second bit line on a side of the third stack structure away from the first stack structure and connecting the second bit line to the second drain of the second selection transistor includes: forming a seventh insulating layer on a side of the third stack structure away from the first stack structure, forming the second bit line in the seventh insulating layer and connecting the second bit line to the second drain;

[0086] After forming a second bit line on a side of the third stack structure away from the first stack structure and connecting the second bit line to the second drain of the second selection transistor, the method further includes:

[0087] A fourth air gap is formed in the seventh insulating layer and is located between at least partially adjacent two second bit lines and extends along the third direction.

[0088] The present application also provides a memory system, comprising:

[0089] At least one semiconductor device as described above; and

[0090] A controller is configured to control the semiconductor device.

[0091] The semiconductor device, preparation method thereof, and memory system provided by the present application respectively connect a first selection transistor and a second selection transistor on a capacitor structure, and connect the two ends of the first electrode layer of the capacitor structure to the first channel layer of the first selection transistor and the gate of the second selection transistor, respectively. The first selection transistor and the second selection transistor respectively perform write operations and read operations. Therefore, the second selection transistor of the semiconductor device provided by the present application does not require a write-back operation and can implement a non-destructive read operation, thereby effectively avoiding the state destruction problem caused by the read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0093] FIG1A is a circuit diagram of a semiconductor device provided in this application.

[0094] FIG1B is a schematic diagram of the circuit structure of another semiconductor device provided in this application.

[0095] FIG. 2A is a cross-sectional view of the semiconductor device shown in FIG. 1B .

[0096] FIG. 2B is a top view of a bit line of the semiconductor device shown in FIG. 2A .

[0097] FIG. 2C is a schematic diagram illustrating the “0” state and the “1” state of the first selection transistor and the second selection transistor of the semiconductor device shown in FIG. 2A .

[0098] FIG. 3 is a film layer diagram of the circuit structure of the semiconductor device shown in FIG. 1B .

[0099] FIG4 is a cross-sectional view of another semiconductor device provided by the present application.

[0100] FIG. 5 is a schematic diagram illustrating the positional relationship between the third channel structure and the first spacer of the semiconductor device shown in FIG. 4 .

[0101] FIG. 6 is a schematic diagram showing the positional relationship between the second channel structure and the second spacer of the semiconductor device shown in FIG. 4 .

[0102] FIG7 is a cross-sectional view of another semiconductor device provided by the present application.

[0103] FIG8 is a flow chart of a method for preparing a semiconductor device provided in this application.

[0104] FIG. 9 is a flow chart of forming the first stacked structure in step S1 shown in FIG. 8 .

[0105] FIG. 10 is a flow chart of forming the second stacked structure in step S2 shown in FIG. 8 .

[0106] FIG. 11 shows a flow chart of forming the third stacked structure in step S2 .

[0107] FIG12 is a cross-sectional view of a substrate with stacked layers provided in this application.

[0108] FIG. 13 is a cross-sectional view after a first channel hole is formed on the stacked layer shown in FIG. 12 .

[0109] FIG. 14 is a top view of the first channel hole shown in FIG. 13 .

[0110] FIG. 15 is a cross-sectional view after a first channel structure is formed in the first channel hole shown in FIG. 13 .

[0111] FIG16 is an enlarged view of the first channel structure shown in FIG15 .

[0112] FIG. 17 is a cross-sectional view showing the stacked layers shown in FIG. 15 after forming spacer holes.

[0113] FIG. 18 is a top view of the spacing hole and the first channel structure shown in FIG. 17 .

[0114] FIG. 19 is a cross-sectional view showing a first stacked structure obtained by forming a spacing structure in the spacing hole shown in FIG. 17 .

[0115] FIG. 20 is a cross-sectional view of the first stack structure shown in FIG. 19 after a word line is formed at one end away from the substrate.

[0116] FIG. 21 is a cross-sectional view after a second channel hole penetrating the word line is formed on the first stacked structure with the word line shown in FIG. 20 .

[0117] FIG22 is a top view of the second channel hole shown in FIG21 .

[0118] FIG. 23 is a cross-sectional view after a second channel structure is formed in the second channel hole shown in FIG. 21 .

[0119] FIG. 24 is an enlarged view of the second channel structure and the first channel structure shown in FIG. 23 .

[0120] FIG25 is a cross-sectional view of a second stacked structure obtained by forming a first bit line on a side of the second channel structure shown in FIG23 away from the first stacked structure.

[0121] FIG. 26 is a top view of the first bit line shown in FIG. 25 .

[0122] FIG. 27 is a cross-sectional view of the second stack structure shown in FIG. 25 after a second semiconductor structure is formed on a side away from the first stack structure.

[0123] FIG28 is a cross-sectional view after the substrate in FIG27 is removed.

[0124] 29 is a cross-sectional view after a source line is formed on a side of the first stack structure away from the second stack structure in FIG. 28 and a third channel structure penetrating the source line is formed.

[0125] FIG30 is a module diagram of a memory system provided in the present application. DETAILED DESCRIPTION

[0126] The following will be combined with the accompanying drawings of some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0127] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0128] In the description of this application, it is understood that the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned.

[0129] In the description of the present application, it is to be understood that the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0130] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0131] The present application addresses the technical problem that the selection transistor in the ferroelectric memory of the 1T1C or 1TXC (X is an integer greater than 1) architecture requires a write-back operation after the read operation, and the read operation is destructive and will destroy the state of the FeRAM. By respectively connecting the first selection transistor and the second selection transistor on the capacitor structure, and making the two ends of the first electrode layer of the capacitor structure connected to the first channel layer of the first selection transistor and the gate of the second selection transistor respectively, the first selection transistor and the second selection transistor respectively perform a write operation and a read operation, so that the second selection transistor of the semiconductor device provided by the present application does not require a write-back operation and can realize a non-destructive read operation, thereby effectively avoiding the state destruction problem caused by the read operation.

[0132] Referring to Figures 1A, 1B, 2A, 2B, 2C, and 3, some embodiments of the present application provide a semiconductor device 1000, comprising a first semiconductor structure 100. The first semiconductor structure 100 comprises a first selection transistor 101, a second selection transistor 102, and a capacitor structure 103. The first selection transistor 101 and the second selection transistor 102 are respectively connected to the capacitor structure 103. The first selection transistor 101 comprises a first channel layer 41, the second selection transistor 102 comprises a gate 61, and the capacitor structure 103 comprises a first electrode layer 22, with two ends of the first electrode layer 22 respectively connected to the gate 61 of the second selection transistor 102 and the first channel layer 41 of the first selection transistor 101.

[0133] Among them, the first selection transistor 101 is configured to be conductive or non-conductive according to the written content and allow the write voltage to flow into the capacitor structure 103 through the first selection transistor 101; the second selection transistor 102 is configured to be conductive or non-conductive according to the storage content of the capacitor structure 103 and allow the storage content of the capacitor structure 103 to be read. Specifically, when there is a write voltage written, the first selection transistor 101 is turned on, and the write voltage flows into the capacitor structure 103 through the first selection transistor 101 to achieve the write function. When it is necessary to read the storage content of the capacitor structure 103, the second selection transistor 102 is turned on to achieve the read function.

[0134] Please refer to FIG. 1A and FIG. 1B again. The positions of the first selection transistor 101 and the second selection transistor 102 can be changed and are not limited to the positions shown in FIG. 1A or FIG. 1B .

[0135] The semiconductor device provided by the present application connects the first selection transistor 101 and the second selection transistor 102 at both ends of the capacitor structure 103, and connects the two ends of the first electrode layer 22 of the capacitor structure 103 to the first channel layer 41 of the first selection transistor 101 and the gate 61 of the second selection transistor 102, respectively. The first selection transistor 101 and the second selection transistor 102 perform write operations and read operations respectively, so that the second selection transistor 102 of the semiconductor device provided by the present application does not require a write-back operation and can implement a non-destructive read operation, thereby effectively avoiding the state destruction problem caused by the read operation.

[0136] Please refer to Figure 2A again. The first semiconductor structure 100 also includes a first stacking structure 110, a second stacking structure 120 and a third stacking structure 130. The first stacking structure 110 has a first side 111 and a second side 112 arranged opposite to each other in the first direction Z. The capacitor structure 103 is located in the first stacking structure 110; the second stacking structure 120 is located on the first side 111 of the first stacking structure 110, and the first selection transistor 101 is located in the second stacking structure 120; the third stacking structure 130 is located on the second side 112 of the first stacking structure 110, and the second selection transistor 102 is located in the third stacking structure 130.

[0137] Specifically, the first stacking structure 110 includes at least one second electrode layer 11, multiple first insulating layers 12 and multiple first channel structures 20. Any second electrode layer 11 is located between two adjacent first insulating layers 12, and the first channel structure 20 is located along the first direction Z in the stack formed by the second electrode layer 11 and the first insulating layer 12.

[0138] The second electrode layer 11 is made of conductive materials, such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium. In this embodiment, the second electrode layer 11 is made of polycrystalline silicon.

[0139] The first insulating layer 12 is made of an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. In this embodiment, the first insulating layer 12 is made of silicon oxide.

[0140] In this embodiment, the first stacked structure 110 includes a plurality of second electrode layers 11 and a plurality of first insulating layers 12, where the number of first insulating layers 12 is one less than the number of second electrode layers 11. In other embodiments, the first stacked structure 110 may also include one second electrode layer 11 and two first insulating layers 12.

[0141] Each first channel structure 20 includes a first electrode layer 22 extending in a first direction Z and an energy storage layer 21 extending in the first direction Z and located between the second electrode layer 11 and the first electrode layer 22. The second electrode layer 11 and the first insulating layer 12 are arranged around the energy storage layer 21, and the energy storage layer 21 is arranged around the first electrode layer 22. The capacitor structure 103 includes the second electrode layer 11, the energy storage layer 21, and the first electrode layer 22.

[0142] In this embodiment, the constituent materials of the energy storage layer 21 include: ferroelectric materials or antiferroelectric materials. Among them, ferroelectric materials have two or more possible orientations of spontaneous polarization phenomena at a finite temperature, and the orientation of this spontaneous polarization can be changed under the action of an electric field. The ions inside the lattice of the antiferroelectric material will undergo spontaneous polarization similar to that of the ferroelectric material, but unlike the ferroelectric material, the adjacent lattices inside the antiferroelectric material have spontaneous polarizations in opposite directions. For example, the constituent materials of the energy storage layer 21 can be selected from hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Si a (HfO2) b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped hafnium dioxide (Zr a (HfO2) b ) or zirconium oxide (ZrO), etc. Here, a and b are positive numbers. The energy storage layer 21 can be formed by a thin film deposition process, etc. In other embodiments, the material of the energy storage layer 21 is not limited to ferroelectric materials or antiferroelectric materials, and can be set and adjusted according to actual needs.

[0143] The first electrode layer 22 is formed of a conductive material, such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, or ruthenium. In this embodiment, the second electrode layer 11 is formed of tungsten. The first electrode layer 22 can be formed by a thin film deposition process.

[0144] In this embodiment, a plurality of first channel structures 20 form a group, and the first stacked structure 110 is divided into a plurality of channel structure groups.

[0145] An XYZ coordinate system is established with a first direction Z, a second direction X perpendicular to the first direction Z, and a third direction Y perpendicular to the first direction Z and the second direction X. The first direction Z is the stacking direction of the second electrode layer 11 and the first insulating layer 12 .

[0146] The first stacked structure 110 includes a plurality of spacer structures 15 extending along the third direction Y and spaced apart along the second direction X, thereby dividing the first semiconductor structure 100 into a plurality of spaced apart memory blocks. Each memory block includes at least one first select transistor 101, a second select transistor 102, and a capacitor structure 103. A spacer structure 15 is located between two adjacent channel structure groups.

[0147] Among them, the spacing structure 15 is used to separate two adjacent channel structure groups. The spacing structure 15 includes insulating material, which may include at least one of silicon oxide, silicon oxynitride, ethoxysilane, low-temperature oxide, high-temperature oxide, and silicon nitride. The present disclosure is not limited thereto.

[0148] The second stacked structure 120 includes a second insulating layer 31, a word line 32, a third insulating layer 33, and a second channel structure 40. The second insulating layer 31 is located on the first side 111 of the first stacked structure 110. The word line 32 is located on a side of the second insulating layer 31 away from the first stacked structure 110 and extends along the second direction X. The third insulating layer 33 is located on a side of the word line 32 away from the second insulating layer 31. The second channel structure 40 extends along the first direction Z and is located within the stack formed by the second insulating layer 31, the word line 32, and the third insulating layer 33. The second channel structure 40 is provided in a one-to-one correspondence with the first channel structure 20, and the first selection transistor 101 includes the second channel structure 40 and the word line 32. That is, the orthographic projection of the second channel structure 40 on the first side 111 of the first stacked structure 110 at least partially overlaps with the first channel structure 20.

[0149] Referring again to FIG. 3 , each second channel structure 40 includes a first channel layer 41 and a first gate insulating layer 42. One end of the first channel layer 41 is connected to the first electrode layer 22, and the first gate insulating layer 42 is located between the word line 32 and the first channel layer 41. In other words, the word line 32 surrounds each second channel structure 40. The second channel structure 40 and the word line 32 together form a gate transistor.

[0150] Specifically, the first channel layer 41 includes a first drain 411, a channel region 412, and a first source 413. The first drain 411 and the first source 413 are located on opposite sides of the first channel region 412 in the first direction Z. The first source 413 is connected to the first electrode layer 22. The word line 32 is opposite to the first channel region 412, that is, the word line 32 faces the first channel region 412 from all directions. The second channel structure 40 cooperates with the word line 32 to form a gate transistor. The word line 32 controls the conduction and cutoff of the gate transistor. The control signal enters the gate transistor from the word line 32 to control the conduction and cutoff of the gate transistor. The signal enters the first electrode layer 22 through the first source 413, and a voltage difference is generated between the first electrode layer 22 and the second electrode layer 11, forming an electric field.

[0151] 2A and 3 again, the first semiconductor structure 100 further includes a first bit line 37. The first bit line 37 extends along the third direction Y and is located on a side of the second stacked structure 120 away from the first stacked structure 110. The first drain 411 of the second channel structure 40 is connected to the first bit line 37. The first bit line 37 is used to write the stored state of the basic cell.

[0152] Specifically, the first semiconductor structure 100 further includes a sixth insulating layer 35, which is located on a side of the second stacked structure 120 away from the first stacked structure 110. The first bit line 37 is located within the sixth insulating layer 35. One first bit line 37 is located opposite to and connected to one second channel structure 40. Specifically, one first bit line 37 is connected to the first source 413 via one first connector 36.

[0153] Referring again to Figures 2A, 2B, and 3, the third stacked structure 130 includes at least one source line 52, a fourth insulating layer 53, and a third channel structure 60. The source line 52 is located on a first side of the first stacked structure 110 and extends along the second direction X. The fourth insulating layer 53 is located on a side of the source line 52 away from the first stacked structure 110. The third channel structure 60 extends along the first direction Z and is located within the stack formed by the source line 52 and the fourth insulating layer 53. The third channel structure 60 is disposed in a one-to-one correspondence with the first channel structure 20. That is, the orthographic projection of the third channel structure 60 on the second side 112 of the first stacked structure 110 at least partially overlaps with the first channel structure 20.

[0154] The third stacked structure 130 further includes a fifth insulating layer 51 , which is located on a side of the source line 52 close to the first stacked structure 110 . The gate 61 is located within the source line 52 , the fourth insulating layer 53 and the fifth insulating layer 51 .

[0155] In which, each third channel structure 60 includes a gate 61 connected to the first electrode layer 22, a second gate insulating layer 63, a second channel layer 62 and a second drain 64, the second gate insulating layer 63 covers the gate 61, the second channel layer 62 is arranged around the second gate insulating layer 63, and the second drain 64 is located on the side of the second gate insulating layer 63 away from the first electrode layer 22 and is connected to the second channel layer 62, wherein the source line 52 and the fourth insulating layer 53 are arranged around the second channel layer 62, and the second selection transistor 102 includes the source line 52 and the third channel structure 60.

[0156] The first semiconductor structure 100 further includes a second bit line 57, which extends along the third direction X and is located on a side of the third stacked structure 130 away from the first stacked structure 110. The second drain 64 of the third channel structure 60 is connected to the second bit line 57. The second bit line 57 is used to read the current state stored in the basic cell.

[0157] Referring again to FIG. 2C , the second select transistor 102 has different current states: a "0" state and a "1" state, depending on its gate voltage. When the gate voltage of the second select transistor 102 is low, the state read from the second bit line 57 is a "0" state. When the gate voltage of the second select transistor 102 is high, the state read from the second bit line 57 is a "1" state.

[0158] Specifically, the first semiconductor structure 100 further includes a seventh insulating layer 55, which is located on a side of the third stacked structure 130 away from the first stacked structure 110. A second bit line 57 is located within the seventh insulating layer 55. One second bit line 57 is located opposite to and connected to one third channel structure 60. Specifically, one second bit line 57 is connected to the second drain 64 via a second connector 56.

[0159] Specifically, the first semiconductor structure 100 further includes a protection layer 59 , which is located on a side of the second bit line 57 away from the third channel structure 60 and covers the second bit line 57 and the seventh insulating layer 55 . The protection layer 59 is used to protect the second bit line 57 .

[0160] Specifically, the first semiconductor structure 100 further includes a first bonding layer 38 , and the first bonding layer 38 includes a plurality of first bonding structures 381 .

[0161] 2A again, the semiconductor device 1000 further includes a second semiconductor structure 200 . The second semiconductor structure 200 has a circuit element 210 for controlling the first semiconductor structure 100 and is located on one side of the first semiconductor structure 100 . The second semiconductor structure 200 is bonded to the first semiconductor structure 100 in the first direction Z.

[0162] The circuit element 210 may be at least one of a resistor, a capacitor, and a CMOS transistor, or any combination thereof. In this embodiment, the circuit element 210 is a CMOS transistor.

[0163] Specifically, the second semiconductor structure 200 is located on a side of the second stack structure 120 away from the first stack structure 110 or on a side of the third stack structure 130 away from the first stack structure 110. In this embodiment, the second semiconductor structure 200 is located on a side of the second stack structure 120 away from the first stack structure 110.

[0164] Specifically, the second semiconductor structure 200 also includes a second bonding layer 230, which includes a plurality of second bonding structures 231 and is connected to the circuit element 210. The second bonding layer 230 is bonded to the first bonding layer 38, and the second bonding structure 231 is bonded to the first bonding structure 381. In some embodiments of the present application, the second bonding layer 230 and the first bonding structure 381 are bonded by covalent bonding, and the second bonding structure 231 and the first bonding structure 381 are bonded by metal bonding. In other embodiments, the bonding method between the second bonding layer 230 and the first bonding structure 381 is not limited to covalent bonding, and the bonding method between the second bonding structure 231 and the first bonding structure 381 is not limited to metal bonding.

[0165] Specifically, the second semiconductor structure 200 further includes an interconnect structure layer 220, which is located between the second bonding layer 230 and the circuit element 210 and is connected to the circuit element 210. The semiconductor device 1000 further includes a connecting portion 58, which is located on a side of the first semiconductor structure 100 and is connected to the interconnect structure layer 220. One of the first selection transistor 101 and the second selection transistor 102 is connected to the interconnect structure layer 220 via the first bonding structure 381 and the second bonding structure 231, and the other of the first selection transistor 101 and the second selection transistor 102 is connected to the connecting portion 58.

[0166] Of course, in other embodiments of the present application, the semiconductor device 1000 may not include the second semiconductor structure 200 .

[0167] The semiconductor device 1000 provided in the present application connects a first selection transistor and a second selection transistor on a capacitor structure, respectively, and connects the two ends of the first electrode layer of the capacitor structure to the first channel layer of the first selection transistor and the gate of the second selection transistor, respectively. The first selection transistor and the second selection transistor respectively perform write operations and read operations. Therefore, the second selection transistor of the semiconductor device provided in the present application does not require a write-back operation and can implement a non-destructive read operation, thereby effectively avoiding the state destruction problem caused by the read operation.

[0168] Referring to Figures 4 to 6, the present application also provides a semiconductor device 2000. The structure of the semiconductor device 2000 is similar to that of the semiconductor device 1000, except that: the third stacked structure 130 of the semiconductor device 2000 further includes a first spacer 71, and two adjacent source lines 52 are spaced apart by the first spacer 71. The first spacer 71 is located between two adjacent rows of third channel structures 60 arranged along the second direction X and is S-shaped. The first spacer 71 extends along the second direction X. The third stacked structure 130 further includes a first air gap 72. The first air gap 72 is located within the first spacer 71 and between at least part of the two third channel structures 60 in two adjacent rows. The first air gap 72 extends along the second direction X within the first spacer 71. The second stacked structure 120 of the semiconductor device 2000 also includes a second spacer 73, which is used to space two adjacent word lines 32. The second spacer 73 is located between two adjacent rows of second channel structures 40 arranged along the second direction X and is S-shaped. The second spacer 73 extends along the second direction X. The second stacked structure 120 also includes a second air gap 74. The second air gap 74 is located within the second spacer 73 and between at least part of the two second channel structures 40 in the two rows. The second air gap 74 extends along the second direction X within the second spacer 73.

[0169] Of course, the semiconductor device 2000 may also include at least one of the first air gap 72 and the second air gap 74 .

[0170] Air exists between the first air gap 72 and the second air gap 74. Air is the insulating medium with the lowest dielectric constant in nature, with a dielectric constant of 1. Using air gaps as the dielectric layer between adjacent second channel structures 40 can minimize the RC delay between the channel structures. Therefore, the second air gap 74 can reduce the coupling capacitance between adjacent second channel structures 40, and the first air gap 72 can reduce the coupling capacitance between adjacent third channel structures 60. This allows the RC delay requirements to be met even after the size of the semiconductor device 2000 is reduced.

[0171] Referring to FIG. 7 , the present application further provides a semiconductor device 3000 . The structure of semiconductor device 3000 is similar to that of semiconductor device 1000 , except that the second stacked structure 120 of semiconductor device 3000 further includes a third air gap 75 . The third air gap 75 is located within the sixth insulating layer 35 and between at least partially adjacent first bit lines 37 . The third air gap 75 extends along a third direction Y. The third stacked structure 130 of semiconductor device 3000 further includes a fourth air gap 76 . The fourth air gap 76 is located within the seventh insulating layer 55 and between at least partially adjacent second bit lines 57 . The fourth air gap 76 extends along the third direction Y.

[0172] Of course, the semiconductor device 3000 may also include at least one of the third air gap 75 and the fourth air gap 76 .

[0173] There is air between the third air gap 75 and the fourth air gap 76. Air is the insulating medium with the lowest dielectric constant in nature, with a dielectric constant of 1. Using air gaps as the dielectric layer between adjacent bit lines minimizes the RC delay between the bit lines. Therefore, the third air gap 75 can reduce the coupling capacitance between adjacent first bit lines 37, and the fourth air gap 76 can reduce the coupling capacitance between adjacent second bit lines 57. This allows the RC delay requirements to be met even after the size of the semiconductor device 3000 is reduced.

[0174] Referring to FIG. 8 to FIG. 30 , the present application further provides a method for manufacturing a semiconductor device, comprising:

[0175] Step S1: forming a first stacked structure 110; wherein the first stacked structure 110 has a first side 111 and a second side 112 disposed opposite to each other in a first direction Z, and the first stacked structure 110 includes a capacitor structure 103; and

[0176] Step S2: A second stacking structure 120 including a first selection transistor 101 and a third stacking structure 130 including a second selection transistor 102 are respectively formed on the first side 111 and the second side 112 of the first stacking structure 110, and the first channel layer 41 of the first selection transistor 101 is connected to the capacitor structure 103, and the gate 61 of the second selection transistor 102 is connected to the capacitor structure 103.

[0177] In which, the stacked structure formed by the first stacking structure 110, the second stacking structure 120 and the third stacking structure 130 is defined as the first semiconductor structure 100; the preparation method of the semiconductor device also includes step S3: forming a second semiconductor structure 200 having a circuit element 210 for controlling the first semiconductor structure 100 on a side of the second stacking structure 120 or the third stacking structure 130 away from the first stacking structure 110, and bonding the second semiconductor structure 200 to the first semiconductor structure 100 in the first direction Z.

[0178] In some embodiments of the present application, step S3 is located after step S2.

[0179] In some embodiments of the present application, the second stacking structure 120 and the third stacking structure 130 in step S2 are formed successively. After the step of forming the second stacking structure 120, step S3 is performed to form a second semiconductor structure 200 on the side of the second stacking structure 120 away from the first stacking structure 110, and then the third stacking structure 130 is formed on the side of the first stacking structure 110 away from the second stacking structure 120; or after the step of forming the third stacking structure 130, step S3 is performed to form a second semiconductor structure 200 on the side of the third stacking structure 130 away from the first stacking structure 110, and then the second stacking structure 120 is formed on the side of the first stacking structure 110 away from the third stacking structure 130.

[0180] Referring to Figures 12, 27, and 28, in some embodiments of the present application, before step S1, the step of providing a substrate 104 is further included. Accordingly, step S1 includes forming a first stacked structure 110 on the substrate 104. One of the second stacked structure 120 and the third stacked structure 130 is located on a side of the first stacked structure 110 away from the substrate 104. Before forming the other of the second stacked structure and the third stacked structure, the step of removing the substrate 104 is further included. Specifically, the step of removing the substrate 104 is located before step S3.

[0181] The substrate 104 may include single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials.

[0182] Referring to FIG. 9 and FIG. 12 to FIG. 15 , step S1 includes:

[0183] Please refer to FIG. 12 , step S11 : forming at least one second electrode layer 11 and a plurality of first insulating layers 12 stacked in a first direction Z such that any second electrode layer 11 is located between two adjacent first insulating layers 12 .

[0184] 13 and 14 , step S12: opening a first channel hole 13 on the stack formed by the second electrode layer 11 and the plurality of first insulating layers 12.

[0185] Please refer to Figures 15 and 16, step S13: a first electrode layer 22 extending in the first direction Z and a storage layer 21 extending in the first direction Z and located between the second electrode layer 11 and the first electrode layer 22 are formed in the first channel hole 13 to obtain a first channel structure 20, and multiple second electrode layers 11 and multiple first insulating layers 12 are arranged around the storage layer 21, and the storage layer 21 is arranged around the first electrode layer 22.

[0186] The second electrode layer 11 is made of conductive materials, such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium. In this embodiment, the second electrode layer 11 is made of polycrystalline silicon.

[0187] The first insulating layer 12 is made of an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. In this embodiment, the first insulating layer 12 is made of silicon oxide.

[0188] In this embodiment, the constituent materials of the energy storage layer 21 include: ferroelectric materials or antiferroelectric materials. Among them, ferroelectric materials have two or more possible orientations of spontaneous polarization phenomena at a finite temperature, and the orientation of this spontaneous polarization can be changed under the action of an electric field. The ions inside the lattice of the antiferroelectric material will undergo spontaneous polarization similar to that of the ferroelectric material, but unlike the ferroelectric material, the adjacent lattices inside the antiferroelectric material have spontaneous polarizations in opposite directions. For example, the constituent materials of the energy storage layer 21 can be selected from hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Si a (HfO2) b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped hafnium dioxide (Zr a (HfO2) b ) or zirconium oxide (ZrO), etc. Here, a and b are positive numbers. The energy storage layer 21 can be formed by a thin film deposition process, etc. In other embodiments, the material of the energy storage layer 21 is not limited to ferroelectric materials or antiferroelectric materials, and can be set and adjusted according to actual needs.

[0189] The first electrode layer 22 is formed of a conductive material, such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, or ruthenium. In this embodiment, the second electrode layer 11 is formed of tungsten. The first electrode layer 22 can be formed by a thin film deposition process.

[0190] Referring to Figures 17 to 19, after step S13, step S1 also includes the steps of forming a plurality of spacing structure holes 14 extending along the third direction Y and spaced apart along the second direction X in the second electrode layer 11 and the first insulating layer 12, and filling the spacing structure holes 14 with an insulating spacing material to form a spacing structure 15 located in the second electrode layer 11 and the first insulating layer 12.

[0191] 10 and 20 to 23 , the step of “forming a second stack structure 120 including the first selection transistor 101 on the first side 111 of the first stack structure 110 ” in step S2 includes:

[0192] Please refer to FIG. 20 , step S21 : a second insulating layer 31 , a word line 32 and a third insulating layer 33 are sequentially formed on the first side 111 of the first stack structure 110 .

[0193] 21 and 22 , step S22 : forming a plurality of second channel holes 34 on the second stacked structure 120 , penetrating the second insulating layer 31 , the word lines 32 and the third insulating layer 33 and corresponding to the first channel structures 20 .

[0194] 23 and 24 , step S23: forming a first channel layer 41 and a first gate insulating layer 42 in the second channel hole 34 from the center of the second channel hole 34 toward the wall of the second channel hole 34 in sequence, and making the first channel layer 41 include a first drain 411, a channel region 412, and a first source 413, so that the first drain 411 and the first source 413 are located on opposite sides of the channel region 412 in the first direction Z, and the first source 413 is connected to the first electrode layer 22.

[0195] Please refer to FIG. 25 , step S24 : forming a first bit line 37 on a side of the second stack structure 120 away from the first stack structure 110 , and connecting the first bit line 37 to the first drain 411 .

[0196] Please refer to Figure 4. In some embodiments of the present application, after step S23, the following steps are further included: forming a second spacing hole 731 penetrating the second stacking structure 120 on the second stacking structure 120, filling the second spacing hole 731 with spacing material to obtain a second spacer 73, and forming a second air gap 74 in the second spacer 73.

[0197] 5 , step S24 includes forming a sixth insulating layer 35 on a side of the second stack structure 120 away from the first stack structure 110 , and forming a first bit line 37 in the sixth insulating layer 35 and connecting the first bit line 37 to the first drain 411 .

[0198] Please refer to FIG. 5 . In some embodiments of the present application, after step S24 , a further step is included: forming a third air gap 75 between at least partially adjacent two first bit lines 37 and extending along a third direction Y in the sixth insulating layer 35 .

[0199] 11 , 29 and 2A , the step of “forming a third stack structure 130 including the second selection transistor 102 on the second side 112 of the first stack structure 110 ” in step S2 includes:

[0200] Please refer to FIG. 29 , step S25 : forming a source line 52 and a fourth insulating layer 53 in sequence on the second side 112 of the first stacked structure 110 .

[0201] Please refer to FIG. 29 , step S26 : forming a plurality of third channel holes 54 on the third stacked structure 130 , penetrating the source lines 52 and the fourth insulating layer 53 and corresponding one-to-one to the first channel structures 20 .

[0202] Please refer to FIG. 29 , step S27: a gate electrode 61, a second gate insulating layer 63 covering the gate electrode 61, and a second channel layer 62 disposed around the second gate insulating layer 63 are sequentially formed in the third channel hole 54 from the center of the third channel hole 54 to the wall of the third channel hole 54. A second drain electrode 64 is formed on a side of the second gate insulating layer 63 away from the first electrode layer 22, and the gate electrode 61 is connected to the first electrode layer 22 and the second drain electrode 64 is connected to the second channel layer 62.

[0203] Please refer to FIG. 2A , step S28 : forming a second bit line 57 on a side of the third stack structure 130 away from the first stack structure 110 , and connecting the second bit line 57 to the second drain 64 of the second selection transistor 102 .

[0204] Please refer to Figure 4. In some embodiments of the present application, after step S27, the following steps are further included: forming a first spacing hole 711 penetrating the third stacking structure 130 on the third stacking structure 130, filling the first spacing hole 711 with spacing material to obtain a first spacer 71, and forming a first air gap 72 in the first spacer 71.

[0205] Please refer to Figure 4. In some embodiments of the present application, after step S27, the following steps are further included: forming a first spacing hole 711 penetrating the third stacking structure 130 on the third stacking structure 130, filling the first spacing hole 711 with spacing material to obtain a first spacer 71, and forming a first air gap 72 in the first spacer 71.

[0206] 5 , step S28 includes forming a seventh insulating layer 55 on a side of the third stack structure 130 away from the first stack structure 110 , and forming a second bit line 57 in the seventh insulating layer 55 and connecting the second bit line 57 to the second drain 64 .

[0207] Please refer to FIG. 5 . In some embodiments of the present application, after step S28 , a further step is included: forming a fourth air gap in the seventh insulating layer 55 between at least partially adjacent two second bit lines 57 and extending along the third direction Y.

[0208] 1A and 2A , specifically, the second semiconductor structure 200 further includes an interconnect structure layer 220, which is located between the second bonding layer 230 and the circuit element 210 and connected to the circuit element 210. After step S28, the process further includes forming a connecting portion 58, such that the connecting portion 58 is located on one side of the first semiconductor structure 100 and connected to the interconnect structure layer 220. One of the first selection transistor 101 and the second selection transistor 102 is connected to the interconnect structure layer 220 via the first bonding structure 381 and the second bonding structure 231, and the other of the first selection transistor 101 and the second selection transistor 102 is connected to the connecting portion 58.

[0209] Referring to FIG. 30 , the present application further provides a memory system 1100 , which includes one or more semiconductor devices 1000 / 2000 / 3000 and a controller 4000 as described above. The controller 4000 is connected to the semiconductor devices 1000 / 2000 / 3000 , and the controller 4000 is configured to control the semiconductor devices 1000 / 2000 / 3000 .

[0210] The memory system 1100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller may be configured to control operations of the semiconductor device, such as read, erase, and program operations.

[0211] In some embodiments, the controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0212] In some embodiments, the controller is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0213] The semiconductor device, preparation method thereof, and memory system provided by the present application respectively connect a first selection transistor and a second selection transistor on a capacitor structure, and connect the two ends of the first electrode layer of the capacitor structure to the first channel layer of the first selection transistor and the gate of the second selection transistor, respectively. The first selection transistor and the second selection transistor respectively perform write operations and read operations. Therefore, the second selection transistor of the semiconductor device provided by the present application does not require a write-back operation and can implement a non-destructive read operation, thereby effectively avoiding the state destruction problem caused by the read operation.

[0214] In addition, air is present between the first, second, third, and fourth air gaps. Air is the insulating medium with the lowest dielectric constant in nature, with a dielectric constant of 1. Using air gaps as the dielectric layer between adjacent second or third channel structures or first or second bit lines can minimize the resistance-capacitance delay between adjacent channel structures or adjacent bit lines.

[0215] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A semiconductor device comprising a first semiconductor structure, characterized in that: The first semiconductor structure comprises: a first selection transistor including a first channel layer; A second selection transistor including a gate; and The capacitor structure includes a first electrode layer; two ends of the first electrode layer are respectively connected to the gate of the second selection transistor and the first channel layer of the first selection transistor.

2. The semiconductor device according to claim 1, wherein The first selection transistor is configured to be turned on or off according to the written content and allow the write voltage to flow into the capacitor structure through the first selection transistor; the second selection transistor is configured to be turned on or off according to the storage content of the capacitor structure and allow the storage content of the capacitor structure to be read.

3. The semiconductor device according to claim 1, wherein The first semiconductor structure further comprises: A first stacking structure having a first side and a second side disposed opposite to each other in a first direction; the capacitor structure is located in the first stacking structure; A second stack structure is located at a first side of the first stack structure; the first selection transistor is located in the second stack structure; and The third stack structure is located at the second side of the first stack structure; the second selection transistor is located in the third stack structure.

4. The semiconductor device according to claim 3, wherein: The first stacking structure comprises: at least one second electrode layer; A plurality of first insulating layers; any one of the second electrode layers is located between two adjacent first insulating layers; a plurality of first channel structures, located in a stack formed by the second electrode layer and the first insulating layer along the first direction; Wherein, each of the first channel structures comprises: The first electrode layer extends in the first direction; and an energy storage layer extending in the first direction and located between the second electrode layer and the first electrode layer; The second electrode layer and the first insulating layer are arranged around the energy storage layer, and the energy storage layer is arranged around the first electrode layer; the capacitor structure includes the second electrode layer, the energy storage layer and the first electrode layer.

5. The semiconductor device according to claim 4, wherein: The second stacking structure comprises: a second insulating layer, located on the first side of the first stacked structure; A word line, located at a side of the second insulating layer away from the first stacked structure and extending along a second direction perpendicular to the first direction; A third insulating layer is located on a side of the word line away from the second insulating layer; and A second channel structure extending along the first direction and located in a stack formed by the second insulating layer, the word line and the third insulating layer; The second channel structure is arranged in a one-to-one correspondence with the first channel structure, and the first selection transistor includes the second channel structure and the word line.

6. The semiconductor device according to claim 5, characterized in that Each of the second channel structures comprises: the first channel layer; one end of the first channel layer is connected to the first electrode layer; and The first gate insulating layer is located between the word line and the first channel layer.

7. The semiconductor device according to claim 6, wherein: The first channel layer includes a first drain, a channel region and a first source. The first drain and the first source are located at two opposite sides of the channel region in the first direction. The first source is connected to the first electrode layer.

8. The semiconductor device according to claim 7, wherein: The first semiconductor structure further includes a first bit line; The first bit line extends along a third direction perpendicular to the first direction and crossing the second direction and is located on a side of the second stack structure away from the first stack structure, and the first drain of the second channel structure is connected to the first bit line.

9. The semiconductor device according to any one of claims 4 to 8, characterized in that: The third stacking structure comprises: at least one source line, located at the first side of the first stacked structure and extending along a second direction perpendicular to the first direction; a fourth insulating layer, located on a side of the source line away from the first stacked structure; and a third channel structure extending along the first direction and located in a stack formed by the source line and the fourth insulating layer; Wherein, the third channel structure is arranged in one-to-one correspondence with the first channel structure.

10. The semiconductor device according to claim 9, wherein: The third stacking structure further includes a fifth insulating layer, the fifth insulating layer is located on a side of the source line close to the first stacking structure, and the gate is located within the source line, the fourth insulating layer and the fifth insulating layer.

11. The semiconductor device according to claim 10, wherein: Each of the third channel structures comprises: The gate is connected to the first electrode layer; A second gate insulating layer covering the gate; a second channel layer, disposed around the second gate insulating layer; and A second drain electrode is located on a side of the second gate insulating layer away from the first electrode layer and connected to the second channel layer; The source line and the fourth insulating layer are arranged around the second channel layer, and the second selection transistor includes the source line and the third channel structure.

12. The semiconductor device according to claim 11, wherein The first semiconductor structure further includes a second bit line; The second bit line extends along a third direction perpendicular to the first direction and crossing the second direction and is located on a side of the third stack structure away from the first stack structure, and the second drain of the third channel structure is connected to the second bit line.

13. The semiconductor device according to claim 9, wherein: Two adjacent source lines are spaced apart by a first spacer, the first spacer is located between two adjacent rows of third channel structures arranged along the second direction and is S-shaped, the first spacer extends along the second direction, the third stacking structure also includes a first air gap, the first air gap is located in the first spacer and between at least part of two third channel structures in two adjacent rows, and the first air gap extends along the second direction in the first spacer.

14. The semiconductor device according to claim 5, wherein: Two adjacent word lines are spaced apart by a second spacer, the second spacer is located between two adjacent rows of second channel structures arranged along the second direction and is S-shaped, the second spacer extends along the second direction, the second stacking structure also includes a second air gap, the second air gap is located in the second spacer and between at least part of two second channel structures in two rows, and the second air gap extends along the second direction in the second spacer.

15. The semiconductor device according to claim 8, wherein Two adjacent first bit lines are spaced apart, the second stacking structure further includes a sixth insulating layer, the first bit line is located in the sixth insulating layer, the second stacking structure further includes a third air gap, the third air gap is located in the sixth insulating layer and is located between at least partially adjacent two first bit lines, and the third air gap extends along the third direction.

16. The semiconductor device according to claim 10, wherein: Two adjacent second bit lines are spaced apart, the third stacking structure further includes a seventh insulating layer, the second bit line is located in the seventh insulating layer, the third stacking structure further includes a fourth air gap, the fourth air gap is located in the seventh insulating layer and is located between at least partially adjacent two second bit lines, and the fourth air gap extends along the third direction.

17. The semiconductor device according to claim 3, wherein: The first stacking structure has a plurality of spacing structures extending along a third direction perpendicular to the first direction and intersecting the second direction and spaced apart along the second direction, so as to divide the first semiconductor structure into a plurality of spaced apart storage blocks, each of the storage blocks including at least one of the first selection transistors, the second selection transistor and the capacitor structure.

18. The semiconductor device according to claim 3, wherein: The semiconductor device further comprises: The second semiconductor structure has a circuit element for controlling the first semiconductor structure and is located at one side of the first semiconductor structure; the second semiconductor structure is bonded to the first semiconductor structure in the first direction.

19. The semiconductor device according to claim 18, wherein: The second semiconductor structure is located on a side of the second stack structure away from the first stack structure or on a side of the third stack structure away from the first stack structure.

20. The semiconductor device according to claim 18, wherein The second semiconductor structure also includes an interconnect structure layer, which is located between the first semiconductor structure and the circuit element; the semiconductor device also includes a connecting portion, which is located on one side of the first semiconductor structure and connected to the interconnect structure layer, one of the first selection transistor and the second selection transistor is connected to the interconnect structure layer through a bonding structure, and the other of the first selection transistor and the second selection transistor is connected to the connecting portion.

21. A method for preparing a semiconductor device, characterized in that: include: forming a first stacking structure; The first stacked structure has a first side and a second side disposed opposite to each other in the first direction, and the first stacked structure includes a capacitor structure; and A second stacking structure including a first selection transistor and a third stacking structure including a second selection transistor are respectively formed on the first side and the second side of the first stacking structure, and the first channel layer of the first selection transistor is connected to the capacitor structure, and the gate of the second selection transistor is connected to the capacitor structure.

22. The method for preparing a semiconductor device according to claim 21, characterized in that: Before the step of forming the first stacked structure, the method further includes: providing a substrate; The step of forming a first stacking structure includes: forming the first stacking structure on the substrate; Among them, one of the second stacking structure and the third stacking structure is located on a side of the first stacking structure away from the substrate; before forming the other of the second stacking structure and the third stacking structure, it also includes: removing the substrate.

23. The method for preparing a semiconductor device according to claim 21, characterized in that: defining a stacked structure formed by the first stacked structure, the second stacked structure and the third stacked structure as a first semiconductor structure; After forming one of the second stacking structure and the third stacking structure, the method further includes: A second semiconductor structure having a circuit element for controlling the first semiconductor structure is formed on a side of the second stack structure or the third stack structure away from the first stack structure, and the second semiconductor structure is bonded to the first semiconductor structure in the first direction.

24. The method for preparing a semiconductor device according to claim 21, wherein: The step of forming a first stacking structure includes: At least one second electrode layer and a plurality of first insulating layers are formed in an alternating stacked manner in a first direction; Opening a first channel hole on a stack formed by the second electrode layer and a plurality of first insulating layers; A first electrode layer extending in the first direction and an energy storage layer extending in the first direction and located between the second electrode layer and the first electrode layer are formed in the first channel hole to obtain The first channel structure is provided, and a plurality of the second electrode layers and a plurality of the first insulating layers are arranged around the energy storage layer, and the energy storage layer is arranged around the first electrode layer.

25. The method for preparing a semiconductor device according to claim 24, characterized in that: The step of forming a second stack structure including a first selection transistor on the first side of the first stack structure comprises: forming a second insulating layer, a word line and a third insulating layer in sequence on the first side of the first stacked structure; forming a plurality of second channel holes on the second stacked structure, penetrating the second insulating layer, the word line and the third insulating layer and corresponding to the first channel structures one by one; and A first channel layer and a first gate insulating layer are sequentially formed in the second channel hole from the center of the second channel hole to the hole wall of the second channel hole, and the first channel layer includes a first drain, a channel region and a first source, so that the first drain and the first source are located on opposite sides of the channel region in the first direction and the first source is connected to the first electrode layer.

26. The method for preparing a semiconductor device according to claim 25, characterized in that: After the step of forming a second stack structure including a first selection transistor on the first side of the first stack structure, the method further includes: A first bit line is formed on a side of the second stack structure away from the first stack structure, and the first bit line is connected to the first drain.

27. The method for preparing a semiconductor device according to claim 26, wherein: The step of forming a first bit line on a side of the second stacking structure away from the first stacking structure and connecting the first bit line to the first drain comprises: forming a sixth insulating layer on a side of the second stacking structure away from the first stacking structure, forming a first bit line in the sixth insulating layer and connecting the first bit line to the first drain; After forming a first bit line on a side of the second stacking structure away from the first stacking structure and connecting the first bit line to the first drain, the method further includes forming a third air gap in the sixth insulating layer, the third air gap being located between two at least partially adjacent first bit lines and extending along a third direction.

28. The method for preparing a semiconductor device according to claim 24, wherein: The step of forming a third stack structure including a second selection transistor on the second side of the first stack structure comprises: forming a source line and a fourth insulating layer in sequence on the second side of the first stacked structure; A plurality of insulating layers are formed on the third stacked structure, penetrating the source lines and the fourth insulating layer and adjacent to the source lines. a third channel hole corresponding one-to-one to the first channel structure; and The gate, a second gate insulating layer covering the gate, and a second channel layer arranged around the second gate insulating layer are formed in sequence in the third channel hole from the center of the third channel hole to the hole wall of the third channel hole, and a second drain is formed on a side of the second gate insulating layer away from the first electrode layer, and the gate is connected to the first electrode layer and the second drain is connected to the second channel layer.

29. The method for preparing a semiconductor device according to claim 28, characterized in that: After the step of forming a third stack structure including a second selection transistor on the second side of the first stack structure, the method further includes: A second bit line is formed on a side of the third stack structure away from the first stack structure, and the second bit line is connected to the second drain of the second selection transistor.

30. The method for preparing a semiconductor device according to claim 29, wherein: The step of forming a second bit line on a side of the third stack structure away from the first stack structure and connecting the second bit line to the second drain of the second selection transistor comprises: forming a seventh insulating layer on a side of the third stacking structure away from the first stacking structure, and forming a second bit line in the seventh insulating layer so that the second bit line is connected to the second drain; After the step of forming a second bit line on a side of the third stacking structure away from the first stacking structure and connecting the second bit line to the second drain of the second selection transistor, the method further includes: forming a fourth air gap in the seventh insulating layer, the fourth air gap being located between two at least partially adjacent second bit lines and extending along a third direction.

31. A memory system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 20; and A controller is configured to control the semiconductor device.

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