Resistive random access memory device with metal nitride compound electrode

Abstract

The invention relates to a resistive random access memory (RRAM) device. In some embodiments, an RRAM device includes a first electrode including a metal nitride, a second electrode including a first conductive material, and a switching oxide layer between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and / or tantalum nitride. The first electrode does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a resistive random access memory (RRAM), and more particularly, to a RRAM device having a metal nitride compound electrode. Background Art

[0002] An RRAM device is a two-terminal passive device with adjustable and non-volatile resistance. The resistance of the RRAM device can be electrically switched between a high resistance state (HRS) and a low resistance state (LRS) by applying a suitable programming signal to the RRAM device. RRAM devices can be used to form a crossbar array, which can be used to implement in-memory computing applications, non-volatile solid-state memory, image processing applications, neural networks, etc. Summary of the invention

[0003] The following is a brief summary of the present disclosure, which is used to provide a basic understanding of some aspects of the present disclosure. The summary is not an extensive overview of the present disclosure. The summary is not intended to identify the key or important elements of the present disclosure, nor is it intended to illustrate any scope of a particular implementation of the present disclosure or any scope of the claims. The sole purpose of the summary is to present some concepts of the present disclosure as a language simplification of a more detailed description presented subsequently.

[0004] According to one or more aspects of the present disclosure, a resistive random access memory (RRAM) device may include: a first electrode including a metal nitride; a second electrode including a first conductive material; and a switching oxide layer located between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide. The first electrode does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.

[0005] According to one or more aspects of the present disclosure, a method for manufacturing a RRAM device is provided. The method includes manufacturing one or more layers on a first electrode including a metal nitride; and manufacturing a second electrode on a top layer of the one or more layers. The second electrode includes a conductive material. The one or more layers include a switching oxide layer located between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide.

[0006] In some embodiments, the metal nitride in the first electrode includes titanium nitride.

[0007] In some embodiments, the metal nitride in the first electrode includes tantalum nitride.

[0008] In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x≤2.0 and y≤2.5.

[0009] In some embodiments, the conductive material in the second electrode includes tantalum.

[0010] In some embodiments, the RRAM device further includes an interface layer A between the switching oxide layer and the second electrode.

[0011] In some embodiments, the interface layer A comprises aluminum oxide.

[0012] In some embodiments, the RRAM device further includes an interface layer B between the switching oxide layer and the first electrode.

[0013] In some embodiments, the interface layer A or the interface layer B comprises aluminum oxide.

[0014] In some embodiments, both the interface layer A and the interface layer B include aluminum oxide. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be used to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0016] Figure 1 is a schematic diagram showing an example of a crossbar switch circuit according to some embodiments of the present disclosure.

[0017] Figure 2 is a schematic diagram showing an example of a cross-point device according to some embodiments of the present disclosure.

[0018] Figure 3A A cross-sectional view of a first example RRAM device using a metal nitride instead of platinum (Pt) in a non-reactive electrode is shown.

[0019] Figure 3B and Figure 3C They are shown respectively Figure 3A Cross-sectional view of the RRAM device in low-resistance state and high-resistance state.

[0020] Figure 4 is a flow chart illustrating a method of manufacturing a RRAM device according to some embodiments of the present disclosure.

[0021] Figure 5A IV (current-voltage) characteristics of RRAM devices in some embodiments according to the present disclosure are shown.

[0022] Figure 5B IV curves are shown that illustrate simulated behavior of RRAM devices according to some embodiments of the present disclosure.

[0023] Fig. 6A and Figure 6B The read current stability over time of an example RRAM device at room temperature and 135° C. is shown, respectively.

[0024] Figure 7 A cross-sectional view of a second example RRAM device using a metal nitride instead of platinum (Pt) in a non-reactive electrode is shown.

[0025] Figure 8 A flow chart of a method for manufacturing a RRAM device according to some embodiments of the present disclosure is shown.

[0026] Fig. 9 A cross-sectional view of a third example RRAM device using a metal nitride instead of platinum (Pt) in a non-reactive electrode is shown.

[0027] Fig.10 and Fig.11 A flow chart of a method for manufacturing a RRAM device according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0028] Various aspects of the present disclosure provide RRAM devices and methods for making RRAM devices. RRAM devices are two-terminal passive devices with adjustable resistance. The RRAM device may include a first electrode, a second electrode, and a switching oxide layer located between the first electrode and the second electrode. In some embodiments, the first electrode and the second electrode may be the bottom electrode and the top electrode of the RRAM device, respectively. In some embodiments, the first electrode and the second electrode may be the top electrode and the bottom electrode of the RRAM device, respectively. The first electrode may include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc. The second electrode may include a reactive metal, such as tantalum (Ta). An electrode including a non-reactive metal may also be referred to as a "non-reactive electrode". An electrode including a reactive metal may also be referred to as a "reactive electrode". The switching oxide layer may include a transition metal oxide, such as hafnium oxide (HfO x ) or tantalum oxide (TaO x). The RRAM device may be in an initial state or original state and have an initial high resistance before it receives an appropriate electrical stimulus (e.g., a voltage or current signal applied to the RRAM device). The RRAM device may be converted from the original state to a low resistance state through a formation process, or may be switched from a high resistance state to a low resistance state through a setting process. The formation process refers to programming the device from the original state. The setting process refers to programming the device from a high resistance state (HRS). After the reactive metal electrode is deposited on the switching oxide, the reactive metal may absorb oxygen ions from the switching oxide layer, creating oxygen vacancies in the switching oxide layer, and the oxygen ions may migrate in the switching oxide through a vacancy mechanism. During the formation process, an appropriate programming signal (e.g., a voltage or current signal) applied to the RRAM device may cause oxygen ions to drift and migrate from the switching oxide to the reactive electrode. Therefore, a conductive channel or conductive filament may pass through the switching oxide layer (e.g., from a reactive electrode to a non-reactive electrode). Then, the RRAM device may be reset to a high resistance state by applying a reset signal (e.g., a voltage signal, a current signal) to the RRAM device. Applying the reset signal to the RRAM device can cause the oxygen ions to migrate back to the switching oxide layer, thereby interrupting the conductive filament. By applying an appropriate programming signal (e.g., a voltage signal, a current signal) to the RRAM device, the RRAM device can be electrically switched between a high resistance state and a low resistance state. In a crossbar array circuit, the programming signal can be provided to a specified RRAM device through a selector (e.g., a transistor).

[0029] An RRAM device containing platinum (Pt) in a non-reactive electrode can provide RRAM high performance, such as reliability, durability, multi-level, retention, etc. In an RRAM device including a bottom electrode containing platinum, a switching oxide layer including tantalum oxide, and a Ta-containing switching oxide layer (also referred to as "Pt / TaO x / Ta system”), TaO x The Ta wire in Pt / HfO exhibits excellent linearity, analog, retention and durability. x In the / Ta system, Ta can migrate to HfO x In HfO xTa-rich filaments are formed in RRAM devices and exhibit excellent linearity, analog, retention, and durability in IMC applications. However, the material and processing costs of platinum are high, and major manufacturing plants may not be ready to incorporate platinum in their production processes. Therefore, it is desirable to be able to replace Pt in the non-reactive electrode in RRAM devices with a suitable alternative material that is chemically stable so that it does not react with oxygen during RRAM switching and can enable RRAM devices to be multi-level or analog in IMC applications.

[0030] In the present disclosure, some embodiments use metal nitrides, such as TiN or TaN, as an alternative material to the non-reactive electrode Pt in the RRAM device. The first electrode does not include a non-reactive metal, such as platinum (Pt) or palladium (Pd). TiN and TaN are both conductive materials. Both TiN and TaN are compatible with the manufacturing process of CMOS (complementary metal oxide semiconductor), can be mass-produced, and have a much lower production cost than Pt. Both TiN and TaN are chemically stable, and they do not react with oxygen during the RRAM switching process. For IMC applications, RRAM devices containing TiN or TaN in the non-reactive electrode have multi-level or analog characteristics.

[0031] In some embodiments, the RRAM device may include TiN / HfO for the first electrode, the switching oxide layer, and the second electrode, respectively. x In another embodiment, the RRAM device may include a TiN / HfO2 layer for the first electrode, the switching oxide layer, the interface layer, and the second electrode. x / AlO x / Ta device stack. For an interface layer including aluminum oxide, the RRAM device may be a high resistance and annealing resistant RRAM device. In a further embodiment, the RRAM device may include TiN / AlO for the first electrode, the first interface layer, the switching oxide layer, the second interface layer, and the second electrode, respectively. x / HfO x / AlO x / Ta device stack.

[0032] Compared with RRAM devices using Pt-based non-reactive electrodes, RRAM devices using TiN or TaN-based non-reactive electrodes have lower material and manufacturing costs, can be used in CMOS processes, and can be mass-produced. The RRAM devices disclosed herein exhibit appropriate performance and capabilities in multi-level switching and analog behavior.

[0033] Figure 11 is a schematic diagram showing an example 100 of a crossbar switch circuit according to some embodiments of the present disclosure. As shown in the figure, the crossbar switch circuit 100 may include a plurality of interconnected conductive lines for a crossbar array of n rows by m columns, such as one or more row lines 111a, 111b, ..., 111i, ..., 111n, and column lines 113a, 113b, ..., 113j, ..., 113m. The crossbar switch circuit 100 may further include crosspoint devices 120a, 120b, ..., 120z, etc. Each crosspoint device may connect a row line and a column line. For example, the crosspoint device 120ij may connect a row line 111i and a column line 113j. In some embodiments, the crossbar switch circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and one or more suitable circuit components for implementing a crossbar switch device. The number of column lines 113a-m and the number of row lines 111a-n may be the same or different.

[0034] The row lines 111 may include a first row line 111a, a second row line 111b, ..., 111i, ..., and an nth row line 111n. Each row line 111a, ..., 111n may be and / or include any suitable conductive material. In some embodiments, each row line 111a-n may be a metal line.

[0035] The column lines 113 may include a first column line 113a, a second column line 113b, ... and an mth column line 113m. Each column line 113a-m may be and / or include any suitable conductive material. In some embodiments, each column line 113a-m may be a metal line.

[0036] Each cross-point device 120 may be and / or include any suitable device having an adjustable resistance, such as a memristor, a phase change memory (PCM) device, a floating gate, a spintronic device, a resistive random access memory (RRAM), a static random access memory (SRAM), etc. In some embodiments, one or more of the cross-point devices 120 may include, for example, a combination of Figure 3A-1 2 RRAM device described.

[0037] The crossbar switch circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal can be applied to one or more rows (e.g., one or more selected rows) of the crossbar switch circuit 100. The input signal can flow through the crosspoint devices of the rows of the crossbar switch circuit 100. The conductance of the crosspoint device can be adjusted to a specific value (also referred to as a "weighted value"). According to Ohm's law, the input voltage is multiplied by the crosspoint conductance and generates a current flowing through the crosspoint device. Through Kirchhoff's law, the sum of the currents through the devices on each column generates a current as an output signal, which can be read from the column (e.g., the output of an ADC). According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I=VG, where I is the output signal matrix, expressed as current; V is the input signal matrix, expressed as voltage; and G is the conductance matrix of the crosspoint device. Therefore, according to Ohm's law, the input signal is weighted by its conductance at each crosspoint device. The weighted current is output through each column line and accumulated according to Kirchhoff's current law. This can be achieved by implementing parallel multiplication and summation in the crossbar array to achieve in-memory computing (IMC).

[0038] Figure 2 Schematic diagram of an example 200 of a cross-point device according to an embodiment of the present disclosure is shown. As shown, the cross-point device 200 can connect a bit line (BL) 211, a select line (SEL) 213, and a word line (WL) 215. The bit line 211 and the word line 215 can be respectively as shown in FIG. Figure 1 The column and row lines described.

[0039] The cross-point device 200 may include a RRAM device 201 and a transistor 203. A transistor is a three-terminal device, which may be labeled as a gate (G), a source (S), and a drain (D). The transistor 203 may be connected in series to the RRAM device 201. Figure 2 As shown, the first electrode of the RRAM device 201 can be connected to the drain of the transistor 203. The second electrode of the RRAM device 201 can be connected to the bit line 211. The source of the transistor 203 can be connected to the word line 215. The gate of the transistor 203 can be connected to the select line 213. The RRAM device 201 may include a combination of the following Figure 3A-11One or more RRAM devices described. The cross-point device 200 may also be referred to as a one-transistor-one-resistor (1T1R) configuration. The transistor 203 may be used as a selector and a current controller, which may set the current compliance of the RRAM device 201 during programming. The gate voltage of the transistor 203 may set the current compliance of the cross-point device 200 during programming, and thus control the conductance and analog behavior of the cross-point device 200. For example, when the cross-point device 200 is set from a high-resistance state to a low-resistance state, a setting signal (e.g., a voltage signal, a current signal) may be provided via a bit line (BL) 211. Another voltage, also referred to as a select voltage or a gate voltage, may be applied to the transistor gate via a select line (SEL) 213 to turn on the gate and set the current compliance, while a word line (WL) 215 may be set to ground. When the cross-point device 200 is reset from a low-resistance state to a high-resistance state, a gate voltage may be applied to the gate of the transistor via a select line 213 to turn on the transistor gate. At the same time, a reset signal may be sent to the RRAM device 201 via the word line 215 , while the bit line 211 may be set to ground.

[0040] Figure 3A , 3B 3C illustrate cross-sectional views of example RRAM devices according to some embodiments of the present disclosure. RRAM devices 300b and 300c may correspond to the low resistance state and the high resistance state of RRAM device 300a, respectively.

[0041] like Figure 3A As shown, the RRAM device 300a may include a substrate 310, a first electrode 320 fabricated on the substrate 310, a switching oxide layer 330, and a second electrode 340. The switching oxide layer 330 is fabricated between the first electrode 320 and the second electrode 340. The substrate 310 may include one or more layers of any suitable material that can be used for a RRAM device substrate, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. In some embodiments, the substrate 310 may include a diode, a transistor, an interconnect, an integrated circuit, etc. In some embodiments, the substrate may include a driving circuit, which includes one or more circuits (e.g., a circuit array) that can be controlled individually. In some embodiments, the driving circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers.

[0042] The first electrode 320 may include a metal nitride. The metal nitride is conductive and non-reactive to the switching oxide. The metal nitride may have suitable chemical stability, i.e., it does not react with oxygen during RRAM switching. For example, the first electrode 320 may include titanium nitride (TiN), tantalum nitride (TaN), etc. The first electrode 320 does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc. In some embodiments, the first electrode 320 does not include Pt or Pd. RRAM devices that include metal nitrides in their non-reactive metals have multi-level or analog behaviors required for IMC applications.

[0043] In some embodiments, a Ta layer and / or a Ti layer (not shown) may be formed between the first electrode and the substrate 310 to enhance adhesion between the substrate 310 and components of the RRAM device 300 a .

[0044] The switching oxide layer 330 may include one or more transition metal oxides among binary oxides, ternary oxides, and advanced oxides, such as TaO x , HfO x 、TiO x ,NbO x 、ZrO x In some embodiments, the chemical stability of the non-reactive material in the first electrode 320 may be higher than the chemical stability of the transition metal oxide in the switching oxide layer 330. In some embodiments, the transition metal oxide includes HfO x or TaO x At least one of: wherein x can be used to indicate that the oxide is oxygen-deficient compared to its complete (or terminal) oxide, and the value of x can vary depending on the ratio of oxygen and metal atoms in the stoichiometry of its complete oxide, such as for HfO x (where HfO2 is a complete oxide) x≤2.0, for TaO x (where Ta2O5 is a complete oxide), x≤2.5.

[0045] The first electrode (comprising TiN) and the switching oxide layer (comprising HfO x ) can be evaluated by, for example, the following chemical reaction (1):

[0046] HfO2 + TiN = TiO2 + HfN (1)

[0047] ΔH°=ΔH° TiO2 +ΔH° HfN -ΔH° HfO2 -ΔH° TiN =32.4kcal>0

[0048] ΔS°=S° TiO2 +S° HfN -S° HfO2 -S° TiN =0.04cal / deg~0

[0049] ΔG°=ΔH°-TΔS°=32400–0.04T>0

[0050] ΔH°, ΔS°, and ΔG° are the enthalpy change, entropy change, and free energy change of reaction (1) at 298K (or 25°C), respectively.

[0051] ΔH° >> 0 and ΔG° >> 0 indicate that the chemical reaction is thermodynamically unfavorable (1), or that HfO2 and TiN do not spontaneously react to form TiO2 and HfN when they come into contact.

[0052] For thermochemical stability assessment, the following is a reference table based on Metallurgical Thermochemistry, 5th edition, by O. Kubaschewski and CB Alcock.

[0053]

[0054] The second electrode 340 may include any suitable metal material that is electronically conductive and reactive to the switching oxide. For example, the metal material in the second electrode 340 may include Ta, Hf, Ti, TiN, TaN, etc. The second electrode 340 may react with the switching oxide and have a suitable oxygen solubility so that oxygen can be absorbed from the switching oxide layer 330 and oxygen vacancies can be generated in the switching oxide layer 330. In other words, the reactive metal material in the second electrode 340 may have a suitable oxygen solubility and / or oxygen mobility. In some embodiments, the second electrode 340 may not only generate oxygen vacancies in the switching oxide layer 330 (e.g., by scavenging oxygen), but may also act as an oxygen storage or oxygen source for the switching oxide layer 330 during cell programming.

[0055] The RRAM device 330a may have an initial resistance (also referred to herein as “original resistance”) after fabrication. The initial resistance of the RRAM device 300a may be changed, and the RRAM device 300a may be switched to a state of lower resistance through a formation process. For example, an appropriate voltage or current may be applied to the RRAM device 300a. The voltage applied to the RRAM device 300a may cause the metal material in the second electrode to absorb oxygen from the switching oxide layer 330 and generate oxygen vacancies in the switching oxide layer. As a result, a conductive channel (e.g., a conductive filament) rich in oxygen vacancies may be formed in the switching oxide layer 330. For example, as Figure 3BAs shown, a conductive channel 335a can be formed in the switching oxide layer. As shown, the conductive channel 335a can cross the switching oxide layer 330 from the second electrode 340 to the first electrode 320. The RRAM device 300b can be reset to a high resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) can be applied to the RRAM device 300b during the reset process. In some embodiments, the set signal and the reset signal can have opposite polarities, such as a positive signal and a negative signal, respectively. The application of the reset signal can cause oxygen to drift back to the switching oxide layer 330 and recombine with one or more oxygen vacancies. For example, during the reset process, a conductive channel 335a can be formed in the switching oxide layer 330. Figure 3C As shown, the conductive channel can be interrupted by an oxide gap located between the interrupted conductive channel 335b and the first electrode 320. The lateral dimension of the interrupted conductive channel 335b can be smaller than the lateral dimension of the conductive channel 335a. In some embodiments, the interrupted conductive channel 335b discontinuously connects the first electrode 320 and the second electrode 340. The RRAM device 300a-c can be electrically switched between a high resistance state and a low resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device.

[0056] In one embodiment, the second electrode 340 may include one or more alloys. Each alloy may include two or more metal elements. Each of the alloys may include a binary alloy (e.g., an alloy containing two metal elements), a ternary alloy (e.g., an alloy containing three metal elements), a quaternary alloy (e.g., an alloy containing four metal elements), a quinary alloy (e.g., an alloy containing five metal elements), and / or a high-order alloy (e.g., an alloy containing more than six metal elements). In some embodiments, the second electrode 340 may include one or more alloys, the alloy containing a first metal element and one or more second metal elements. Each second metal element has a reactivity less than or greater than the first metal element to the transition metal oxide in the switching oxide layer. In some embodiments, the first metal element may be Ta. The second metal element may include one or more of tungsten (W), hafnium (Hf), molybdenum (Mo), niobium (Nb), zirconium (Zr), etc. In some embodiments, the ratio of the first metal element to the second metal element of the alloy in the second electrode 340 may be 50 atomic percent. In some embodiments, the appropriate ratio of the first metal element to the second metal element in the alloy may be optimized from the entire composition range. During the formation process, the second metal element can generate less oxygen vacancies in the switching oxide layer than the first metal element. Therefore, the lateral size of the conductive filament formed in the RRAM device including the second electrode containing the alloy can be smaller than the lateral size of the conductive filament formed in the RRAM device including the second electrode made of only the first metal.

[0057] In some embodiments, the second electrode 340 may include multiple layers of different metal materials. For example, the second electrode 340 may include a titanium (Ti) layer and a tantalum (Ta) layer. The Ti layer may be much thinner than the Ta layer. For example, the thickness of the Ti layer may be between about 0.2nm and 5nm. The thickness of the Ta layer may be about 50nm. In some embodiments, the thickness of the Ti layer may be between 0.3nm and 2nm. Both Ti and Ta can capture and release oxygen during device operation. Adding a thin Ti layer to a RRAM device can change the original resistance of the RRAM device, resulting in a less obtrusive formation process, lowering the formation voltage, lowering the reset current, and reducing the voltage and / or current requirements in subsequent operations.

[0058] In some embodiments, the RRAM device 300a may include TiN / HfO for the first electrode 320, the switching oxide layer 330, and the second electrode 340, respectively. x / Ta device stack.

[0059] Figure 4 It is shown that according to the embodiment of the present disclosure, a Figures 3A-3CFlowchart of an example method 400 for an RRAM device of a Pt-free RRAM device 330 a - 330 c in FIG.

[0060] In 410, a first electrode may be fabricated on a substrate. Fabricating the first electrode may include depositing one or more layers of a metal nitride, such as TiN or TaN. For example, fabricating the first electrode may include depositing one or more layers of TiN using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a Ti reactive sputtering technique, and / or any other suitable deposition technique. The first electrode may be and / or include a combination of the above. Figure 3A Depicted first electrode 320. In some embodiments, a thin layer of bonding material, such as Ti, Ta, etc., may be fabricated between the substrate and the first electrode.

[0061] In 420, a switching oxide layer including one or more transition metal oxides may be formed on the first electrode. The transition metal oxide may include, for example, HfO x For example, fabricating the switching oxide layer may include depositing HfO using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a reactive sputtering technique of Hf, and / or any other suitable deposition technique. x The switching oxide layer may be and / or include the above combination Figure 3A A switching oxide layer 330 is depicted.

[0062] At 430, a second electrode may be fabricated on the switching oxide layer. Fabricating the second electrode may include fabricating one or more layers of one or more metallic materials, wherein the metallic materials are electronically conductive and reactive to the switching oxide. For example, fabricating the second electrode may include depositing one or more layers of Ta using a physical vapor deposition (PVD) technique and / or any other suitable deposition technique. The second electrode may be and / or include a combination of the above Figure 3A The second electrode 340 is described.

[0063] Figure 5A The use of TiN / HfO in some embodiments of the present disclosure is shown. x IV (current-voltage) characteristics of the RRAM device 300a of the / Ta device stack. The RRAM device 300a is Figure 5A Switch 1, Switch 2, and Switch 3 in FIG. 5 provide repeatable and desired set-reset operation, demonstrating stability over multiple switching cycles.

[0064] Figure 5B The present invention shows the use of TiN / HfO in some embodiments. xIV curve of analog behavior of RRAM device 300a of Ta / Ta device stack. RRAM device 300a exhibits desired analog behavior, i.e., the device resistance can be adjusted to multiple levels (or analog behavior) by controlling the current compliance, and the current is linearly proportional to the voltage (or linear behavior) in each resistance state.

[0065] Fig. 6A and 6B Graphs 600A and 600B show device read current characteristics of an example RRAM device over time according to some embodiments of the present disclosure. The example RRAM device may include TiN / HfO x / Ta device stack. Figures 600A and 600B represent device read current characteristics of an example RRAM device at room temperature and 135°C, respectively. Figures 600A and 600B may represent the results of a device retention test of the ability of the RRAM device to maintain a resistance level over time. Figures 600A and 600B may also represent the results of a read stability test, as the RRAM device is under a constant read (with a read voltage of 0.2V) due to its ability to maintain a resistance level over time. Fig. 6A As shown, the RRAM device exhibits the desired device read stability over time at room temperature. Figure 6B As shown, the RRAM device exhibits desirable read stability over time at 135° C. Thus, the RRAM device exhibits desirable resistance stability or retention at the device operating temperature.

[0066] Figure 7 A cross-sectional view of an example RRAM device 700 is shown in another embodiment according to the present disclosure, wherein the example RRAM device 700 uses metal nitrides instead of platinum (Pt) in its non-reactive electrodes. The RRAM device 700 may be referred to as a Pt-free RRAM device.

[0067] The RRAM device 700 may include a first electrode 720, a switching oxide layer 730, an interface layer A (ILA) 750, and a second electrode 740. The first electrode 720, the switching oxide layer 730, and the second electrode 740 may be respectively combined with Figure 3A The first electrode 320, the switching oxide layer 330, and the second electrode 340 are the same as described above. In some embodiments, the RRAM device 700 may further include a combination of Figure 3A A substrate (not shown) is described.

[0068] ILA 750 (also referred to as a "first interface layer") may include a first material that is more chemically stable than a transition metal oxide. The first material may include, for example, Al2O 3、 MgO, Y2O 3、La2O3, etc. ILA 750 may include a discontinuous film of the first material and / or a continuous film of the first material. In some embodiments, the thickness of ILA 750 may be approximately between 0.2 nm and 0.5 nm. In some embodiments, the ILA 750 may include an Al2O3 film having a thickness equal to or less than 0.5 nm. In some embodiments, the ILA 750 may be and / or include an Al2O3 film having a thickness less than 1 nm.

[0069] In some embodiments, the RRAM device 700 may include TiN / HfO for the first electrode 720, the switching oxide layer 730, the ILA 750, and the second electrode 740, respectively. x / AlO x In the case where the ILA 750 includes aluminum oxide, the RRAM device 700 may be a high resistance and annealing resistant RRAM device.

[0070] Figure 8 It is shown that according to some embodiments of the present disclosure, a method of manufacturing a Figure 7 800 is a flow chart of an example method of an RRAM device 700 of an RRAM device.

[0071] At 810, a first electrode may be fabricated on a substrate. Fabricating the first electrode may include depositing one or more layers of a metal nitride, such as TiN or TaN. For example, fabricating the first electrode may include depositing one or more layers of TiN using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a Ti reactive sputtering technique, and / or any other suitable deposition technique. The first electrode may be and / or include the above combined Figure 7 A first electrode 720 is described.

[0072] In 820, a switching oxide layer including one or more transition metal oxides may be fabricated on the first electrode. The transition metal oxide may include, for example, HfOx. For example, fabricating the switching oxide layer may include depositing HfOx using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a reactive sputtering technique of Hf, and / or any other suitable deposition technique. The switching oxide layer may be and / or include a combination of the above. Figure 7 The switching oxide layer 730 .

[0073] In 830, an interfacial layer may be fabricated on the switching oxide layer. The first interfacial layer may include a metal that is more chemically stable than the transition metal oxide in the switching oxide layer, such as AlO. x, such as Al2O3. For example, manufacturing the first interface layer may include depositing AlO using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, an Al reactive sputtering technique, and / or any other suitable deposition technique. x The interface layer A may be and / or include the above combination Figure 7 ILA 750 as described.

[0074] At 840, a second electrode may be fabricated on the interface layer. Fabricating the second electrode may include fabricating one or more layers of one or more metallic materials that are electronically conductive and reactive to the switching oxide. For example, fabricating the second electrode may include depositing one or more layers of Ta using a physical vapor deposition (PVD) technique and / or any other suitable deposition technique. The second electrode may be and / or include a combination of the above Figure 7 The second electrode 740.

[0075] Fig. 9 9 shows a cross-sectional view of an example RRAM device 900 that uses a metal nitride instead of platinum (Pt) in its non-reactive electrode according to a further embodiment of the present disclosure. The RRAM device 900 may be referred to as a Pt-free RRAM. The RRAM device 900 may include a first electrode 920, an interface layer B (ILB) 960, a switching oxide layer 930, an interface layer A (ILA) 950, and a second electrode 940. The first electrode 920, the switching oxide layer 930, and the second electrode 940 may be combined with Figure 3A The first electrode 320, the switching oxide layer 330, and the second electrode 340 are the same as described above. The ILA 950 may be Figure 7 In some embodiments, the RRAM device 900 may further include a combination of Figure 3A A substrate (not shown) is described.

[0076] The ILB 960 may include a second material that is more chemically stable than a transition metal oxide. The second material may include, for example, Al2O3, MgO, Y2O3, La2O3, etc. The ILB 960 may include a discontinuous film of the second material and / or a continuous film of the second material. In some embodiments, the thickness of the ILB 960 may be between about 0.2nm and about 0.5nm. In some embodiments, the ILB 960 may include an Al2O3 film having a thickness equal to or less than 0.5nm. In some embodiments, the ILB 960 may include an Al2O3 film having a thickness less than 1nm.

[0077] The RRAM device 900 may use a device stack of TiN / AlOx / HfOx / AlOx / Ta for the first electrode 920, the ILB 960, the switching oxide layer 930, the ILA 950, and the second electrode 940, respectively. Through the first and second interface layers, the RRAM device 900 may be a high resistance and annealing resistant RRAM device.

[0078] Fig.10 According to some embodiments of the present disclosure, the Fig. 9 900 is a flow chart of a method example 1000 of an RRAM device in the present invention.

[0079] In 1010, a first electrode may be fabricated on a substrate. Fabricating the first electrode may include depositing one or more layers of metal nitride, such as TiN or TaN. For example, fabricating the first electrode may include depositing one or more layers of TiN using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a Ti reactive sputtering technique, and / or any other suitable deposition technique. The first electrode may be and / or include a combination of the above. Fig. 9 The first electrode 920.

[0080] In 1020, an interface layer B (ILB) may be formed on the first electrode. The ILB may include a transition metal oxide (e.g., AlO) in a switching oxide layer described later. x, For example, fabricating the interface layer B may include depositing AlO using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, an Al reactive sputtering technique, and / or any other suitable deposition technique. x The interface layer B may be and / or include the above combination Fig. 9 ILB 960 as described.

[0081] In 1030, the switching oxide layer including one or more transition metal oxides may be fabricated on the interface layer B. The transition metal oxide may include, for example, HfO x For example, fabricating the switching oxide layer may include depositing HfO using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a reactive sputtering technique of Hf, and / or any other suitable deposition technique. x The switching oxide layer may be and / or include a combination of the above Fig. 9 The switching oxide layer 930 .

[0082] In 1040, an interfacial layer A (ILA) may be fabricated on the switching oxide layer. The ILA may include a metal that is more chemically stable than the transition metal oxide in the switching oxide layer, such as AlO.x , such as Al2O3. For example, manufacturing the interface layer A may include depositing AlO using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, Al reactive sputtering technology and / or any other suitable deposition technology. x The interface layer A may be and / or include the above combination Fig. 9 ILA 950 as described.

[0083] In 1050, a second electrode may be fabricated on the interface layer A. Fabricating the second electrode may include fabricating one or more layers of one or more metallic materials that are electronically conductive and reactive to the switching oxide. For example, fabricating the second electrode may include depositing one or more Ta layers using a physical vapor deposition (PVD) technique and / or any other suitable deposition technique. The second electrode may be and / or include a combination of the above Fig. 9 The second electrode 940.

[0084] Fig.11 According to some embodiments of the present disclosure, the Figure 3A The RRAM device 300a, Figure 7 The RRAM device 700 and / or Fig. 9 Flowchart of an example method 1100 for an RRAM device of the RRAM device 900 .

[0085] In 1110, one or more layers may be fabricated on a first electrode. The first electrode includes a metal nitride, such as titanium nitride, tantalum nitride, etc. The one or more layers may include a switching oxide layer located between the first electrode and the second electrode of the RRAM device. The switching oxide layer includes at least one transition metal oxide (e.g., HfO x and / or TaO y , where x≤2.0 and y≤2.5).

[0086] In some embodiments, the one or more layers on the first electrode may further include one or more interface layers, such as an interface layer A between the switching oxide layer and the second electrode and / or an interface layer B between the switching oxide layer and the first electrode. Each of the interface layer A and the interface layer B may include Al2O3, MgO, Y2O3, La2O3, etc. In some embodiments, at least one of the interface layer A and the interface layer B includes Al2O3.

[0087] In 1120, a second electrode may be fabricated on a top layer of the one or more layers. The second electrode may include a conductive material. In some embodiments, the conductive material includes Ta, such as one or more alloys of Ta, a Ta layer, etc. In some embodiments, the second electrode includes a Ta layer and a Ti layer.

[0088] In some embodiments, the top layer of the one or more layers may be an interface layer A between the switching oxide layer and the second electrode. In some embodiments, the top layer of the one or more layers may be the switching oxide layer.

[0089] For the sake of brevity of explanation, the method of the present disclosure is depicted and described as a series of actions. However, actions according to the present disclosure can occur in various orders and / or simultaneously, and occur together with other actions that are not proposed and described in the present disclosure. In addition, not all actions of explanation can be required to realize the method according to the disclosed subject matter. In addition, those skilled in the art will understand and recognize that the method can be represented as a series of mutual states via state diagrams or events alternatively.

[0090] As used herein, the terms "approximately," "about," and "substantially" may refer to within a normal tolerance range in the art, such as within 2 standard deviations of the mean, within ±20% of a target size in some embodiments, within ±10% of a target size in some embodiments, within ±5% of a target size in some embodiments, within ±2% of a target size in some embodiments, within ±1% of a target size in some embodiments, and within ±0.1% of a target size in some embodiments. The terms "approximately" and "about" may include a target size. Unless otherwise specified or apparent from the context, all numerical values ​​described herein are modified by the term "about."

[0091] As used herein, a range includes all values ​​within the range. For example, a range of 1 to 10 may include any number, combination of numbers, sub-ranges of numbers from 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10, and fractions thereof.

[0092] The present disclosure has been described in detail in the above description. However, it is obvious that the present disclosure can be implemented without these specific details. In some examples, in order to highlight the content of the present invention, well-known structures and devices are shown in the form of block diagrams rather than specific details.

[0093] The terms "first", "second", "third", "fourth", etc. used in this document are marks used to distinguish different components and may not necessarily have the ordinal meaning of the numerical numbers used.

[0094] The word "example" or "exemplary" as used herein means serving as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be understood as being more preferred or advantageous than other aspects or designs. On the contrary, the purpose of using the words "example" or "exemplary" is to present the concept in a concrete way. In this application, the term "or" means to include "or" rather than exclude "or". That is, unless otherwise specified or as can be seen from the context, "X includes A or B" means any natural inclusive permutation and combination. That is, if X includes A; X includes B; or X includes both A and B, then in any of the above cases, "X includes A or B" is satisfied. In addition, "a" and "an" used in this application and the appended claims should generally be understood as "one or more", unless otherwise specified or as can be clearly indicated from the context as being directed to a singular form. "One embodiment" or "an embodiment" mentioned in this specification means that a specific feature, structure or characteristic associated with the embodiment is included in at least one embodiment. Therefore, the phrases "one embodiment" or "an embodiment" appearing in different places in this specification do not necessarily all refer to the same embodiment.

[0095] As used herein, when an element or layer is referred to as being “on” another element or layer, the element or layer may be directly on the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on” another element or layer, there are no intervening elements or layers present.

[0096] Although it is obvious to those skilled in the art that additional changes and modifications may be made to the present disclosure after understanding the above description, it should be understood that any specific embodiments shown and described by way of illustration should not be considered limiting. Therefore, the details of various embodiments are not intended to limit the scope of the claims, which themselves merely describe the disclosed technical features.

Claims

1. A resistive random access memory (RRAM) device, comprising: a first electrode comprising a metal nitride; a second electrode comprising a conductive material; and A switching oxide layer is located between the first electrode and the second electrode, wherein the switching oxide layer includes at least one transition metal oxide. 2 . The RRAM device of claim 1 , wherein the metal nitride in the first electrode comprises at least one of titanium nitride or tantalum nitride. 3 . The RRAM device of claim 1 , wherein the metal nitride in the first electrode does not include a non-reactive metal.

4. The RRAM device of claim 1 , wherein the at least one transition metal oxide comprises HfO x or TaO y At least one of , wherein x≤2.0 and y≤2.

5. The RRAM device of claim 1 , wherein the conductive material in the second electrode comprises tantalum.

6. The RRAM device according to claim 1, further comprising: An interface layer A is located between the switching oxide layer and the second electrode. The RRAM device according to claim 6 , wherein the interface layer A comprises aluminum oxide.

8. The RRAM device according to claim 6, further comprising: An interface layer B is located between the switching oxide layer and the first electrode. 9 . The RRAM device according to claim 8 , wherein the interface layer A or the interface layer B comprises aluminum oxide. 10 . The RRAM device of claim 8 , wherein both the interface layer A and the interface layer B comprise aluminum oxide.

11. A method of manufacturing a resistive random access memory (RRAM) device, comprising: fabricating one or more layers on a first electrode, the first electrode comprising a metal nitride; and A second electrode is fabricated on top of the one or more layers, the second electrode comprising a conductive material, wherein the one or more layers comprise a switching oxide layer between the first electrode and the second electrode, wherein the switching oxide layer comprises at least one transition metal oxide.

12. The method of claim 11, wherein the metal nitride in the first electrode comprises titanium nitride.

13. The method of claim 11, wherein the metal nitride in the first electrode comprises tantalum nitride.

14. The method of claim 11, wherein the at least one transition metal oxide comprises HfO x or TaO y At least one of , wherein x≤2.0 and y≤2.

5.

15. The method of claim 11, wherein the conductive material in the second electrode comprises tantalum.

16. The method of claim 11, wherein a top layer of the one or more layers comprises: An interface layer A is located between the switching oxide layer and the second electrode. The method according to claim 16 , wherein the interface layer A comprises aluminum oxide.

18. The method of claim 16, wherein the one or more layers further comprise: An interface layer B is located between the switching oxide layer and the first electrode. The method according to claim 18 , wherein the interface layer A or the interface layer B comprises aluminum oxide.

20. The method of claim 18, wherein the interface layer A and the interface layer B both comprise aluminum oxide.

Images