Synchronous sampling method, electronic equipment and computer program product

Abstract

The invention is suitable for the technical field of power grid relay protection, and provides a synchronous sampling method, electronic equipment and a computer program product, and the method comprises the steps: generating a voltage and current waveform at a fixed sampling rate under a specified sampling clock frequency for a specified power grid; based on the zero crossing points of the voltage waveform with the fixed sampling rate and sampling points of the synchronously sampled voltage waveform (obtained by interpolation based on an initial value of stepping interpolation), calculating a synchronous sampling error among a plurality of zero crossing points in real time, and determining the correction of the current stepping interpolation; based on the correction amount and the initial value of the stepping interpolation, correcting the size of the current stepping interpolation to obtain a target value of the stepping interpolation; and respectively acting the target value of the stepping interpolation on the current waveform and the voltage waveform with the fixed sampling rate, and changing the sampling rate of the output waveform so as to obtain a new synchronous sampling waveform. According to the invention, the frequency change of the voltage can be quickly responded, and the precision of synchronous sampling is ensured by adjusting the stepping interpolation in real time.

Description

Technical Field

[0001] The present application belongs to the technical field of power grid relay protection, and in particular, relates to a synchronous sampling method, electronic equipment, and computer program product. Background Art

[0002] The metering chip needs to output synchronous sampling waveforms for functions such as power quality analysis and load identification. In order to meet this requirement, a system that can achieve synchronous sampling at the hardware level must be designed.

[0003] At present, the mainstream technology for achieving synchronous sampling is the Phase-Locked Loop (PLL). PLL technology dynamically locks the phase and frequency between the reference clock and the analog-to-digital converter (ADC) sampling clock, thereby eliminating sampling errors caused by clock asynchrony and improving the accuracy and reliability of data acquisition.

[0004] Since metering chips are used in fluctuating power systems, they have strict requirements for fast response, and as legal metering instruments, they need to have industrial-grade high reliability. In addition, metering chips have very high accuracy requirements, and need to achieve ten-thousandth-level accuracy. When PLL technology changes the sampling clock frequency of the ADC, the noise floor of the ADC will change, resulting in metering error offset, which cannot meet the accuracy requirements of the metering chip.

[0005] Based on the above reasons, PLL technology is not suitable as a way to implement synchronous sampling of metering chips. Therefore, a synchronous sampling method suitable for the characteristics of metering chips is urgently needed. Summary of the invention

[0006] In view of this, the embodiments of the present application provide a synchronous sampling method, apparatus, computer device and computer program product, which can quickly respond to the frequency change of voltage and ensure the accuracy of synchronous sampling by adjusting the size of step interpolation in real time.

[0007] A first aspect of an embodiment of the present application provides a synchronous sampling method, comprising:

[0008] For a specified power grid, generate a fixed sampling rate voltage waveform and a fixed sampling rate current waveform at a specified sampling clock frequency;

[0009] Determining a correction amount of a step-by-step interpolation based on a zero-crossing point of the fixed sampling rate voltage waveform and a sampling point of a synchronously sampled voltage waveform, wherein the sampling point of the synchronously sampled voltage waveform is obtained by interpolation based on an initial value of the step-by-step interpolation, and the step-by-step interpolation represents a time interval between adjacent sampling points;

[0010] Based on the correction amount and the initial value of the step-by-step interpolation, the size of the step-by-step interpolation is corrected to obtain a target value of the step-by-step interpolation;

[0011] Based on the target value of the step-by-step interpolation, the sampling rates of the fixed sampling rate current waveform and the fixed sampling rate voltage waveform are changed by interpolation to obtain a new synchronous sampling waveform.

[0012] In an implementation of the first aspect, determining a correction amount of the step interpolation based on the zero-crossing point of the fixed sampling rate voltage waveform and the sampling point of the synchronously sampled voltage waveform includes:

[0013] Extracting the zero-crossing point of the fixed sampling rate voltage waveform;

[0014] Between multiple zero-crossing points of the fixed sampling rate voltage waveform, counting the actual number of sampling points of the synchronously sampled voltage waveform, and calculating the error between the actual number and the theoretical number;

[0015] A synchronization error between a fixed sampling rate voltage waveform and a voltage synchronous sampling waveform within a fixed time is determined, and a correction amount of the step-by-step interpolation is determined based on the synchronization error.

[0016] In an implementation of the first aspect, the stepping interpolation is corrected based on the correction amount and the initial value of the stepping interpolation to obtain the target value of the stepping interpolation, including:

[0017] Obtaining a preset synchronous sampling frequency point number, wherein the synchronous sampling frequency point number represents the number of sampling points of one or more cycles;

[0018] Based on the synchronous sampling frequency points, the correction amount and the initial value of the step-by-step interpolation, the size of the step-by-step interpolation is corrected to obtain the target value of the step-by-step interpolation.

[0019] In an implementation of the first aspect, the stepping interpolation is corrected based on the correction amount and the initial value of the stepping interpolation to obtain the target value of the stepping interpolation, including:

[0020] Based on the threshold limit information for the correction amount, the correction amount is adjusted to obtain a target correction amount;

[0021] Based on the target correction amount and the initial value of the step-by-step interpolation, the size of the step-by-step interpolation is adjusted to obtain the target value of the step-by-step interpolation.

[0022] In an implementation of the first aspect, adjusting the correction amount based on threshold limit information for the correction amount to obtain a target correction amount includes:

[0023] Detecting whether the correction amount exceeds the threshold range of the threshold limit information, and obtaining a detection result;

[0024] If the detection result indicates that the correction amount exceeds the threshold range, the correction amount is adjusted to obtain a target correction amount, and the target correction amount is within the threshold range.

[0025] In an implementation of the first aspect, the step of adjusting the sampling rates of the fixed sampling rate current waveform and the fixed sampling rate voltage waveform based on the target value of the step-by-step interpolation to obtain a new synchronous sampling waveform includes:

[0026] By means of a first interpolation circuit, based on a target value of the step-by-step interpolation, the sampling rate of the fixed sampling rate voltage waveform is adjusted to generate a new synchronous sampling voltage waveform;

[0027] By means of a second interpolation circuit, based on the target value of the step-by-step interpolation, the sampling rate of the fixed sampling rate current waveform is adjusted to generate a new synchronous sampling current waveform;

[0028] Wherein, the sampling points of the synchronously sampled voltage waveform and the synchronously sampled current waveform are aligned.

[0029] In an implementation of the first aspect, the method further includes: performing harmonic filtering on the voltage waveform to obtain a fundamental voltage with harmonic interference removed;

[0030] When the fundamental voltage crosses zero voltage from positive to negative or from negative to positive, the zero crossing point of the fundamental voltage is extracted.

[0031] In an implementation of the first aspect, generating a fixed sampling rate voltage waveform and a fixed sampling rate current waveform at a specified sampling clock frequency for a specified power grid includes:

[0032] For a specified power grid, the voltage signal is collected at a specified sampling clock frequency through the analog-to-digital converter of the voltage channel to generate a fixed sampling rate voltage waveform;

[0033] The current signal is sampled at the specified sampling clock frequency through the analog-to-digital converter of the current channel to generate a fixed sampling rate current waveform.

[0034] A second aspect of an embodiment of the present application provides a synchronous sampling device, comprising:

[0035] A generating module, for generating a fixed sampling rate voltage waveform and a fixed sampling rate current waveform at a specified sampling clock frequency for a specified power grid;

[0036] A determination module, configured to determine a correction amount of a step-by-step interpolation based on a zero-crossing point of the fixed sampling rate voltage waveform and a sampling point of a synchronously sampled voltage waveform, wherein the sampling point of the synchronously sampled voltage waveform is obtained by interpolation based on an initial value of the step-by-step interpolation, and the step-by-step interpolation represents a time interval between adjacent sampling points;

[0037] A correction module, used for correcting the size of the step-by-step interpolation based on the correction amount and the initial value of the step-by-step interpolation to obtain a target value of the step-by-step interpolation;

[0038] The adjustment module is used to change the sampling rates of the fixed sampling rate current waveform and the fixed sampling rate voltage waveform by interpolation based on the target value of the step-by-step interpolation to obtain a new synchronous sampling waveform.

[0039] A third aspect of an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method described in the first aspect when executing the computer program.

[0040] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described in the first aspect above is implemented.

[0041] A fifth aspect of the embodiments of the present application provides a computer program product, including a computer program, and when the computer program is executed, the method described in the first aspect above is executed.

[0042] In a first aspect of an embodiment of the present application, a fixed sampling rate voltage waveform and a current waveform obtained with the same sampling clock frequency are first used as the data basis for realizing synchronous sampling, thereby ensuring the preliminary synchronization of the voltage waveform and the current waveform; then, a correction amount of the step interpolation is determined according to the error in the number of sampling points of the synchronously sampled voltage waveform between multiple zero crossing points in the fixed sampling rate voltage waveform, and the size of the step interpolation is adjusted accordingly; finally, based on the target value of the step interpolation, the sampling rate of the fixed sampling rate voltage and current waveforms is changed by interpolation to generate a new synchronous sampling waveform. In this way, the frequency change of the voltage can be quickly responded to and the size of the step interpolation can be adjusted in real time to ensure the accuracy of the synchronous sampling.

[0043] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 It is a schematic diagram of the implementation flow of the synchronous sampling method provided in the embodiment of the present application;

[0046] Figure 2 It is a schematic diagram of the implementation flow of the method for determining time error provided in an embodiment of the present application;

[0047] Figure 3 is a flowchart of the implementation of the step-by-step interpolation correction method provided in the embodiment of the present application;

[0048] Figure 4 is another implementation flow chart of the step-by-step interpolation correction method provided in an embodiment of the present application;

[0049] Figure 5 is another implementation flow chart of the step-by-step interpolation correction method provided in an embodiment of the present application;

[0050] Figure 6 is a structural diagram of a synchronous sampling system provided in an embodiment of the present application;

[0051] Figure 7 is a flow chart of a method for generating a synchronous sampling waveform provided in an embodiment of the present application;

[0052] Figure 8 is a flow chart of the zero-crossing detection method provided in an embodiment of the present application;

[0053] Fig. 9 is a schematic diagram of a synchronous sampling device provided in an embodiment of the present application;

[0054] Fig.10 It is a schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0056] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0057] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0058] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0059] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0060] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0061] In one embodiment, Figure 1 As shown, a synchronous sampling method is provided, which is described by taking the method applied to a control device in a synchronous sampling system as an example, and includes the following steps S101 to S104.

[0062] in:

[0063] Step S101 : generating a fixed sampling rate voltage waveform and a fixed sampling rate current waveform at a specified sampling clock frequency for a specified power grid.

[0064] In the application, the control device samples the voltage signal on the specified power grid based on a fixed sampling rate through the voltage channel analog-to-digital converter (ADC) at a specified sampling clock frequency. Each sampling corresponds to a voltage sampling point on the time axis. A voltage waveform with a fixed sampling rate, i.e., a fixed sampling rate voltage waveform, can be obtained through multiple voltage sampling points. Similarly, the controller samples the current signal of the specified power grid based on a fixed sampling rate through the ADC of the current channel at the same specified sampling clock frequency as that on the voltage channel, and obtains multiple current sampling points. A current waveform with a fixed sampling rate, i.e., a fixed sampling rate current waveform, is obtained through multiple current sampling points. The voltage waveform describes the changing trend of the voltage signal over time from a graphical perspective. The current waveform describes the changing trend of the current signal over time from a graphical perspective. It should be noted that the sampling of the current signal and the voltage signal are obtained by interpolation processing based on the initial value of the step-by-step interpolation, and the size of the step-by-step interpolation determines the time interval between two adjacent sampling points.

[0065] In application, if the voltage indicated by the voltage waveform is the fundamental voltage, subsequent operations can be performed directly. If the voltage indicated by the voltage waveform is a voltage with other frequency components superimposed on the fundamental voltage, it is necessary to remove the harmonic interference in the voltage indicated by the voltage waveform to obtain the fundamental voltage.

[0066] Step S102, determining a correction amount of the step interpolation based on the zero crossing point of the fixed sampling rate voltage waveform and the sampling points of the synchronously sampled voltage waveform, wherein the sampling points of the synchronously sampled voltage waveform are obtained by interpolation processing based on the initial values ​​of the step interpolation, and the step interpolation represents the time interval between adjacent sampling points.

[0067] In applications, the voltage waveform is a continuous signal that changes with time, and the sampling point refers to a series of discrete points selected on the time axis. The control device can achieve a refined description of the voltage waveform based on the sampling points. The more sampling points there are, the finer the voltage waveform. The zero crossing point refers to the time point when the voltage value in the voltage signal changes from positive to negative or from negative to positive, marking the end of a complete cycle and the beginning of another cycle. If the sampling point can be closer to the zero crossing point, the turning point of the waveform can be captured more accurately, thereby improving the accuracy of the description of the waveform characteristics. The controller can detect the zero crossing point in the voltage waveform through a comparator. When the voltage signal crosses the zero point, the comparator will output a signal indicating the occurrence of the zero crossing point. It should be noted that since there may be multiple size adjustments for the step interpolation, the initial value of the step interpolation can also be the size of the step interpolation after the last step interpolation adjustment.

[0068] In the application, the fixed sampling rate voltage waveform obtained in step S101 includes multiple zero crossing points, and the control device performs interpolation processing based on the initial value of the step-by-step interpolation to obtain multiple sampling points of the synchronously sampled voltage waveform. The interpolation processing is implemented by a preset interpolation algorithm, such as linear interpolation, quadratic interpolation, etc. The size of the step-by-step interpolation determines the step size of each interpolation processing, that is, the time interval between each new sampling point generated and the previous sampling point.

[0069] In application, the control device determines the correction amount of the step interpolation based on the error between the actual number of sampling points of the synchronous sampling waveform obtained by interpolation within multiple zero-crossing points of the fixed sampling rate voltage waveform and the preset theoretical number.

[0070] Exemplarily, 11 in-phase zero-crossing points can determine 10 complete cycles. Assuming that 64 sampling points need to be collected in one cycle, but only 639 are collected in the current 10 complete cycles, then based on the initial value of the step-by-step interpolation, the correction amount of the step-by-step interpolation required to collect 640 sampling points is determined.

[0071] Step S103, based on the correction amount and the initial value of the step interpolation, correct the size of the step interpolation to obtain the target value of the step interpolation.

[0072] In the application, the control device adjusts the size of the step interpolation according to the correction amount of the step interpolation and the initial value of the step interpolation to obtain the target value of the step interpolation. The target value of the step interpolation is used as the step size of the interpolation algorithm in the next sampling cycle. The adjustment of the step interpolation is to make the output speed of the synchronous sampling waveform match the actual change speed of the fundamental voltage, thereby ensuring the accuracy of the synchronous sampling.

[0073] In the application, the control device can obtain the correction amount according to the preset first mapping relationship by taking the correction amount as the input of the first mapping relationship. The first mapping relationship is used to indicate the association relationship between the target value of the step-by-step interpolation, the correction amount, and the initial value of the step-by-step interpolation.

[0074] Step S104 , based on the step-by-step interpolation target value, the sampling rates of the fixed sampling rate current waveform and the fixed sampling rate voltage waveform are changed by interpolation to obtain a new synchronous sampling waveform.

[0075] In the application, the control device adjusts the sampling rate of the fixed sampling rate current waveform and the fixed sampling rate voltage waveform in real time through interpolation according to the target value of the step-by-step interpolation to obtain a new synchronous sampling waveform. And as the fundamental voltage frequency changes, the above process is repeated continuously, and the step-by-step interpolation is adjusted in real time to ensure that the synchronous sampling waveform can always keep in sync with the fundamental voltage.

[0076] In this embodiment, the voltage waveform and current waveform obtained with the same sampling clock frequency are first used as the data basis for realizing synchronous sampling, thereby ensuring the preliminary synchronization of the voltage waveform and the current waveform; then, the correction amount of the step interpolation is determined according to the number error of the sampling points of the synchronously sampled voltage waveform between multiple zero-crossing points in the fixed sampling rate voltage waveform, and the size of the step interpolation is adjusted accordingly; finally, based on the target value of the step interpolation, the sampling points of the fixed sampling rate voltage and current waveforms are changed by interpolation to generate a new synchronous sampling waveform, so that the frequency change of the voltage can be quickly responded to and the size of the step interpolation can be adjusted in real time to ensure the accuracy of the synchronous sampling.

[0077] In one embodiment, Figure 2 As shown, the implementation process of step S102 includes the following steps S201 to S204:

[0078] Step S201, extracting the zero-crossing point of the fixed sampling rate voltage waveform.

[0079] In applications, the zero-crossing point is an important characteristic point in the voltage waveform, marking the end of a complete cycle and the beginning of another cycle. At the hardware level, the zero-crossing point detection can be achieved through a dedicated zero-crossing detection circuit. Such circuits usually include components such as comparators, filters, and trigger circuits.

[0080] Step S202 , counting the actual number of sampling points of the synchronously sampled voltage waveform between multiple zero-crossing points of the fixed sampling rate voltage waveform.

[0081] In the application, the control device extracts multiple zero-crossing points of the fixed sampling rate voltage waveform, where every two adjacent zero-crossing points can determine a cycle. Between the multiple zero-crossing points, the actual number of sampling points of the synchronously sampled voltage waveform is interpolated based on the initial value of the step-by-step interpolation.

[0082] Step S203: determining a synchronization error between a voltage waveform with a fixed sampling rate and a voltage synchronous sampling waveform within a fixed time based on an error between the actual number and the theoretical number.

[0083] In an application, the control device determines an error between an actual number and a theoretical number, and based on the error determines a synchronization error between a fixed sampling rate voltage waveform and a voltage synchronous sampling waveform within a fixed time.

[0084] Step S204: determining a correction amount of the step-by-step interpolation based on the synchronization error.

[0085] In the application, the synchronization error is input as a variable into the preset first mapping relationship to determine the correction amount. The correction amount is used to adjust the size of the step interpolation in the preset interpolation method. The first mapping relationship is used to indicate the correlation between the synchronization sampling point error and the correction amount.

[0086] For example, assume that there is a power system in which the fundamental voltage frequency is 50 Hz, the ADC sampling frequency is 1 kHz, and the preset number of synchronous sampling points is 64 points per cycle. If it is counted that there are N_sample=639 synchronous sampling points between 11 in-phase zero crossing points (10 cycles), theoretically there are N_ideal=64*10 synchronous sampling points, and the error Δn of the number of sampling points is N_sample-N_ideal, the error Δn is substituted into the preset first mapping relationship to obtain the correction amount of the step-by-step interpolation.

[0087] In this embodiment, the correction amount of the step interpolation is determined by the error between the actual number and the theoretical number of sampling points of the synchronously sampled voltage waveform between multiple zero-crossing points of the fixed sampling rate voltage waveform, which can significantly improve the sampling accuracy, thereby achieving accurate capture of the voltage waveform characteristics and optimization of synchronous sampling.

[0088] In one embodiment, Figure 3 As shown, the implementation process of step S103 includes the following steps S301 to S302:

[0089] Step S301, obtaining a preset synchronous sampling frequency point number, wherein the synchronous sampling frequency point number represents the number of sampling points of one or more frequencies.

[0090] In applications, the number of synchronous sampling cycle points refers to the number of sampling points in one cycle or a specified number of cycles. The control device can determine the generation of sampling points by interpolation according to the preset number of synchronous sampling cycle points. For example, it can support synchronous sampling waveforms with 64 / 128 / 256 / 512 points per cycle, and support synchronous sampling waveforms with 1024 / 2048 / 4096 points in 10 cycles.

[0091] Step S302, based on the synchronous sampling frequency points, the correction amount and the initial value of the step interpolation, the size of the step interpolation is corrected to obtain the target value of the step interpolation.

[0092] In the application, the adjustment process for the size of the step interpolation is related to the preset number of synchronous sampling frequency points, the correction amount and the initial value of the step interpolation. The control device determines the target value of the step interpolation based on the preset number of synchronous sampling frequency points, the correction amount and the initial value of the step interpolation. The target value of the step interpolation determines the step size of each movement in the interpolation method, that is, the interval between the new sampling point obtained by each interpolation and the previous sampling point. The adjustment principle for the step interpolation is to make the sampling waveform closer to the actual change of the fundamental voltage to maintain synchronization. For example, if the time error indicates that the sampling is delayed, the step interpolation will be appropriately increased (that is, the target value of the step interpolation is greater than the initial value of the step interpolation), otherwise it will be reduced.

[0093] Exemplarily, 11 in-phase zero-crossing points can determine 10 complete cycles. Assuming that 64 sampling points need to be collected in one cycle, but only 639 are collected in the current 10 complete cycles, the goal is to collect 640 sampling points. The correction amount is determined based on the above-mentioned sampling point number error determination method, and combined with the initial value of the step interpolation, the size of the step interpolation that can collect 64 sampling points per cycle is determined.

[0094] In this embodiment, the step interpolation is corrected by obtaining a preset frequency point and combining the correction amount and the initial value of the step interpolation to obtain a target value of the step interpolation. During the entire synchronous sampling process, it is only necessary to adjust the size of the step interpolation to output synchronous sampling waveforms with different frequency points, thereby improving sampling accuracy and synchronization.

[0095] In one embodiment, Figure 4 As shown, the implementation process of step S103 includes the following steps S401 to S402:

[0096] Step S401, adjusting the correction amount based on the threshold limit information for the correction amount to obtain a target correction amount.

[0097] In the application, during the adjustment process, threshold limit information can also be set for the correction amount, and the threshold limit information is used to limit the correction amount to prevent the correction amount from being too large or too small and affecting the stability of the step interpolation. The control device adjusts the correction amount through the preset threshold limit information to obtain the target correction amount.

[0098] Step S402, adjusting the step interpolation based on the target correction amount and the initial value of the step interpolation to obtain the target value of the step interpolation.

[0099] In the application, the control device inputs the target correction amount and the initial value of the step interpolation into the functional relationship between the correction amount, the initial value of the step interpolation and the target value of the step interpolation to determine the target value of the step interpolation. In the next sampling cycle, the interpolation calculation is performed according to the target value of the step interpolation to generate a new sampling point. Repeat the above process: As the fundamental voltage frequency changes, the system will continuously repeat the above process and adjust the step interpolation in real time to ensure that the sampling rate of the synchronous sampling waveform can always keep pace with the fundamental voltage frequency.

[0100] In this embodiment, the correction amount is adjusted based on the threshold limit information of the correction amount to obtain the target correction amount, and the step interpolation is adjusted in combination with the initial value of the step interpolation, and finally the target value of the step interpolation is obtained. While ensuring the reasonable range of the correction amount, the position of the sampling point can be finely adjusted, thereby improving the sampling accuracy and the reliability of signal processing.

[0101] In one embodiment, Figure 5 As shown, the implementation process of step S401 includes the following steps S501 to S502. Among them:

[0102] Step S501, detecting whether the correction amount exceeds the threshold range of the threshold limit information, and obtaining a detection result.

[0103] In the application, the threshold range of the threshold limit information includes first setting the upper and lower limits of the correction amount, which is usually based on the maximum acceptable adjustment range of the system. After the correction amount is calculated, it is checked whether it exceeds the preset threshold range.

[0104] Step S502: If the detection result indicates that the correction amount exceeds the threshold range, the correction amount is adjusted to obtain a target correction amount, and the target correction amount is within the threshold range.

[0105] In the application, the correction amount is adjusted according to the detection result. Specifically, if the correction amount exceeds the threshold range, it is limited to the threshold range. For example, if the calculated correction amount exceeds the maximum threshold of the threshold range, the maximum threshold is used as the correction amount; if it is lower than the minimum threshold of the threshold range, the minimum threshold is used as the correction amount. The correction amount adjusted in combination with the threshold range is always within the threshold range.

[0106] Exemplarily, assuming that the threshold range for the correction amount is ±10%, if the calculated correction amount is +15%, it is limited to +10%; if the calculated correction amount is -12%, it is limited to -10%.

[0107] In this embodiment, by adding a threshold limit to the correction amount, instability and reliability degradation caused by excessive adjustment of the correction amount can be effectively avoided. The threshold limit ensures the stable operation and reliability of synchronous sampling, and can quickly respond and maintain the accuracy of synchronous sampling even when the fundamental frequency fluctuates.

[0108] In one embodiment, Figure 6 The synchronous sampling system shown in the figure includes a first analog-to-digital converter 610 for the current channel, a second analog-to-digital converter 620 for the voltage channel, a fundamental wave filter 621, a zero-crossing point extraction circuit 622, a comparator 623, a step-by-step interpolation determination circuit 624 (also referred to as an interpolation step calculation circuit), a first interpolation circuit 626 adapted to the voltage waveform, a second interpolation circuit 611 adapted to the current waveform, and a sampling time extraction circuit 625. Among them, the first analog-to-digital converter ADC of the voltage channel is used to collect the voltage signal at a specified sampling clock frequency to generate a voltage waveform. The second analog-to-digital converter ADC of the current channel is used to collect the current signal at a specified sampling clock frequency to generate a current waveform. The fundamental wave filter is used to perform harmonic filtering on the voltage waveform to obtain a fundamental wave voltage with harmonic interference removed. The zero-crossing point extraction circuit is used to extract the zero-crossing point from the voltage fixed sampling rate waveform. Between multiple zero-crossing points of the fixed sampling rate voltage waveform, the actual number of sampling points of the synchronously sampled voltage waveform is counted, and the correction amount of the step-by-step interpolation is determined based on the error between the actual number and the theoretical number. The step-by-step interpolation determination circuit is used to adjust the size of the step-by-step interpolation in real time based on the correction amount of the step-by-step interpolation to obtain the target value of the step-by-step interpolation. The first interpolation circuit is used to generate a synchronously sampled voltage waveform based on the target value of the step-by-step interpolation. The second interpolation circuit is used to generate a synchronously sampled current waveform based on the target value of the step-by-step interpolation. It should be noted that the sampling points of the voltage synchronous sampling waveform and the current synchronous sampling waveform are aligned.

[0109] In the synchronous sampling system, the hardware circuit detects the zero-crossing signal of the fundamental voltage of the fixed sampling rate of the power grid as the benchmark for closed-loop control synchronous sampling, calculates the output speed of the synchronous sampling waveform achieved by interpolation and the error of the zero-crossing signal of the fixed sampling rate power grid voltage in real time, and inputs this error signal as a correction into the step of the interpolation module, thereby fine-tuning the sampling rate of the synchronous sampling waveform, realizing the synchronous tracking of the fundamental voltage by the synchronous waveform, and forming a synchronous sampling system of hardware closed-loop control.

[0110] In the application, the entire synchronous sampling system constitutes a hardware closed-loop control synchronous sampling system through precise sampling, filtering, zero-crossing detection, synchronous error calculation and step-by-step interpolation adjustment, realizing synchronous sampling of voltage and current signals, significantly improving measurement accuracy and real-time performance. Its fast response and high reliability are suitable for metering chips that need to output synchronous sampling waveforms for functions such as power quality analysis and load identification.

[0111] In one embodiment, Figure 7 As shown, based on Figure 6 The synchronous sampling system shown, Figure 1 The implementation process of step S104 in the embodiment includes the following steps S701 to S703. Among them:

[0112] Step S701 : Using a first interpolation circuit, based on the target value of the step-by-step interpolation, the sampling rate of the fixed sampling rate voltage waveform is changed by interpolation to generate a synchronous sampling voltage waveform.

[0113] In the application, when sampling the voltage waveform, after obtaining the target value of the step-by-step interpolation, the controller inputs the target value of the step-by-step interpolation into the first interpolation circuit in the new sampling period, and uses the interpolation method to adjust the sampling point of the voltage waveform to obtain a synchronously sampled voltage waveform. The interpolation algorithm can be a variety of interpolation algorithms such as linear interpolation and quadratic interpolation, which can be flexibly selected according to needs.

[0114] Step S702: Using a second interpolation circuit, based on the step-by-step interpolation target value, the sampling points of the fixed sampling rate current waveform are changed by interpolation to generate a synchronous sampling current waveform, wherein the synchronous sampling voltage waveform is aligned with the sampling points of the synchronous sampling current waveform.

[0115] In the application, when sampling the voltage waveform, after obtaining the target value of the step-by-step interpolation, the controller inputs the target value of the step-by-step interpolation into the first interpolation circuit in the new sampling period, and uses the interpolation method to adjust the sampling point of the voltage waveform to obtain a synchronously sampled voltage waveform. The interpolation algorithm can be a variety of interpolation algorithms such as linear interpolation and quadratic interpolation, which can be flexibly selected according to needs. The sampling points of the synchronously sampled voltage waveform and the synchronously sampled current waveform are precisely aligned on the time axis, that is, the voltage signal and the current signal are sampled at the same time, ensuring that their sampling points are located at the same time position.

[0116] In this embodiment, the sampling rates of the fixed sampling rate voltage waveform and the current waveform are adjusted based on the target values ​​of the step-by-step interpolation through the first interpolation circuit and the second interpolation circuit, respectively, to generate aligned synchronously sampled voltage waveforms and synchronously sampled current waveforms, thereby ensuring that the sampling points of the voltage and current signals are precisely aligned, thereby improving the accuracy and reliability of synchronous sampling in the power system, and further optimizing data analysis and control performance.

[0117] In one embodiment, Figure 8 As shown, the implementation process of step S401 includes the following steps S701 to S702:

[0118] Step S701, performing harmonic filtering on the voltage waveform to obtain a fundamental voltage with harmonic interference removed.

[0119] In actual power grids, in addition to the fundamental wave (such as 50Hz or 60Hz), there are also various harmonic components. These harmonic components will interfere with the extraction of zero-crossing signals, thereby affecting the accuracy of synchronous sampling. Therefore, the fundamental wave filter can effectively filter out the unnecessary harmonic components in the ground voltage waveform to obtain the fundamental wave voltage to ensure the accuracy of subsequent zero-crossing point extraction. The fundamental wave filter is a filter specially designed to retain the fundamental frequency component and filter out other frequency components. Common types of fundamental wave filters include bandpass filters, notch filters, etc.

[0120] In the power system, the fundamental voltage usually refers to the sine wave voltage of the standard frequency of the power grid (such as 50Hz or 60Hz). It is the most basic voltage form in the power system, and all other frequency components (such as harmonics) are superimposed on it.

[0121] In the application, you can also use an oscilloscope or other visualization tools to see whether the filtered waveform is closer to the ideal fundamental waveform.

[0122] Step S702: when the fundamental voltage crosses zero voltage from positive to negative or from negative to positive, extract the zero crossing point of the fundamental voltage.

[0123] In the application, the fundamental voltage is compared with the zero voltage to detect the zero crossing point. When the fundamental voltage crosses the zero voltage from positive to negative or from negative to positive, the zero crossing point extraction circuit will generate a zero crossing signal to indicate the occurrence of the zero crossing point. The generation of the zero crossing point can be realized with the help of hardware. A comparator can be used to detect whether the voltage signal crosses the zero point. When the voltage signal crosses the zero point, the comparator will output a signal to indicate the occurrence of the zero crossing point.

[0124] In this embodiment, by performing harmonic filtering on the voltage waveform to extract the pure fundamental voltage and accurately capturing the zero-crossing point when it crosses zero voltage, harmonic interference can be effectively eliminated and the accuracy and reliability of power system monitoring and control can be improved.

[0125] In one embodiment, the implementation process of step S101 includes: for a specified power grid, collecting voltage signals at a specified sampling clock frequency through an analog-to-digital converter of a voltage channel to generate a voltage waveform; collecting current signals at the specified sampling clock frequency through an analog-to-digital converter of a current channel to generate a current waveform.

[0126] In applications, the ADC of the current channel is responsible for converting the current signal into digital form. Usually, a high-speed analog-to-digital converter (ADC) is used to collect voltage signals from a specified power grid with the same specified sampling clock to generate a fixed sampling rate voltage waveform. The voltage waveform describes the change trend of the voltage signal over time from a graphical perspective.

[0127] In applications, the current waveform describes the changing trend of the current signal over time from a graphical perspective. The analog-to-digital converters (ADCs) of the voltage and current channels collect grid signals at the same sampling clock frequency to generate fixed sampling rate voltage and fixed sampling rate current waveforms, such as 32KHz. This means that in each sampling cycle, the voltage and current signals are collected at the same time, ensuring the synchronization of voltage and current data in time.

[0128] The present application also provides a synchronous sampling device for executing the steps in the above-mentioned synchronous sampling method embodiment. Fig. 9 As shown, the synchronous sampling device 900 provided in the embodiment of the present application includes:

[0129] The generating module 910 is used to generate a voltage waveform and a current waveform at a specified sampling clock frequency for a specified power grid.

[0130] The determination module 920 is used to determine the correction amount of the step interpolation based on the zero crossing point of the voltage waveform and the sampling points of the voltage waveform, wherein the sampling points of the voltage waveform are obtained by interpolation processing based on the initial values ​​of the step interpolation, and the step interpolation represents the time interval between adjacent sampling points.

[0131] The correction module 930 is used to correct the size of the step-by-step interpolation based on the correction amount and the initial value of the step-by-step interpolation to obtain the target value of the step-by-step interpolation.

[0132] The adjustment module 940 is used to adjust the sampling points of the current waveform and the voltage waveform respectively based on the target value of the step-by-step interpolation to obtain a synchronous sampling waveform.

[0133] In one embodiment, the determination module is also used to extract the zero-crossing point of the fixed sampling rate voltage waveform; between multiple zero-crossing points of the fixed sampling rate voltage waveform, count the actual number of sampling points of the synchronous sampling voltage waveform; based on the error between the actual number and the theoretical number, determine the synchronization error between the fixed sampling rate voltage waveform and the voltage synchronous sampling waveform within a fixed time; based on the synchronization error, determine the correction amount of the step interpolation.

[0134] In one embodiment, the correction module is also used to obtain a preset number of synchronous sampling frequency points, wherein the number of synchronous sampling frequency points represents the number of sampling points of one or more frequencies; based on the number of synchronous sampling frequency points, the correction amount and the initial value of the step interpolation, the step interpolation is corrected to obtain a target value of the step interpolation.

[0135] In one embodiment, the correction module is further used to adjust the correction amount based on threshold limit information for the correction amount to obtain a target correction amount; and adjust the size of the step interpolation based on the target correction amount and the initial value of the step interpolation to obtain the target value of the step interpolation.

[0136] In one embodiment, the correction module is also used to detect whether the correction amount exceeds the threshold range of the threshold limit information to obtain a detection result; if the detection result indicates that the correction amount exceeds the threshold range, the correction amount is adjusted to obtain a target correction amount, and the target correction amount is within the threshold range.

[0137] In one embodiment, the adjustment module is further used to generate a new synchronously sampled voltage waveform by changing the sampling rate of the fixed sampling rate voltage waveform by interpolation based on the target value of the step-by-step interpolation through a first interpolation circuit; and to generate a new synchronously sampled current waveform by changing the sampling rate of the current waveform by interpolation based on the target value of the step-by-step interpolation through a second interpolation circuit; wherein the sampling points of the synchronously sampled voltage waveform and the synchronously sampled current waveform are aligned.

[0138] In one embodiment, the adjustment module is further used to perform harmonic filtering on the voltage waveform to obtain a fundamental voltage with harmonic interference removed; when the fundamental voltage crosses zero voltage from positive to negative or from negative to positive, the zero crossing point of the fundamental voltage is extracted.

[0139] In one embodiment, the acquisition module is also used to collect voltage signals at a specified sampling clock frequency through the analog-to-digital converter of the voltage channel to generate a voltage waveform for a specified power grid; and collect current signals at the specified sampling clock frequency through the analog-to-digital converter of the current channel to generate a current waveform.

[0140] In applications, each module in the synchronous sampling device may be a software program module, or may be implemented by different logic circuits integrated in a processor, or may be implemented by multiple distributed processors.

[0141] Fig.10 This is a schematic diagram of the structure of an electronic device for implementing a synchronous sampling method provided by an embodiment of the present application. Fig.10 As shown, the electronic device 1000 of this embodiment includes: at least one processor 1010 ( Fig.10Only one is shown in the figure) a processor, a memory 1020, and a computer program 1030 stored in the memory 1020 and executable on the at least one processor 1010, and when the processor 1010 executes the computer program 1030, the steps in any of the above-mentioned embodiments of the synchronous sampling method are implemented.

[0142] The electronic device 1000 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The electronic device 1000 may include, but is not limited to, a processor 1010 and a memory 1020. Those skilled in the art will appreciate that Fig.10 It is only an example of the electronic device 1000 and does not constitute a limitation of the electronic device 1000. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0143] The processor 1010 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0144] In some embodiments, the memory 1020 may be an internal storage unit of the electronic device 1000, such as a hard disk or memory of the electronic device 1000. In other embodiments, the memory 1020 may also be an external storage device of the electronic device 1000, such as a plug-in hard disk, a smart memory card (SmartMedia Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 1000. Further, the memory 1020 may also include both an internal storage unit of the electronic device 1000 and an external storage device. The memory 1020 is used to store an operating system, an application program, a boot loader (BootLoader), data and other programs, such as the program code of the computer program, etc. The memory 1020 may also be used to temporarily store data that has been output or is to be output.

[0145] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0146] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0147] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0148] An embodiment of the present application provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0149] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0150] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0151] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0152] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0153] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0154] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A synchronous sampling method, characterized in that: include: For a specified power grid, generate a fixed sampling rate voltage waveform and a fixed sampling rate current waveform at a specified sampling clock frequency; Determining a correction amount of a step-by-step interpolation based on a zero-crossing point of the fixed sampling rate voltage waveform and a sampling point of a synchronously sampled voltage waveform, wherein the sampling point of the synchronously sampled voltage waveform is obtained by interpolation based on an initial value of the step-by-step interpolation, and the step-by-step interpolation represents a time interval between adjacent sampling points; Based on the correction amount and the initial value of the step-by-step interpolation, the size of the step-by-step interpolation is corrected to obtain a target value of the step-by-step interpolation; Based on the target value of the step-by-step interpolation, the sampling rates of the fixed sampling rate current waveform and the fixed sampling rate voltage waveform are changed by interpolation to obtain a new synchronous sampling waveform.

2. The synchronous sampling method according to claim 1, characterized in that: The step-by-step interpolation correction amount is determined based on the zero-crossing point of the fixed sampling rate voltage waveform and the sampling point of the synchronously sampled voltage waveform, including: Extracting the zero-crossing point of the fixed sampling rate voltage waveform; Between a plurality of zero-crossing points of the fixed sampling rate voltage waveform, counting the actual number of sampling points of the synchronously sampled voltage waveform; Based on the error between the actual number and the theoretical number, determining the synchronization error between the fixed sampling rate voltage waveform and the voltage synchronous sampling waveform within a fixed time; Based on the synchronization error, a correction amount of the step-by-step interpolation is determined.

3. The synchronous sampling method according to claim 1, characterized in that: The step of correcting the size of the step interpolation based on the correction amount and the initial value of the step interpolation to obtain the target value of the step interpolation includes: Obtaining a preset synchronous sampling frequency point number, wherein the synchronous sampling frequency point number represents the number of sampling points of one or more cycles; Based on the synchronous sampling frequency points, the correction amount and the initial value of the step-by-step interpolation, the size of the step-by-step interpolation is corrected to obtain the target value of the step-by-step interpolation.

4. The synchronous sampling method according to claim 1, characterized in that: The step of correcting the size of the step interpolation based on the correction amount and the initial value of the step interpolation to obtain the target value of the step interpolation includes: Based on the threshold limit information for the correction amount, the correction amount is adjusted to obtain a target correction amount; Based on the target correction amount and the initial value of the step-by-step interpolation, the size of the step-by-step interpolation is adjusted to obtain the target value of the step-by-step interpolation.

5. The synchronous sampling method according to claim 4, characterized in that: The step of adjusting the correction amount based on the threshold limit information of the correction amount to obtain the target correction amount includes: Detecting whether the correction amount exceeds the threshold range of the threshold limit information, and obtaining a detection result; If the detection result indicates that the correction amount exceeds the threshold range, the correction amount is adjusted to obtain a target correction amount, and the target correction amount is within the threshold range.

6. The synchronous sampling method according to claim 1, characterized in that: The step-by-step interpolation based target value changes the sampling rates of the fixed sampling rate current waveform and the fixed sampling rate voltage waveform by interpolation to obtain a new synchronous sampling waveform, including: By means of a first interpolation circuit, based on the target value of the step-by-step interpolation, the sampling rate of the fixed sampling rate voltage waveform is changed by interpolation to generate a new synchronous sampling voltage waveform; By means of a second interpolation circuit, based on the target value of the step-by-step interpolation, the sampling rate of the fixed sampling rate current waveform is changed by interpolation to generate a new synchronous sampling current waveform; Wherein, the sampling points of the synchronously sampled voltage waveform and the synchronously sampled current waveform are aligned.

7. The synchronous sampling method according to any one of claims 1 to 6, characterized in that: The method further comprises: Performing harmonic filtering on the voltage waveform to obtain a fundamental voltage with harmonic interference removed; When the fundamental voltage crosses zero voltage from positive to negative or from negative to positive, the zero crossing point of the fundamental voltage is extracted.

8. The synchronous sampling method according to any one of claims 1 to 6, characterized in that: The method of generating a fixed sampling rate voltage waveform and a fixed sampling rate current waveform at a specified sampling clock frequency for a specified power grid includes: For a specified power grid, the voltage signal is collected at a specified sampling clock frequency through the analog-to-digital converter of the voltage channel to generate a fixed sampling rate voltage waveform; The current signal is sampled at the specified sampling clock frequency through the analog-to-digital converter of the current channel to generate a fixed sampling rate current waveform.

9. An electronic device, characterized in that: The electronic device comprises a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the electronic device implements the method as claimed in any one of claims 1 to 8.

10. A computer program product, characterized in that The invention comprises a computer program, which, when being executed, enables the method according to any one of claims 1 to 8 to be performed.

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