A method for preparing a high-verticality BTO waveguide

By combining Si3N4 thin film etching and BTO sol-gel filling with PECVD cladding technology during the fabrication of barium titanate waveguides, the problems of low etching rate and non-uniformity were solved, and a high-verticality BTO waveguide was fabricated, thus improving device performance.

CN119596461BActive Publication Date: 2025-10-21SHAOXING RES INST OF ZHEJIANG UNIV
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Patent Information

Application Number
CN202411751682.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-12-02
Publication Date
2025-10-21
Estimated Expiration
2044-12-02

AI Technical Summary

Technical Problem

In the prior art, barium titanate waveguides have problems such as low etching rate, unevenness, residual by-products and low waveguide angle during the etching process, resulting in insufficient device performance.

Method used

A high-verticality BTO waveguide was fabricated by growing a Si3N4 thin film using low-pressure chemical vapor deposition, combined with CMP and plasma etching, and then transferring the pattern through two etching processes. The etched trenches were filled with BTO sol-gel agent and annealed. Finally, the cladding was grown by PECVD.

Benefits of technology

A BTO waveguide structure with high aspect ratio, high absolute depth, vertical sidewall angle, and smooth sidewalls was achieved, which improved the performance of the modulator.

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Abstract

The application discloses a preparation method of a high-verticality BTO waveguide, which comprises the following steps: S1, growing a Si3N4 film layer; S2, coating a photoresist; S3, etching; S4, pouring a BTO sol-gel agent; S5, annealing; S6, CMP; and S7, growing a cladding layer. The preparation method of the high-verticality BTO waveguide is characterized in that: the pattern is transferred to a quartz substrate through twice etching, the photoresist is removed and the wafer surface is cleaned to remove organic matters; the BTO solution is solidified in the etched groove through a customized mold, and the solution is filled into every corner of the groove through ultrasonic; the thickness and the flatness of the BTO are adjusted through CMP; and the upper cladding layer is grown to prepare the high-verticality BTO waveguide, so that the performance of the modulator is improved, and the barium titanate waveguide structure with high depth-width ratio, high absolute depth, vertical side wall angle and smooth side wall is realized.
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Description

Technical Field

[0001] The present invention belongs to the technical field of waveguide preparation technology, and in particular relates to a method for preparing a high-verticality BTO waveguide. Background Art

[0002] With the development of microelectromechanical systems (MEMS) technology, silicon has begun to emerge in the field of microelectronics as a low-cost, easy-to-process structural material. However, as a functional material, silicon's performance still has many shortcomings. In the field of optoelectronic transmission, a new type of MEMS device, its transmission loss is large. Many different materials have shown better performance (quality factor Q) than silicon. Specifically, in the fields of optical waveguides, microwave technology, sensors, and biochips, devices based on perovskite materials such as lithium niobate and barium titanate have emerged.

[0003] Due to the chemical stability and compact crystal structure of barium titanate materials. Currently, perovskite materials face problems such as difficulty in etching and by-products easily remaining in the etching cavity, resulting in a low reaction rate on its surface and a slow etching process. During the etching process, due to the unevenness of the barium titanate surface (such as defects, impurities, etc.) and the uneven distribution of the etchant, the etching results may be uneven. The by-products produced during the etching process may be difficult to completely remove and remain in the etching cavity or the surface of the material, causing chamber contamination. In addition, the etched barium titanate waveguide will have defects such as a low waveguide angle and rough side walls.

[0004] Therefore, further improvements are made to the above problems. Summary of the Invention

[0005] The main purpose of the present invention is to provide a method for preparing a high-verticality BTO waveguide to achieve a barium titanate waveguide structure with a high aspect ratio, a high absolute depth, a vertical sidewall angle and smooth sidewalls.

[0006] To achieve the above objectives, the present invention provides a method for preparing a high-verticality BTO waveguide, comprising the following steps:

[0007] Step S1: Using low pressure chemical vapor deposition to grow a Si3N4 thin film layer of a predetermined thickness (1 μm) on a quartz substrate (SiO2) to obtain a wafer, and then performing a CMP process to ensure the thickness, surface roughness, and uniformity of the Si3N4 thin film layer;

[0008] Step S2: increasing the adhesion of the surface of the Si3N4 thin film layer and coating it with photoresist;

[0009] Step S3: performing a first etching step, introducing a first etching gas into the process chamber of the etching equipment, and performing plasma etching on the upper Si3N4 thin film layer using the first process parameters; performing a second etching step, introducing a second etching gas into the process chamber of the etching equipment, and performing plasma etching on the lower quartz substrate using the second process parameters;

[0010] Step S4: Use a degumming solution and plasma cleaning to remove residual photoresist, place the etched wafer in a custom-made mold, pour BTO (barium titanate) sol-gel, and simultaneously ultrasonically heat the bottom to facilitate the BTO sol-gel to enter the etched grooves;

[0011] Step S5: After being completely solidified, the BTO sol-gel is placed in an annealing furnace for annealing, and after annealing, the BTO sol-gel is completely solidified into a layer of BTO film;

[0012] Step S6: adjusting the thickness and surface flatness of the BTO film through a CMP process;

[0013] Step S7: using PECVD (plasma enhanced chemical vapor deposition) to grow a cladding layer (boro-phospho-silicate glass (BPSG)) to prepare a BTO waveguide with high verticality, thereby improving the performance of the modulator.

[0014] As a further preferred technical solution of the above technical solution, for the first etching step of step S3, the first process parameters include the lower electrode power and the upper electrode power, the upper electrode power is greater than 1500W, the lower electrode power is greater than 100W, and the etching time is determined by the thickness of the Si3N4 thin film layer (it can be over-etched by about 10% to ensure clean etching).

[0015] As a further preferred technical solution of the above technical solution, for the second etching step of step S3, the second process parameters include lower electrode power and upper electrode power, the upper electrode power is greater than 1500W, and the lower electrode power is greater than 200W.

[0016] As a further preferred technical solution of the above technical solution, the first etching gas is a mixed gas of a first fluorine-based gas and Ar, O2, the first fluorine-based gas is CHF3 and CF4, and the ratio of C atoms to F atoms in the first fluorine-based gas is maintained at a preset ratio (between 1:2 and 1:4).

[0017] As a further preferred technical solution of the above technical solution, the second etching gas is a mixed gas of a second fluorine-based gas and Ar, O2, the second fluorine-based gas is C4F8 and CF4, and the ratio of C atoms to F atoms in the second fluorine-based gas is maintained at a preset ratio (between 1:2 and 1:4). BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic flow diagram of the present invention.

[0019] Figure 2 is a schematic diagram of a wafer of the present invention.

[0020] Figure 3 It is a schematic diagram of the pattern after photolithography of the present invention.

[0021] Figure 4 It is a schematic diagram of the first etching step of the present invention.

[0022] Figure 5 It is a schematic diagram of the second etching step of the present invention.

[0023] Figure 6 Schematic diagram of forming a BTO thin film according to the present invention.

[0024] Figure 7 It is a schematic diagram of removing excess BTO film according to the present invention.

[0025] Figure 8 is a schematic diagram of the growth blanket of the present invention.

[0026] The reference numerals include: 1. Si3N4 thin film layer; 2. quartz substrate; 3. photoresist; 4. BTO thin film; 5. cladding. DETAILED DESCRIPTION

[0027] The following description is intended to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are for illustrative purposes only, and those skilled in the art will readily appreciate other obvious variations. The basic principles of the present invention defined in the following description may be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0028] In the preferred embodiment of the present invention, those skilled in the art should note that the low pressure chemical vapor deposition method, CMP, etc. involved in the present invention can be regarded as prior art.

[0029] Preferred embodiment.

[0030] like Figure 1-8 As shown, the present invention discloses a method for preparing a high verticality BTO waveguide, comprising the following steps:

[0031] Step S1: Using low pressure chemical vapor deposition to grow a Si3N4 thin film layer 1 of a predetermined thickness (1 μm) on a quartz substrate 2 (SiO2) to obtain a wafer, and then performing a CMP process to ensure the thickness, surface roughness, and uniformity of the Si3N4 thin film layer 1;

[0032] Step S2: increasing the adhesion of the surface of the Si3N4 thin film layer 1 and coating the photoresist 3;

[0033] Step S3: performing a first etching step, introducing a first etching gas into the process chamber of the etching equipment, and performing plasma etching on the upper Si3N4 thin film layer using the first process parameters; performing a second etching step, introducing a second etching gas into the process chamber of the etching equipment, and performing plasma etching on the lower quartz substrate using the second process parameters;

[0034] Step S4: Use a degumming solution and plasma cleaning to remove residual photoresist to avoid organic contamination. Place the etched wafer in a custom-made mold and pour BTO (barium titanate) sol-gel. At the same time, ultrasonic heating is applied to the bottom to facilitate the BTO sol-gel to enter the etched grooves.

[0035] Step S5: After being completely solidified, the BTO sol-gel is placed in an annealing furnace for annealing (placed in an annealing furnace for rapid annealing at 800° C. for 5 minutes), and after annealing, the BTO sol-gel is completely solidified into a layer of BTO film 4;

[0036] Step S6: Adjust the thickness and surface flatness of the BTO film 4 by CMP process (excess BTO needs to be thinned by CMP and uniformity is ensured, and Si3N4 can also serve as a polishing stop layer to prevent the subsequent growth of silicon oxide film from being uniform);

[0037] Step S7: using PECVD (plasma enhanced chemical vapor deposition) to grow the cladding layer 5 (Boro-phospho-silicate glass (BPSG)) to prepare a BTO waveguide with high verticality, thereby improving the performance of the modulator.

[0038] Specifically, for the first etching step in step S3, the first process parameters include the lower electrode power and the upper electrode power, the upper electrode power is greater than 1500W, the lower electrode power is greater than 100W, and the etching time is determined by the thickness of the Si3N4 thin film layer (about 10% can be overetched to ensure clean etching), wherein:

[0039] Upper electrode power: 1500~2000W;

[0040] Lower electrode power: 100~300W;

[0041] Cavity pressure: 5-10mT;

[0042] CF4 flow rate: 20-40 sccm;

[0043] CHF3 flow rate: 40~80sccm;

[0044] Ar flow rate is: 10~40sccm.

[0045] More specifically, for the second etching step of step S3, the second process parameters include the lower electrode power and the upper electrode power, the upper electrode power is greater than 1500W, and the lower electrode power is greater than 200W, wherein:

[0046] Upper electrode power: 1500~2000W;

[0047] Lower electrode power: 100~400W;

[0048] Cavity pressure: 5-10mT;

[0049] CF4 flow rate: 10~80sccm;

[0050] C4F8 flow rate: 40~200sccm;

[0051] O2 flow rate is: 10~40sccm.

[0052] Furthermore, the first etching gas is a mixed gas of a first fluorine-based gas and Ar and O2 (one of Ar and O2 or a mixture of both), the first fluorine-based gas is CHF3 and CF4, and the ratio of C atoms to F atoms in the first fluorine-based gas is maintained at a preset ratio (between 1:2 and 1:4).

[0053] Furthermore, the second etching gas is a mixed gas of a second fluorine-based gas and Ar and O2 (one of Ar and O2 or a mixture of both), the second fluorine-based gas is C4F8 and CF4, and the ratio of C atoms to F atoms in the second fluorine-based gas is maintained at a preset ratio (between 1:2 and 1:4).

[0054] The present invention transfers the pattern through two etching steps. First, a first fluorine-based gas is introduced into the process chamber of the etching equipment, and the upper silicon nitride layer (Si3N4 thin film layer) is plasma-etched using the first process parameters. In the second etching step, a second fluorine-based gas is introduced into the process chamber of the etching equipment, and the silicon oxide layer (quartz substrate) is plasma-etched using the second process parameters. The pattern is transferred to the silicon oxide layer. Degumming and cleaning are performed to remove organic matter on the surface of the wafer. The BTO solution is solidified in the etched grooves using a custom mold, and the solution is filled into every corner of the grooves using ultrasound. The thickness and surface flatness of the BTO are then adjusted using CMP. An upper cladding layer is grown to prepare a BTO waveguide with high verticality, thereby improving the performance of the modulator.

[0055] For the present invention, Si3N4 is grown as a mask layer for etching the quartz substrate and a polishing stop layer for subsequent CMP. Si3N4 is very suitable as a polishing stop layer because of its good chemical stability and mechanical strength. The pattern to be etched is defined by uniform coating (i.e., applying photoresist evenly on the wafer surface) and photolithography technology. Then, these patterns are used as masks to etch Si3N4 and the quartz substrate below. The basic structure of the waveguide is formed. After applying the BTO solution, ultrasound is applied to the bottom of the wafer, and a certain pressure is applied above the wafer for 20 minutes. Through the combination of the vibration effect of the ultrasound and the pressure from above, the BTO solution is better filled into the etched structure, and the formation of bubbles and gaps is reduced, thereby improving the verticality and sidewall smoothness of the waveguide. A BTO waveguide with high verticality and low sidewall roughness is prepared.

[0056] It is worth mentioning that the technical features such as low-pressure chemical vapor deposition and CMP involved in the patent application of this invention should be regarded as prior art. The specific structure, working principle and possible control method and spatial arrangement method of these technical features can be selected by conventional means in the field and should not be regarded as the inventive point of this patent. This patent will not be further elaborated.

[0057] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent replacements for some of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a high verticality BTO waveguide, characterized in that: The following steps are involved: Step S1: using low pressure chemical vapor deposition to grow a Si3N4 thin film layer of a predetermined thickness on a quartz substrate to obtain a wafer, and then performing a CMP process to ensure the thickness, surface roughness, and uniformity of the Si3N4 thin film layer; Step S2: increasing the adhesion of the surface of the Si3N4 thin film layer and coating it with photoresist; Step S3: performing a first etching step, introducing a first etching gas into the process chamber of the etching equipment, and performing plasma etching on the upper Si3N4 thin film layer using the first process parameters; performing a second etching step, introducing a second etching gas into the process chamber of the etching equipment, and performing plasma etching on the lower quartz substrate using the second process parameters; Step S4: Use a degumming solution and plasma cleaning to remove residual photoresist, place the etched wafer in a custom-made mold, pour BTO sol-gel, and simultaneously ultrasonically heat the bottom to facilitate the BTO sol-gel to enter the etched grooves; Step S5: After being completely solidified, the BTO sol-gel is placed in an annealing furnace for annealing, and after annealing, the BTO sol-gel is completely solidified into a layer of BTO film; Step S6: adjusting the thickness and surface flatness of the BTO film through a CMP process; Step S7: Use PECVD to grow the cladding to prepare a BTO waveguide with high verticality, thereby improving the modulator performance.

2. The method for preparing a high verticality BTO waveguide according to claim 1, characterized in that: For the first etching step in step S3, the first process parameters include the lower electrode power and the upper electrode power. The upper electrode power is greater than 1500W, and the lower electrode power is greater than 100W. The etching time is determined by the thickness of the Si3N4 thin film layer.

3. The method for preparing a high verticality BTO waveguide according to claim 2, characterized in that: For the second etching step in step S3 , the second process parameters include the lower electrode power and the upper electrode power. The upper electrode power is greater than 1500W, and the lower electrode power is greater than 200W.

4. The method for preparing a high verticality BTO waveguide according to claim 1, characterized in that: The first etching gas is a mixed gas of a first fluorine-based gas, Ar, and O 2 . The first fluorine-based gas is CHF 3 and CF 4 . The ratio of C atoms to F atoms in the first fluorine-based gas is maintained at a preset ratio.

5. The method for preparing a high verticality BTO waveguide according to claim 1, characterized in that: The second etching gas is a mixed gas of a second fluorine-based gas, Ar, and O2. The second fluorine-based gas is C4F8 and CF4. The ratio of C atoms to F atoms in the second fluorine-based gas is maintained at a preset ratio.

Citation Information

Patent Citations

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