Distributed real-time control system and method based on TSN and FPGA

Abstract

The invention relates to a distributed real-time control system and method based on a TSN and an FPGA. The system comprises a TSN module, a plurality of data acquisition modules and a plurality of control output modules, and the TSN module is used for receiving a control instruction sent by a superior processing system and forwarding the control instruction to the data acquisition modules and the control output modules through a high-speed interface in an assembly line mode. The data acquisition module is used for receiving acquired data returned by each data acquisition module and each control output module through the high-speed interface and transmitting the acquired data to a superior processing system; the data acquisition module is used for acquiring data according to a data acquisition message in the received control instruction, and transmitting the acquired data to the TSN module in an assembly line mode; and the control output module is used for controlling the external equipment in real time according to a control output message in the received control instruction, and transmitting a feedback signal to the TSN module in an assembly line mode. By adopting the system, the requirements of modern industry on efficient and accurate control can be met.

Description

Technical Field

[0001] The present application relates to the field of intelligent control technology, and in particular to a distributed real-time control system and method based on TSN and FPGA. Background Art

[0002] With the development of Industry 4.0 and intelligent manufacturing, fieldbus is increasingly used in industrial network communications. Common fieldbus protocols include EtherCAT, PROFINET, POWERLINK, CC-Link, etc. These protocols are modified based on standard Ethernet to ensure certain real-time requirements and the different requirements of each industrial network level. This requires the deployment of dedicated gateways, routers, switches and other communication equipment. Although traditional Ethernet is popular, it has limitations in real-time data transmission. When the network is congested, it is often unable to effectively transmit data that requires real-time performance.

[0003] In the field of intelligent manufacturing, there is an urgent need for a unified network infrastructure environment that can not only meet the real-time and deterministic requirements of industrial control systems for data transmission, but also be compatible with traditional Ethernet protocols. Therefore, how to achieve low-latency real-time acquisition and control while being compatible with traditional Ethernet protocols is a technical problem that needs to be solved. Summary of the invention

[0004] Based on this, it is necessary to provide a distributed real-time control system and method based on TSN and FPGA to address the above technical problems.

[0005] A distributed real-time control system based on TSN and FPGA, the system comprising:

[0006] TSN module, multiple data acquisition modules and multiple control output modules, each module includes at least one FPGA, the FPGA is used to process signal acquisition, data processing and forwarding in the module; the modules are connected through a VPX backplane, and data is transmitted in series between the modules through a high-speed interface;

[0007] The TSN module is connected to the upper processing system via Ethernet, and is used to receive control instructions sent by the upper processing system and forward them to the data acquisition module and the control output module in the form of a pipeline through a high-speed interface, and is used to receive the collected data returned by each data acquisition module and each control output module through a high-speed interface and transmit it to the upper processing system; the control instructions include data acquisition messages, control output messages and configuration management messages;

[0008] The data acquisition module is used to collect data according to the data acquisition message in the received control instruction, and transmit the collected data to the TSN module in a pipeline manner;

[0009] The control output module is used to perform real-time control on the external device according to the control output message in the received control instruction, and transmit the feedback signal to the TSN module in a pipeline manner.

[0010] A distributed real-time control method based on TSN and FPGA, the method comprising:

[0011] The TSN module receives control instructions sent by the upper processing system and forwards them to the data acquisition module and the control output module in the form of a pipeline through the high-speed interface, and receives the collected data returned by each data acquisition module and each control output module through the high-speed interface and transmits it to the upper processing system; the control instructions include data acquisition messages, control output messages and configuration management messages;

[0012] The data acquisition module collects data according to the data acquisition message in the received control instruction, and transmits the collected data to the TSN module in a pipeline manner;

[0013] The control output module is used to control the external device in real time according to the control output message in the received control instruction, and transmit the feedback signal to the TSN module in a pipeline manner.

[0014] The above-mentioned distributed real-time control system and method based on TSN and FPGA realizes real-time data transmission through TSN technology, which meets the high real-time requirements of industrial control systems. The system uses FPGA for data acquisition and processing, has parallel processing capabilities, and can quickly respond to the real-time processing requirements of large amounts of data. The modules are connected to the VPX backplane through a high-speed interface, and data is transmitted in a pipeline manner, which greatly improves the speed and efficiency of data transmission. The embodiments of the present invention improve real-time performance and reliability, and also have strong flexibility and scalability, which can meet the needs of modern industry for efficient and precise control. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is an application scenario diagram of a distributed real-time control method based on TSN and FPGA in one embodiment;

[0016] Figure 2 A schematic diagram of the structure of a TSN module in one embodiment;

[0017] Figure 3 A schematic diagram of the structure of a data acquisition module in one embodiment;

[0018] Figure 4 It is a structural schematic diagram of a control output module in one embodiment;

[0019] Figure 51 is a flow chart of a distributed real-time control method based on TSN and FPGA in one embodiment;

[0020] Figure 6 The figure is a flowchart of data processing in one embodiment. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] In one embodiment, Figure 1 As shown, a distributed real-time control system based on TSN and FPGA is provided, including:

[0023] TSN module, multiple data acquisition modules and multiple control output modules, each module includes at least one FPGA, which is used to process signal acquisition, data processing and forwarding in the module; the modules are connected through a VPX backplane, and data is transmitted in series between the modules through a high-speed interface;

[0024] The TSN module is connected to the upper processing system via Ethernet, and is used to receive control instructions sent by the upper processing system and forward them to the data acquisition module and the control output module in the form of a pipeline through a high-speed interface, and is used to receive the collected data returned by each data acquisition module and each control output module through a high-speed interface and transmit it to the upper processing system; the control instructions include data acquisition messages, control output messages and configuration management messages;

[0025] The data acquisition module is used to collect data according to the data acquisition message in the received control instruction, and pass the collected data to the TSN module in a pipeline manner;

[0026] The control output module is used to perform real-time control of external devices according to the control output message in the received control instruction, and transmit the feedback signal to the TSN module in a pipeline manner.

[0027] In the above-mentioned distributed real-time control method based on TSN and FPGA, real-time data transmission is realized through TSN technology, which meets the high real-time requirements of industrial control systems, and the system uses FPGA for data acquisition and processing, has parallel processing capabilities, and can quickly respond to the real-time processing requirements of large amounts of data. The modules are connected to the VPX backplane through a high-speed interface, and data is transmitted in a pipeline manner, which greatly improves the speed and efficiency of data transmission. The embodiment of the present invention improves real-time performance and reliability, and also has strong flexibility and scalability, which can meet the needs of modern industry for efficient and precise control.

[0028] In one embodiment, the data acquisition module and the control output module both include a high-speed receiving interface and a high-speed sending interface. The high-speed receiving interface is used for bidirectional communication with the connected upper-level module, and the high-speed sending interface is used for bidirectional communication with the connected lower-level module. The data acquisition module and the control output module receive messages from the upper-level module through the high-speed receiving interface, and forward the data to the lower-level module through the high-speed sending interface after processing. When the data is passed to the last module of the link, the last module passes the data back to the TSN module along the same link to complete the data return.

[0029] like Figure 1 As shown, the data acquisition module is responsible for collecting data from sensors and other devices; the control output module controls the external devices in real time according to the processing results; the TSN communication and data processing module is responsible for receiving the data collected by the data acquisition module for rapid processing and sending the collected data to the upper processing system through the TSN network. At the same time, the control instructions sent by the upper processing system are received through the TSN network and parsed and forwarded to the control output module. The modules are connected through the VPX backplane, and the remote host sends (control output, data acquisition, configuration management) messages to the device TSN module through Ethernet, and then the TSN module forwards to the first submodule through the backplane LVDS interface. The modules are connected in series through the backplane LVDS interface, and the messages are passed down in turn and passed up by the last module, and finally returned to the TSN module and forwarded back to the remote host. Through this structural design, not only the real-time performance and reliability of the system are improved, but also the flexibility and scalability of the system are enhanced.

[0030] In one embodiment, each data acquisition module and each control output module respectively uses PPS+ToD and TSN modules for clock synchronization.

[0031] like Figure 1 As shown, the remote host updates the clock to the TSN module through the Ethernet 802.1AS protocol, and the TSN module updates the modules that send the synchronized clock through the PPS and ToD interfaces of the backplane. PPS (Pulse Per Second) is a pulse signal used for time synchronization. It provides a fixed pulse per second to mark the beginning of each second. This signal is usually generated by devices such as GPS receivers to ensure that the system clock is synchronized with the international standard time (such as UTC). It has high accuracy and can reach the nanosecond level. ToD (Time of Day) is a type of information that provides the current time (such as hours, minutes, seconds, etc.). It is usually used for time synchronization between devices to ensure that the clocks of each device are consistent. The ToD signal is usually transmitted through the network or other protocols to provide the actual time of the system.

[0032] In one embodiment, the FPGA in the TSN module is used to receive and preprocess data transmitted by the high-speed interface, package the preprocessed data into data packets that comply with the TSN protocol, and send them to the Ethernet interface; it is also used to receive control instructions transmitted by the Ethernet interface and parse and transmit them to the high-speed interface.

[0033] like Figure 2 The structural diagram of the TSN module shown in the figure, the TSN module includes an Ethernet communication interface, an LVDS communication interface, an FPGA and a power management unit. The Ethernet communication interface is used to communicate with an external network or host and supports real-time data transmission of the TSN protocol. The LVDS communication interface is responsible for data transmission with other modules (such as data acquisition module and control output module) through a high-speed LVDS interface. The power management unit provides a stable power supply to ensure the normal operation of the entire module. The FPGA is the core processing unit responsible for data processing and protocol conversion. The TSN module is connected to the external TSN network, receives and sends data, integrates the TSN protocol stack, supports real-time data transmission, and ensures low latency and high deterministic transmission of data in the network.

[0034] In one embodiment, the FPGA in the TSN module is also used to filter the received messages to obtain valid message types, which include data read and write messages and configuration management messages. The data read and write messages include data acquisition messages and control output messages. The priority of the message is configured by the filter identification module. When processing the data read and write messages, they are directly forwarded to the downstream module for real-time processing in a pipeline manner. When processing the module configuration message, it is cached in a low-priority queue and forwarded after the high-priority data read and write messages are sent.

[0035] Specifically, for the data of the data acquisition module, the message type of the device is divided into two categories, one is the data read and write message, and the other is the module configuration message. The data read and write message has the highest priority. When receiving the message, the filter filters out other invalid messages of these two categories, and then parses the received message and directly forwards it to other modules. Other modules receive the message to read or insert data, which is forwarded to the lower-level modules in turn and then uploaded from the last module. It will be sent to the corresponding priority queue according to the message type priority. The time slice of time-aware scheduling is set to 50us. After each refresh time slice, the data read and write message is transmitted first, and then the module configuration message is transmitted. The data read and write message can be sent immediately as long as there is data without being cached in the queue during the refresh cycle, and the module configuration message is sent immediately. It will be cached in the low-priority queue and will be sent after the high-priority message is sent. Before sending the module configuration message, the sending time of the current configuration message will be calculated. If the sending time will exceed the next refresh time, the sending will be delayed, thereby ensuring the real-time performance of the system and the low latency of the data message. At the same time, the device sends data through dual network ports redundantly to ensure that the message can still be sent to the host normally after an abnormality occurs in one network. The TSN communication and data processing module also uses pipelined data processing to receive data from other modules, thereby ensuring that the device sends the processed message back to the host after receiving the message sent by the host and forwarding it to each module. The delay time can be controlled within ±200ns (the refresh time of the host to send read and write messages is consistent with the time slice of time-aware scheduling).

[0036] In one embodiment, the FPGA of the data acquisition module includes an analog input signal processing unit and a digital input signal processing unit; the digital input signal processing unit is connected to multiple parallel digital signal acquisition channels, and each digital signal acquisition channel acquires digital signals through an optocoupler; the analog input signal processing unit is connected to multiple parallel analog signal acquisition channels.

[0037] like Figure 3 The structural schematic diagram of the data acquisition module shown in the figure, the data acquisition module includes an LVDS communication interface, multiple parallel digital signal acquisition channels, multiple parallel analog signal acquisition channels, an FPGA and a power management unit.

[0038] Specifically, the multi-channel parallel analog signal acquisition channel uses a high-precision analog-to-digital converter (ADC) to collect analog signals, supports multi-channel simultaneous sampling, and meets the needs of synchronous acquisition of multiple signals. The multi-channel parallel digital signal acquisition channel uses high-speed optocouplers to realize the acquisition of external digital signals, supports multi-channel simultaneous sampling, thereby realizing real-time acquisition, processing and analysis of analog and digital data. Data acquisition The data acquisition module communicates with the TSN communication and data processing module using a high-speed LVDS interface and uses PPS+ToD for clock synchronization (accuracy reaches ±50ns). Each module contains 2 LVDS channels, each of which contains a sending channel and a receiving channel. Data is transmitted in series between modules. If there is a module at the lower level, the current module forwards the message through LVDS2. If the current module is the last module in the link, the message is forwarded through LVDS1. The transmission between modules is similar to pipeline operation. The data acquisition module does not cache the message sent by the TSN communication and data processing module, but reads or inserts data in real time and immediately sends it to the next module through another LVDS channel. The message does not stay between modules, and the last module returns to the TSN communication and data processing module along the cascade link. Each module has only a few nanoseconds of delay from receiving to sending the message, which greatly improves the real-time performance. Synchronizing the clock through the PPS+ToD method can ensure the time certainty of the acquisition.

[0039] In one embodiment, the FPGA controlling the output module includes an analog output signal processing unit and a digital output signal processing unit; the digital output signal processing unit is connected to multiple parallel digital signal output channels, and each digital signal output channel outputs a digital signal through an optocoupler; the analog output signal processing unit is connected to multiple parallel analog signal output channels.

[0040] like Figure 4 The structural schematic diagram of the control output module shown in the figure, the control output module includes an LVDS communication interface, multiple parallel digital signal output channels, multiple parallel analog signal output channels, an FPGA and a power management unit.

[0041] Specifically, the multi-channel parallel analog signal output channel adopts a high-precision digital-to-analog converter (DAC) to output analog signals, and supports multi-channel simultaneous output. The multi-channel parallel digital signal output channel adopts a high-speed optocoupler to realize the output of external digital signal quantity, and supports multi-channel simultaneous output. The control output module communicates through the LVDS interface and synchronizes the clock in the PPS+ToD method like the data acquisition module. The message carries a timestamp and after clock synchronization, its control delay can be controlled within ±100ns, thereby realizing real-time control of the analog and digital signals of the control system. Since the time slice of time-aware scheduling is set to 50us, and the control frequency is often greater than this refresh frequency, a bilinear interpolation algorithm is used in this process to increase the control frequency and perform refined control output of the analog control instructions.

[0042] In one embodiment, the system also includes a power supply; the power supply is connected to the power interface in the TSN module, multiple data acquisition modules and multiple control output modules; the TSN module, multiple data acquisition modules and multiple control output modules all include a power monitoring sub-module; the power monitoring sub-module is respectively connected to the FPGA and the power interface in the module.

[0043] In one embodiment, the high speed interface is a LVDS high speed interface.

[0044] In one embodiment, Figure 5 As shown, a distributed real-time control method based on TSN and FPGA is provided, including the following steps:

[0045] Step 502: receiving control instructions sent by the upper processing system through the TSN module and forwarding them to the data acquisition module and the control output module in the form of a pipeline through the high-speed interface, and receiving the collected data returned by each data acquisition module and each control output module through the high-speed interface and transmitting them to the upper processing system; the control instructions include data acquisition messages, control output messages and configuration management messages;

[0046] Step 504, collecting data according to the data collection message in the received control instruction through the data collection module, and transferring the collected data to the TSN module in a pipeline manner;

[0047] Step 506: The control output module is used to control the external device in real time according to the control output message in the received control instruction, and the feedback signal is transmitted to the TSN module in a pipeline manner.

[0048] In this embodiment, if Figure 6The data processing flow diagram shown in the figure, firstly, the analog and digital signals are collected by the data acquisition module and then sent to the TSN communication and data processing module through the high-speed LVDS interface. The TSN communication and data processing module uses FPGA to implement the 802.1AS, 802.1CB, 802.1Qbv, and 802.Qci protocols in TSN and realizes synchronous acquisition and packaging for multiple acquisition cards and outputs control output messages to multiple control cards at the same time. Specifically, the TSN communication and data processing module performs preliminary processing on the collected data, such as filtering, filtering, diagnosis, etc., packages the processed data into the TSN protocol and uploads it to the remote system through the network interface, receives the control output message in the TSN protocol format sent by the remote system through the network interface, and forwards the parsed control output message to the control output module through the high-speed LVDS interface. The control output module receives the control output message through the high-speed LVDS interface to output analog and digital signals. The system and method of the present invention are suitable for the fields of industrial automation, intelligent manufacturing, etc., and have broad market prospects.

[0049] It should be understood that although Figure 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 5 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0050] For the specific limitations of the distributed real-time control method based on TSN and FPGA, please refer to the limitations of the distributed real-time control system based on TSN and FPGA above, which will not be repeated here.

[0051] Each module in the above-mentioned distributed real-time control system based on TSN and FPGA can be implemented in whole or in part by software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules.

[0052] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A distributed real-time control system based on TSN and FPGA, characterized in that: The system includes a TSN module, multiple data acquisition modules and multiple control output modules, each module includes at least one FPGA, and the FPGA is used to process signal acquisition, data processing and forwarding in the module; the modules are connected through a VPX backplane, and data is transmitted in series between the modules through a high-speed interface; The TSN module is connected to the upper processing system via Ethernet, and is used to receive control instructions sent by the upper processing system and forward them to the data acquisition module and the control output module in the form of a pipeline through a high-speed interface, and is used to receive the collected data returned by each data acquisition module and each control output module through a high-speed interface and transmit it to the upper processing system; the control instructions include data acquisition messages, control output messages and configuration management messages; The data acquisition module is used to collect data according to the data acquisition message in the received control instruction, and transmit the collected data to the TSN module in a pipeline manner; The control output module is used to perform real-time control on the external device according to the control output message in the received control instruction, and transmit the feedback signal to the TSN module in a pipeline manner.

2. The system according to claim 1, characterized in that The data acquisition module and the control output module both include a high-speed receiving interface and a high-speed sending interface, the high-speed receiving interface is used to perform two-way communication with the connected upper-level module, and the high-speed sending interface is used to perform two-way communication with the connected lower-level module; The data acquisition module and the control output module receive messages from the upper-level module through the high-speed receiving interface, and forward the data to the next-level module through the high-speed sending interface after processing. When the data is transmitted to the last module of the link, the last module transmits the data back to the TSN module along the same link to complete the data return.

3. The system according to claim 1, characterized in that Each data acquisition module and each control output module uses PPS+ToD and TSN modules for clock synchronization.

4. The system according to claim 1, characterized in that The FPGA in the TSN module is used to receive and pre-process the data transmitted by the high-speed interface, package the pre-processed data into data packets that comply with the TSN protocol, and send them to the Ethernet interface; It is also used to receive control instructions transmitted by the Ethernet interface and parse them before transmitting them to the high-speed interface.

5. The system according to claim 1, characterized in that The FPGA in the TSN module is also used to screen the received messages to obtain valid message types, which include data read and write messages and configuration management messages, and the data read and write messages include data acquisition messages and control output messages; The priority of the message is configured through the filter identification module. When processing data read and write messages, it is directly forwarded to the downstream module for real-time processing through the pipeline method. When the module configures the message, it is cached in the low-priority queue and waits for the high-priority data read and write messages to be sent before forwarding.

6. The system according to claim 1, characterized in that The FPGA of the data acquisition module includes an analog input signal processing unit and a digital input signal processing unit; the digital input signal processing unit is connected to multiple parallel digital signal acquisition channels, and each digital signal acquisition channel collects digital signals through an optical coupler; the analog input signal processing unit is connected to multiple parallel analog signal acquisition channels.

7. The system according to claim 1, characterized in that The FPGA of the control output module includes an analog output signal processing unit and a digital output signal processing unit; the digital output signal processing unit is connected to multiple parallel digital signal output channels, and each digital signal output channel outputs a digital signal through an optocoupler; the analog output signal processing unit is connected to multiple parallel analog signal output channels.

8. The system according to claim 1, characterized in that The system also includes a power supply; the power supply is connected to the power supply interface in the TSN module, the multiple data acquisition modules and the multiple control output modules; The TSN module, multiple data acquisition modules and multiple control output modules all include a power monitoring submodule; the power monitoring submodule is respectively connected to the FPGA and the power interface in the module.

9. The system according to claim 1, characterized in that The high-speed interface is a LVDS high-speed interface.

10. A method implemented in a distributed real-time control system based on TSN and FPGA as claimed in any one of claims 1 to 9, characterized in that: The method comprises: The TSN module receives control instructions sent by the upper processing system and forwards them to the data acquisition module and the control output module in the form of a pipeline through the high-speed interface, and receives the collected data returned by each data acquisition module and each control output module through the high-speed interface and transmits it to the upper processing system; the control instructions include data acquisition messages, control output messages and configuration management messages; The data acquisition module collects data according to the data acquisition message in the received control instruction, and transmits the collected data to the TSN module in a pipeline manner; The control output module is used to control the external device in real time according to the control output message in the received control instruction, and transmit the feedback signal to the TSN module in a pipeline manner.

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