Debugging circuit and electronic equipment

Abstract

The invention provides a debugging circuit and electronic equipment, and is applied to the technical field of electronic equipment. Wherein a first input end of the error acquisition circuit is connected with a preset voltage source, and a second input end of the error acquisition circuit is connected with a first end of the load point chip; the input end of the clock acquisition circuit is connected with the output end of the error acquisition circuit; the control end of the first switch tube is connected with the output end of the clock acquisition circuit, the first end of the first switch tube is grounded, and the second end of the first switch tube is connected with the second end of the load point chip. The error signal is determined through the voltage at the first end of the load point chip and the preset voltage source, so that the clock modulation signal is determined, the first switching tube is controlled to determine the time proportion of the on time and the off time of the first switching tube according to the duty ratio in the clock modulation signal, and the dynamic response time of the loop is adjusted. In the whole adjusting process, the problem of electronic component replacement in the circuit does not need to be considered, the whole debugging is more convenient, and the circuit is suitable for more scenes.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment, and in particular to a debugging circuit and electronic equipment. Background Art

[0002] With the continuous advancement of electronic equipment technology, the data processing capabilities of electronic equipment have been significantly enhanced. In order to cope with more diverse and complex application scenarios, the current demand on the electronic equipment motherboard has increased significantly, and the system has put forward higher requirements on the dynamic response speed of the power supply. Therefore, in order to ensure the stability of the motherboard output voltage and the complexity of the dynamic response requirements, it has also increased.

[0003] In recent years, a debugging loop stabilization circuit is usually added to the motherboard of electronic equipment to ensure the stability of its output voltage and dynamic response requirements. The debugging of its power loop stability is mainly through changing the output inductance value, reducing or speeding up the loop response speed to suppress the overshoot of the system, or changing the size of the feedforward capacitor to improve the output, and connecting the feedforward capacitor in parallel to reduce the noise of the feedback loop and optimize the output voltage. However, the above methods all adjust the loop stability by replacing the peripheral hardware circuit. However, in actual adjustment, this method needs to constantly try different sizes of capacitors and inductors for the motherboard with fixed panel devices. The combinations should not be too large or too small, which leads to too many limitations of the method and makes debugging more difficult.

[0004] It can be seen that how to provide a debugging circuit with fewer limitations is a problem that those skilled in the art need to solve. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a debugging circuit and electronic equipment, which can solve the problem that the debugging of the circuit by replacing hardware devices in the prior art is relatively limited and difficult to debug.

[0006] In order to solve the above technical problems, on the one hand, an embodiment of the present invention provides a debugging circuit, including an error acquisition circuit, a clock acquisition circuit and a first switch tube;

[0007] The first input terminal of the error acquisition circuit is connected to a preset voltage source, and the second input terminal of the error acquisition circuit is connected to a first terminal of the load point chip, and is used to determine a corresponding error signal according to a preset voltage corresponding to the preset voltage source and a voltage at the first terminal of the load point chip;

[0008] The input end of the clock acquisition circuit is connected to the output end of the error acquisition circuit, and is used to determine the corresponding clock modulation signal according to the error signal, so that the first switch tube determines the time ratio of the on time and the off time of the first switch tube according to the duty cycle in the clock modulation signal, thereby adjusting the loop dynamic response time of the debugging circuit;

[0009] The control end of the first switch tube is connected to the output end of the clock acquisition circuit, the first end of the first switch tube is grounded, and the second end of the first switch tube is connected to the second end of the load point chip.

[0010] In some embodiments, the error acquisition circuit is an error amplifier;

[0011] The first input terminal of the error amplifier is connected to a preset voltage source as the first input terminal of the error acquisition circuit;

[0012] The second input terminal of the error amplifier is connected to the first terminal of the load point chip as the second input terminal of the error acquisition circuit;

[0013] The output end of the error amplifier is connected to the first input end of the clock acquisition circuit as the output end of the error acquisition circuit.

[0014] In some embodiments, a clock acquisition circuit includes: a comparator, a latch, an oscillator, and a first capacitor;

[0015] The first input terminal of the comparator is connected to the output terminal of the error acquisition circuit as the first input terminal of the clock acquisition circuit;

[0016] The second input terminal of the comparator is connected to the first terminal of the oscillator and the first terminal of the first capacitor;

[0017] The output terminal of the comparator is connected to the first terminal of the latch;

[0018] The second terminal of the latch is connected to the second terminal of the oscillator;

[0019] The third terminal of the latch is connected to the control terminal of the first switch tube as the output terminal of the clock acquisition circuit;

[0020] The second end of the first capacitor is grounded as a second output end of the clock acquisition circuit.

[0021] In some embodiments, the clock acquisition circuit further includes: a first resistor, a second resistor, a third resistor, a second switch tube, and a second capacitor;

[0022] The first end of the first resistor is connected to the first end of the second resistor, the first end of the load point chip, the second input end of the error acquisition circuit, and the first end of the second capacitor;

[0023] The second end of the first resistor is connected to the control end of the second switch tube and the first end of the second switch tube, and they serve together as the output end of the debugging circuit;

[0024] The second end of the second resistor is grounded;

[0025] The second end of the second switch tube is connected to the first end of the third resistor;

[0026] The second end of the third resistor is connected to the second end of the second capacitor.

[0027] In some embodiments, further comprising: an input optimization circuit and an output optimization circuit;

[0028] The output end of the input optimization circuit is connected to the third end of the load point chip, and is used to filter the circuit signal in the debugging circuit;

[0029] The output end of the output optimization circuit is connected to the fourth end of the load point chip, and is used for performing capacitance supplementary adjustment on the circuit signal in the debugging circuit.

[0030] In some embodiments, the input optimization circuit includes: a first controller, an electrode plate, a sliding resistor, and a third capacitor;

[0031] The first end of the electrode plate is connected to the control end of the sliding rheostat;

[0032] The second end of the electrode plate is grounded;

[0033] The third end of the electrode plate is connected to the first end of the first controller;

[0034] The first end of the sliding resistor is connected to the first end of the third capacitor, the power supply end and the second end of the first controller;

[0035] The second end of the sliding resistor is connected to the second end of the third capacitor and the third end of the load point chip.

[0036] In some embodiments, the input optimization circuit further includes: a third switch tube;

[0037] The control end of the third switch tube is connected to the second end of the first controller;

[0038] The first end of the third switch tube is connected to the first end of the sliding resistor and the power supply end;

[0039] The second end of the third switch tube is connected to the first end of the third capacitor.

[0040] In some embodiments, the output optimization circuit includes: a second controller and a capacitance compensation circuit;

[0041] A first terminal of the second controller is connected to a first terminal of the capacitance compensation circuit;

[0042] The second end of the second controller is connected to the second end of the capacitance compensation circuit;

[0043] The third terminal of the second controller is connected to the third terminal of the capacitance compensation circuit;

[0044] The fourth end of the second controller is connected to the control end of the second switch tube and the second end of the first resistor;

[0045] The fourth terminal of the capacitance compensation circuit is connected to the third terminal of the load point chip.

[0046] In some embodiments, the capacitance compensation circuit includes: a fourth switch tube, a fifth switch tube, a sixth switch tube, a fourth capacitor, a fifth capacitor and a sixth capacitor;

[0047] The control end of the fourth switch tube is connected to the first end of the second controller as the first end of the capacitance compensation circuit;

[0048] The first end of the fourth switch tube is connected to the first end of the fourth capacitor;

[0049] The control end of the fifth switch tube is connected to the second end of the second controller as the second end of the capacitance compensation circuit;

[0050] The first end of the fifth switch tube is connected to the first end of the fifth capacitor;

[0051] The control end of the sixth switch tube is connected to the third end of the second controller as the third end of the capacitance compensation circuit;

[0052] The first end of the sixth switch tube is connected to the first end of the sixth capacitor;

[0053] The second end of the fourth switch tube is connected to the second end of the fifth switch tube and the second end of the sixth switch tube, and together they serve as the fourth end of the capacitance compensation circuit and are connected to the third end of the load point chip;

[0054] The second end of the fourth capacitor is connected to the second end of the fifth capacitor and the second end of the sixth capacitor, and is grounded.

[0055] On the other hand, the present invention further provides an electronic device, comprising the above-mentioned debugging circuit.

[0056] As can be seen from the above technical scheme, the present invention provides a debugging circuit, including an error acquisition circuit, a clock acquisition circuit and a first switch tube; the first input end of the error acquisition circuit is connected to a preset voltage source, the second input end of the error acquisition circuit is connected to the first end of the load point chip, and is used to determine the corresponding error signal according to the preset voltage corresponding to the preset voltage source and the voltage at the first end of the load point chip; the input end of the clock acquisition circuit is connected to the output end of the error acquisition circuit, and is used to determine the corresponding clock modulation signal according to the error signal, so that the first switch tube determines the time ratio of the on time and the off time of the first switch tube according to the duty cycle in the clock modulation signal, thereby adjusting the loop dynamic response time of the debugging circuit; the control end of the first switch tube is connected to the output end of the clock acquisition circuit, the first end of the first switch tube is grounded, and the second end of the first switch tube is connected to the second end of the load point chip. It can be seen that the present invention determines the error signal by the voltage difference between the voltage at the first end of the load point chip and the preset voltage source, thereby determining the corresponding clock modulation signal according to the error signal, and then controlling the first switch tube to determine the time ratio of its own on time and off time according to the duty cycle in the clock modulation signal, thereby realizing the adjustment of the loop dynamic response time to maintain the stability of the loop dynamic response. When the debugging circuit provided by the present invention adjusts the loop dynamic response time, there is no need to consider the problem of replacing electronic components in the circuit, and the overall debugging is more convenient and applicable to more scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0058] Figure 1 A circuit diagram of a debugging circuit provided by an embodiment of the present invention;

[0059] Figure 2 A circuit diagram of an error acquisition circuit and a clock acquisition circuit provided by an embodiment of the present invention;

[0060] Figure 3 A circuit diagram of an input optimization circuit provided by an embodiment of the present invention;

[0061] Figure 4 A circuit diagram of an output optimization circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0064] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0065] Next, a debugging circuit provided by an embodiment of the present invention is described in detail. Figure 1 A circuit diagram of a debugging circuit provided by an embodiment of the present invention, such as Figure 1 As shown, the debugging circuit includes: an error acquisition circuit 1, a clock acquisition circuit 2 and a first switch tube Q1. In addition, Figure 1 The debugging circuit shown also includes: a preset voltage source Vref and a load point chip (POL chip). The connection relationship of the circuit is: the first input end of the error acquisition circuit 1 is connected to the preset voltage source Vref, and the second input end of the error acquisition circuit 1 is connected to the first end of the load point chip (POL chip); the input end of the clock acquisition circuit 2 is connected to the output end of the error acquisition circuit 1; the control end of the first switch tube Q1 is connected to the output end of the clock acquisition circuit 2, the first end of the first switch tube Q1 is grounded, and the second end of the first switch tube Q1 is connected to the second end of the load point chip (POL chip).

[0066] In a specific embodiment, with the continuous advancement of processor technology and storage devices, the data processing capabilities of the server have been significantly enhanced, and it can cope with more diverse and complex application scenarios. This has led to a significant increase in the current demand on the server motherboard, and at the same time, the system has put forward higher requirements on the dynamic response speed of the power supply. Therefore, the complexity of the conventional debugging power loop to meet these dynamic response requirements has also increased. Since the larger the current passing through the board, the more stringent the layout requirements, the greater the difficulty of the debugging loop. At present, the server design transfers the P5V_HDD power supply from the motherboard to the hard disk backplane. The purpose of this is to reduce the voltage loss when the power cable is powered. By directly providing the P5V_HDD voltage on the hard disk backplane, it can ensure that the hard disk obtains a more stable and sufficient power supply during startup and operation, thereby improving the overall stability. This design means that the input voltage P12V on the hard disk backplane needs to provide a larger output current to cope with the larger current when the hard disk is started. That is, this design transfers the current demand on the motherboard to the backplane, requiring the backplane and the power chip on the backplane to continue to maintain the absolute stability of the loop while bearing a larger current load to ensure the normal operation of the hard disk and other devices.

[0067] However, when testing the backplane of a professional platform, it is found that the loops of some boards are very unstable, especially those using alternative materials. Conventional debugging methods are more difficult to debug, and sometimes the loop cannot be adjusted to a stable state. This is because boards made of alternative materials are needed as a backup in some cases to cope with supply chain disruptions, component shortages or design changes, so the performance is relatively weaker than the preferred main material. The reason for the unstable loop is that the ground plane between the input entering the board through the connector and the output power chip is connected together. Due to the increase in current, the input voltage will jitter when the back-end chip undergoes dynamic load changes, and this jitter will be transmitted to the output end through the ground plane, causing the output voltage to jitter.

[0068] At present, the debugging of power loop stability in the server field is mainly to change the output inductance value, reduce or speed up the loop response speed to suppress the overshoot of the system, or to improve the output by changing the feedforward capacitor size, and to reduce the noise of the feedback loop and optimize the output voltage by connecting the feedforward capacitor in parallel. The above adjustment method is relatively fixed, and it is necessary to constantly try different combinations of capacitors and inductors, which cannot be too large or too small, resulting in too many limitations of the method. If you encounter a board with a fixed layout or a board that cannot change materials, it will be extremely difficult to debug.

[0069] Therefore, the present invention provides a debugging circuit, in which the first input end of the error acquisition circuit 1 is connected to the preset voltage source Vref, and is used to obtain the preset voltage corresponding to the preset voltage source Vref (which can be understood as: reference voltage); the second input end of the error acquisition circuit 1 is connected to the first end of the load point chip (POL chip), and is used to obtain the voltage at the first end of the load point chip (POL chip) (which can be understood as: output voltage), and then the voltage difference between the two voltages is determined based on the function of the error acquisition circuit 1 itself, and then the corresponding error signal is generated. The input end of the clock acquisition circuit 2 is connected to the output end of the error acquisition circuit 1, and is used to obtain the error signal generated by the error acquisition circuit 1, and then the clock acquisition circuit 2 adjusts the duty cycle of the signal according to the amplitude of the error signal, and the amplitude is related to the deviation between the output voltage and the reference voltage, so as to generate a clock modulation signal. The control end of the first switch tube Q1 is connected to the output end of the clock acquisition circuit 2, the first end of the first switch tube Q1 is grounded, and the second end of the first switch tube Q1 is connected to the second end of the load point chip (POL chip). The first switch tube Q1 obtains the clock modulation signal through the control end, and then determines the time ratio of its own on time and off time based on the duty cycle in the clock modulation signal, thereby adjusting the loop dynamic response time of the debugging circuit, and then controlling the average voltage of the final load end to achieve precise control.

[0070] Among them, since the load point chip (POL chip) is a BUCK circuit composed of various devices, it is possible to improve the dynamic response by adjusting the internal circuit parameters. The present invention needs to write the configuration file into the load point chip (POL chip) so that the corresponding connection end (pin) takes measures to change certain parts related to the loop in the BUCK circuit to achieve dynamic adjustment of the power supply state, thereby improving the overall performance and reliability of the system.

[0071] It can be seen that for a point-of-load chip (POL chip), it includes the following steps:

[0072] Step 1: Configure the point-of-load chip (POL chip).

[0073] Step 2: Pin control circuit devices.

[0074] Step 3: Change the corresponding pin parameters.

[0075] Step 4: Eliminate input noise.

[0076] Step 5: Adjust the loop response.

[0077] Step 6: Test the dynamic response.

[0078] The premise of its use is: in the present invention, it is necessary to determine the operating voltage range V0-V1 required by the load at the load end. When the output voltage is less than V0 or greater than V1 for a period of time, the on and off time of the switch tube is accurately controlled by the debugging circuit.

[0079] It should be noted that the present invention does not limit the specific structures of the error acquisition circuit 1 and the clock acquisition circuit 2, as long as the above functions are met. The specific structures can be set according to the needs of users.

[0080] The first switch tube Q1 may be a MOS tube. When it is a MOS tube, the control end of the first switch tube Q1 is the gate of the MOS tube; the first end of the first switch tube Q1 is the source of the MOS tube; and the second end of the first switch tube Q1 is the drain of the MOS tube.

[0081] As can be seen from the above technical scheme, the present invention provides a debugging circuit, including an error acquisition circuit, a clock acquisition circuit and a first switch tube; the first input end of the error acquisition circuit is connected to a preset voltage source, the second input end of the error acquisition circuit is connected to the first end of the load point chip, and is used to determine the corresponding error signal according to the preset voltage corresponding to the preset voltage source and the voltage at the first end of the load point chip; the input end of the clock acquisition circuit is connected to the output end of the error acquisition circuit, and is used to determine the corresponding clock modulation signal according to the error signal, so that the first switch tube determines the time ratio of the on time and the off time of the first switch tube according to the duty cycle in the clock modulation signal, thereby adjusting the loop dynamic response time of the debugging circuit; the control end of the first switch tube is connected to the output end of the clock acquisition circuit, the first end of the first switch tube is grounded, and the second end of the first switch tube is connected to the second end of the load point chip. It can be seen that the present invention determines the error signal by the voltage difference between the voltage at the first end of the load point chip and the preset voltage source, thereby determining the corresponding clock modulation signal according to the error signal, and then controlling the first switch tube to determine the time ratio of its own on time and off time according to the duty cycle in the clock modulation signal, thereby realizing the adjustment of the loop dynamic response time to maintain the stability of the loop dynamic response. When the debugging circuit provided by the present invention adjusts the loop dynamic response time, there is no need to consider the problem of replacing electronic components in the circuit, and the overall debugging is more convenient and applicable to more scenarios.

[0082] In some embodiments, Figure 2As shown, the error acquisition circuit 1 is an error amplifier Gm. Therefore, its connection relationship is: the first input end of the error amplifier Gm is connected to the preset voltage source Vref as the first input end of the error acquisition circuit 1; the second input end of the error amplifier Gm is connected to the first end (FB pin) of the load point chip (POL chip) as the second input end of the error acquisition circuit 1; the output end of the error amplifier Gm is connected to the first input end of the clock acquisition circuit 2 as the output end of the error acquisition circuit 1.

[0083] In a specific embodiment, the error amplifier Gm obtains a preset voltage (which can be understood as: reference voltage) corresponding to the preset voltage source Vref and a voltage at the first end of the load point chip (POL chip) (which can be understood as: output voltage), and then determines the voltage difference between the two voltages based on the function of the error amplifier Gm itself, and then amplifies them to generate a corresponding error signal.

[0084] The first input terminal of the error amplifier Gm in the present invention may be a non-inverting input terminal of the error amplifier Gm, or may be an inverting input terminal of the error amplifier Gm, which is not limited in the present invention.

[0085] like Figure 2 As shown, the clock acquisition circuit 2 includes: a comparator Cp, a latch T1, an oscillator S and a first capacitor C1. The connection relationship of the circuit is as follows: the first input end of the comparator Cp is connected to the output end of the error acquisition circuit 1 as the first input end of the clock acquisition circuit 2; the second input end of the comparator Cp is connected to the first end of the oscillator S and the first end of the first capacitor C1; the output end of the comparator Cp is connected to the first end of the latch T1; the second end of the latch T1 is connected to the second end of the oscillator S; the third end of the latch T1 is connected to the control end of the first switch tube Q1 as the output end of the clock acquisition circuit 2; the second end of the first capacitor C1 is grounded as the second output end of the clock acquisition circuit 2.

[0086] In a specific embodiment, the function of the comparator Cp is to compare the error signal with the fixed frequency clock signal generated by the oscillator S. The duty cycle of the generated signal is adjusted according to the amplitude of the error signal, and the amplitude is related to the deviation between the output voltage and the reference voltage. The function of the latch T1 is to obtain the clock modulation signal generated by the comparator Cp, stabilize and store the clock modulation signal, and ensure that it remains unchanged before the next clock cycle. The function of the oscillator S is that the oscillator S generates a clock signal with a fixed frequency to provide a reference clock for the comparator Cp. The frequency of this reference clock signal determines the frequency of the clock modulation signal, which in turn affects the switching speed of the first switch tube Q1. The function of the first switch tube Q1 is that the stable clock modulation signal output by the latch T1 subsequently controls the control end of the first switch tube Q1. Since the duty cycle of the clock modulation signal determines the time ratio of the first switch tube Q1 to be turned on and off, the loop dynamic response time of the debugging circuit is adjusted, and the average voltage of the final load end is controlled to achieve precise control.

[0087] besides, Figure 2 In the circuit shown, the clock acquisition circuit 2 also includes: a first resistor R1, a second resistor R2, a third resistor R3, a second switch tube Q2, and a second capacitor C2. The connection relationship of the circuit is: the first end of the first resistor R1 is connected to the first end of the second resistor R2, the first end of the load point chip (POL chip), the second input end of the error acquisition circuit 1, and the first end of the second capacitor C2; the second end of the first resistor R1 is connected to the control end of the second switch tube Q2 and the first end of the second switch tube Q2, and they are jointly used as the output end P5V_HDD of the debugging circuit; the second end of the second resistor R2 is grounded; the second end of the second switch tube Q2 is connected to the first end of the third resistor R3; the second end of the third resistor R3 is connected to the second end of the second capacitor C2.

[0088] In a specific embodiment, in combination with the comparator Cp, the latch T1, the oscillator S, the first capacitor C1 and the error amplifier Gm, it can be known that the voltage at the first end of the load point chip (POL chip) obtained by the error amplifier Gm is the voltage at the connection point of the first resistor R1, the second resistor R2 and the first end of the load point chip (POL chip). The on and off time of the first switch tube Q1 will affect the voltage output by the load point chip (POL chip) through the first end, thereby controlling the average voltage of the final load end to achieve precise control.

[0089] Among them, the third resistor R3 and the second capacitor C2 form a filter, and the cut-off frequency of the filter is just lower than the noise frequency, so as to effectively filter out the noise, make the output waveform smoother, and reduce the output overshoot. The adjustment of the resistance and capacitance of the filter can refer to the adjustment method of the filter at the input end. By changing the conduction time of the second switch tube Q2, the amount of charge entering the circuit can be controlled. According to the definition of capacitance, C=Q / U, where C is capacitance, Q is charge, and U is voltage. By controlling the charge, the equivalent capacitance of the capacitor is adjusted.

[0090] Among them, the second switch tube Q2 can be a MOS tube. When it is a MOS tube, the control end of the second switch tube Q2 is the gate of the MOS tube; the first end of the second switch tube Q2 is the drain of the MOS tube; the second end of the second switch tube Q2 is the source of the MOS tube.

[0091] In addition, since the connection between the error acquisition circuit 1, the clock acquisition circuit 2 and the first switch tube Q1 mainly transmits signals. And relatively speaking, the specific structure of the clock acquisition circuit 2 is not simple, but a bit complicated, and includes: a comparator Cp, a latch T1, an oscillator S, a first capacitor C1, a resistor R1, a second resistor R2, a third resistor R3, a second switch tube Q2 and a second capacitor C2. Therefore, it is easy for electronic components to fail during signal transmission, thereby affecting signal transmission. Therefore, a signal detector can be connected in parallel to the clock acquisition circuit 2, and the first end of the signal detector is connected to the first input end of the comparator Cp, and the second end of the signal detector is connected to the third end of the latch T1.

[0092] The signal detector in its current connection state can detect whether the error signal sent by the error acquisition circuit 1 is faulty at the first time, and can detect whether the clock modulation signal sent by the clock acquisition circuit 2 to the first switch tube Q1 is faulty at the first time, thereby further controlling the conduction or shutdown of the first switch tube Q1.

[0093] The embodiment of the present invention provides a complete error acquisition circuit structure and a clock acquisition circuit structure. Under this structure, in addition to being able to adjust the dynamic response time of the loop to maintain the stability of the dynamic response of the loop, it also achieves precise control of the voltage and filtering of signal noise, making the output waveform smoother and reducing output overshoot.

[0094] In some embodiments, in order to suppress the interference of a certain frequency noise in the input voltage on the output end, the present invention integrates an input optimization circuit at the input end. The cutoff frequency and bandwidth of the input optimization circuit can be adjusted by an internal controller to match the characteristics of the noise. Figure 3As shown, the input optimization circuit includes: a first controller U1, an electrode plate K, a sliding rheostat RH and a third capacitor C3. The connection relationship of the circuit is: the first end of the electrode plate K is connected to the control end of the sliding rheostat RH; the second end of the electrode plate K is grounded; the third end of the electrode plate K is connected to the first end of the first controller U1; the first end of the sliding rheostat RH is connected to the first end of the third capacitor C3, the power supply end P12V and the second end of the first controller U1; the second end of the sliding rheostat RH is connected to the second end of the third capacitor C3 and the third end of the load point chip (POL chip).

[0095] In addition, it also includes: a third switch tube Q3; the control end of the third switch tube Q3 is connected to the second end of the first controller U1; the first end of the third switch tube Q3 is connected to the first end of the sliding resistor RH and the power supply end P12V; the second end of the third switch tube Q3 is connected to the first end of the third capacitor C3.

[0096] In a specific embodiment, the resistance of the sliding rheostat RH can be adjusted by the voltage at the first end of the first controller U1, so as to accurately control the frequency response. By introducing an electrode plate K at the control end of the sliding rheostat RH, and connecting one end thereof to the ground and the other end thereof to the first controller U1, the electric field generated by the electrode plate can be adjusted by using the voltage change on the first controller U1. The adjustment of this electric field can affect the position of the contact of the sliding rheostat RH, so as to accurately control the resistance value of the sliding rheostat RH, thus providing a non-contact resistance value adjustment mechanism, increasing the flexibility and response speed of the input optimization circuit to achieve filtering. The resistance value of the sliding rheostat RH is proportional to the position of the contact connected to the circuit, that is, the length of the metal wire, and the moving distance of the contact in the electric field is proportional to the voltage on the first controller U1. Therefore, based on the corresponding relationship between the voltage on the first controller U1 and the resistance value, the resistance value can be controlled by voltage.

[0097] At the same time, in order to further fine-tune the input optimization circuit to achieve the filtering effect, a third switch tube Q3 can be connected in series to the third capacitor C3. The other end of the first controller U1 controls the on and off of the third switch tube Q3. By accurately controlling the switching time of the third switch tube Q3, the time when the third capacitor C3 is connected to the circuit can be changed, thereby changing its charge amount, thereby adjusting the equivalent capacitance of the capacitor to achieve dynamic adjustment of the capacitance value.

[0098] The third switch tube Q3 may be a MOS tube. When it is a MOS tube, the control end of the third switch tube Q3 is the gate of the MOS tube; the first end of the third switch tube Q3 is the drain of the MOS tube; and the second end of the third switch tube Q3 is the source of the MOS tube.

[0099] The present invention provides an input optimization circuit, wherein the flexible adjustment mechanism embodied in the input optimization circuit enables the input optimization circuit to adapt to various noise environments, effectively reduces the influence of noise on the output voltage, thereby ensuring the stability and reliability of the output voltage.

[0100] In some embodiments, in order to make the dynamic response smoother, multiple switch tubes can be connected in parallel to increase the capacity of the output capacitor, thereby improving the dynamic response of the circuit. Therefore, the present invention also includes an output optimization circuit in the circuit. Figure 4 As shown, the output optimization circuit includes: a second controller U2 and a capacitor compensation circuit, and a fourth switch tube Q4, a fifth switch tube Q5, a sixth switch tube Q6, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6. The connection relationship is as follows: the control end of the fourth switch tube Q4 is connected to the first end of the second controller U1 as the first end of the capacitor compensation circuit; the first end of the fourth switch tube Q4 is connected to the first end of the fourth capacitor C4; the control end of the fifth switch tube Q5 is connected to the second end of the second controller U2 as the second end of the capacitor compensation circuit; the first end of the fifth switch tube Q5 is connected to the first end of the fifth capacitor C5; the control end of the sixth switch tube Q6 is connected to the third end of the second controller U2 as the third end of the capacitor compensation circuit; the first end of the sixth switch tube Q6 is connected to the first end of the sixth capacitor C6; the second end of the fourth switch tube Q4 is connected to the second end of the fifth switch tube Q5 and the second end of the sixth switch tube Q6, and together as the fourth end of the capacitor compensation circuit is connected to the third end of the load point chip (POL chip); the second end of the fourth capacitor C4 is connected to the second end of the fifth capacitor C5 and the second end of the sixth capacitor C6, and is grounded.

[0101] In a specific embodiment, Figure 4 From the connection relationship in the circuit shown, it can be seen that different ends of the second controller U2 are connected to the control ends of the corresponding switch tubes, and its function is to control the on or off of the switch tubes, thereby controlling whether the capacitor connected to the switch tubes is connected to the circuit, thereby realizing the capacitance supplement of the circuit. This design method can provide additional energy storage, because the increased output capacitor can absorb the ability of the output voltage to overshoot or undershoot during dynamic response, so it can cope with the energy demand when the load changes and reduce the fluctuation of the output voltage.

[0102] It should be noted that the fourth switch tube Q4 can be a MOS tube. When it is a MOS tube, the control end of the fourth switch tube Q4 is the gate of the MOS tube; the first end of the fourth switch tube Q4 is the source of the MOS tube; and the second end of the fourth switch tube Q4 is the drain of the MOS tube.

[0103] The fifth switch tube Q5 may be a MOS tube. When it is a MOS tube, the control end of the fifth switch tube Q5 is the gate of the MOS tube; the first end of the fifth switch tube Q5 is the source of the MOS tube; and the second end of the fifth switch tube Q5 is the drain of the MOS tube.

[0104] The sixth switch tube Q6 may be a MOS tube. When it is a MOS tube, the control end of the sixth switch tube Q6 is the gate of the MOS tube; the first end of the sixth switch tube Q6 is the source of the MOS tube; and the second end of the sixth switch tube Q6 is the drain of the MOS tube.

[0105] It should also be noted that the embodiment provided by the present invention is only one possible implementation method, but is not limited to only this implementation method and can be set according to the needs of the user.

[0106] It can be seen that the present invention provides a debugging circuit, including an error acquisition circuit, a clock acquisition circuit and a first switch tube; the first input end of the error acquisition circuit is connected to a preset voltage source, the second input end of the error acquisition circuit is connected to the first end of the load point chip, and is used to determine a corresponding error signal according to a preset voltage corresponding to the preset voltage source and a voltage at the first end of the load point chip; the input end of the clock acquisition circuit is connected to the output end of the error acquisition circuit, and is used to determine a corresponding clock modulation signal according to the error signal, so that the first switch tube determines the time ratio of the on time and the off time of the first switch tube according to the duty cycle in the clock modulation signal, thereby adjusting the loop dynamic response time of the debugging circuit; the control end of the first switch tube is connected to the output end of the clock acquisition circuit, the first end of the first switch tube is grounded, and the second end of the first switch tube is connected to the second end of the load point chip. It can be seen that the present invention determines the error signal by the voltage difference between the voltage at the first end of the load point chip and the preset voltage source, thereby determining the corresponding clock modulation signal according to the error signal, and then controlling the first switch tube to determine the time ratio of its own on time and off time according to the duty cycle in the clock modulation signal, thereby realizing the adjustment of the loop dynamic response time to maintain the stability of the loop dynamic response. The debugging circuit provided by the present invention does not need to consider the problem of replacing electronic components in the circuit when adjusting the dynamic response time of the loop, and the overall debugging is more convenient and applicable to more scenarios. On this basis, when the error acquisition circuit also includes: an input optimization circuit and an output optimization circuit, its debugging circuit can also adapt to various noise environments, effectively reduce the impact of noise on the output voltage, thereby ensuring the stability and reliability of the output voltage, and responding to the energy demand when the load changes, reducing the fluctuation of the output voltage.

[0107] On the other hand, the present invention also provides an electronic device, comprising the above-mentioned debugging circuit, and having the same beneficial effects.

[0108] The working principle of the electronic device is as follows: the error acquisition circuit acquires the preset voltage corresponding to the preset voltage source Vref and the voltage at the first end of the load point chip (POL chip), and then determines the voltage difference between the two voltages based on the function of the error acquisition circuit itself, thereby generating a corresponding error signal. The clock acquisition circuit acquires the error signal generated by the error acquisition circuit, and then the clock acquisition circuit adjusts the duty cycle of the signal according to the amplitude of the error signal, which is related to the deviation between the output voltage and the reference voltage, thereby generating a clock modulation signal. The first switch tube acquires the clock modulation signal through the control end, and then determines the time ratio of its own on time and off time based on the duty cycle in the clock modulation signal, thereby adjusting the loop dynamic response time of the debugging circuit, and then controlling the average voltage of the final load end to achieve precise control.

[0109] It can be seen from the above technical solution that the present invention determines the error signal by the voltage difference between the voltage at the first end of the load point chip and the voltage of the preset voltage source, thereby determining the corresponding clock modulation signal according to the error signal, and then controlling the first switch tube to determine the time ratio of its own on time and off time according to the duty cycle in the clock modulation signal, thereby realizing the adjustment of the loop dynamic response time to maintain the stability of the loop dynamic response. When the electronic device provided by the present invention adjusts the loop dynamic response time, it does not need to consider the problem of replacing electronic components in the circuit, and the overall debugging is more convenient and applicable to more scenarios.

[0110] The above is a detailed introduction to a debugging circuit and an electronic device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A debugging circuit, characterized in that: It includes an error acquisition circuit, a clock acquisition circuit and a first switch tube; The first input terminal of the error acquisition circuit is connected to a preset voltage source, and the second input terminal of the error acquisition circuit is connected to a first terminal of a load point chip, and is used to determine a corresponding error signal according to a preset voltage corresponding to the preset voltage source and a voltage at the first terminal of the load point chip; The input end of the clock acquisition circuit is connected to the output end of the error acquisition circuit, and is used to determine the corresponding clock modulation signal according to the error signal, so that the first switch tube determines the time ratio of the on time and the off time of the first switch tube according to the duty cycle in the clock modulation signal, thereby adjusting the loop dynamic response time of the debugging circuit; The control end of the first switch tube is connected to the output end of the clock acquisition circuit, the first end of the first switch tube is grounded, and the second end of the first switch tube is connected to the second end of the load point chip.

2. The debugging circuit according to claim 1, characterized in that: The error acquisition circuit is an error amplifier; The first input terminal of the error amplifier is connected to the preset voltage source as the first input terminal of the error acquisition circuit; The second input terminal of the error amplifier is connected to the first terminal of the load point chip as the second input terminal of the error acquisition circuit; The output end of the error amplifier is connected to the first input end of the clock acquisition circuit as the output end of the error acquisition circuit.

3. The debugging circuit according to claim 1 or 2, characterized in that: The clock acquisition circuit comprises: a comparator, a latch, an oscillator and a first capacitor; The first input terminal of the comparator is connected to the output terminal of the error acquisition circuit as the first input terminal of the clock acquisition circuit; The second input terminal of the comparator is connected to the first terminal of the oscillator and the first terminal of the first capacitor; The output terminal of the comparator is connected to the first terminal of the latch; The second end of the latch is connected to the second end of the oscillator; The third terminal of the latch is connected to the control terminal of the first switch tube as the output terminal of the clock acquisition circuit; The second end of the first capacitor is grounded as the second output end of the clock acquisition circuit.

4. The debugging circuit according to claim 3, characterized in that: The clock acquisition circuit further includes: a first resistor, a second resistor, a third resistor, a second switch tube and a second capacitor; The first end of the first resistor is connected to the first end of the second resistor, the first end of the load point chip, the second input end of the error acquisition circuit and the first end of the second capacitor; The second end of the first resistor is connected to the control end of the second switch tube and the first end of the second switch tube, and they serve together as the output end of the debugging circuit; The second end of the second resistor is grounded; The second end of the second switch tube is connected to the first end of the third resistor; The second end of the third resistor is connected to the second end of the second capacitor.

5. The debugging circuit according to claim 4, characterized in that: Also included: an input optimization circuit and an output optimization circuit; The output end of the input optimization circuit is connected to the third end of the load point chip, and is used to filter the circuit signal in the debugging circuit; The output end of the output optimization circuit is connected to the fourth end of the load point chip, and is used to perform capacitance supplementary adjustment on the circuit signal in the debugging circuit.

6. The modulation circuit according to claim 5, characterized in that: The input optimization circuit comprises: a first controller, an electrode plate, a sliding resistor and a third capacitor; The first end of the electrode plate is connected to the control end of the sliding resistor; The second end of the electrode plate is grounded; The third end of the electrode plate is connected to the first end of the first controller; The first end of the sliding resistor is connected to the first end of the third capacitor, the power supply end and the second end of the first controller; The second end of the sliding resistor is connected to the second end of the third capacitor and the third end of the load point chip.

7. The debugging circuit according to claim 6, characterized in that: The input optimization circuit further includes: a third switch tube; The control end of the third switch tube is connected to the second end of the first controller; The first end of the third switch tube is connected to the first end of the sliding resistor and the power supply end; The second end of the third switch tube is connected to the first end of the third capacitor.

8. The debugging circuit according to claim 5, characterized in that: The output optimization circuit comprises: a second controller and a capacitance compensation circuit; The first end of the second controller is connected to the first end of the capacitance compensation circuit; The second end of the second controller is connected to the second end of the capacitance compensation circuit; The third terminal of the second controller is connected to the third terminal of the capacitance compensation circuit; The fourth terminal of the second controller is connected to the control terminal of the second switch tube and the second terminal of the first resistor; The fourth terminal of the capacitance compensation circuit is connected to the third terminal of the load point chip.

9. The debugging circuit according to claim 8, characterized in that: The capacitance compensation circuit comprises: a fourth switch tube, a fifth switch tube, a sixth switch tube, a fourth capacitor, a fifth capacitor and a sixth capacitor; The control end of the fourth switch tube is connected to the first end of the second controller as the first end of the capacitance compensation circuit; The first end of the fourth switch tube is connected to the first end of the fourth capacitor; The control end of the fifth switch tube is connected to the second end of the second controller as the second end of the capacitance compensation circuit; The first end of the fifth switch tube is connected to the first end of the fifth capacitor; The control end of the sixth switch tube is connected to the third end of the second controller as the third end of the capacitance compensation circuit; The first end of the sixth switch tube is connected to the first end of the sixth capacitor; The second end of the fourth switch tube is connected to the second end of the fifth switch tube and the second end of the sixth switch tube, and together serve as the fourth end of the capacitance compensation circuit and are connected to the third end of the load point chip; The second end of the fourth capacitor is connected to the second end of the fifth capacitor and the second end of the sixth capacitor, and is grounded.

10. An electronic device, characterized in that: The debugging circuit comprises the debugging circuit described in any one of claims 1 to 9.

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