Low dropout regulator with high stability under light load

Abstract

The invention provides a low dropout linear regulator with high stability under a light load. A current comparison circuit is used for comparing a sampling current of a sampling current source with a reference current; the module logic generation circuit is used for generating a first logic output signal when the sampling current is smaller than the reference current and generating a second logic output signal when the sampling current is larger than the reference current; and the tail current control switch is arranged in the main loop three-stage operational amplifier circuit and is used for being in a conducting state when the first logic output signal is input so as to increase additional tail current and being in a turn-off state when the second logic output signal is input. When the circuit is in a light load state, the sampling current is small, the bias current is large, a high level is output, the high level opens a tail current switch tube of the main loop three-stage operational amplifier circuit, the tail current is increased, the low-frequency gain is reduced, the loop bandwidth is increased, and the stability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a low voltage difference linear regulator with high stability under light load. Background Art

[0002] With the rapid development of science and technology, electronic products have now penetrated into all aspects of our lives, from large household appliances, medical treatment to portable wearable devices. These electronic products all require a stable power supply, and the power management chip closely connects the power supply with the electronic products. As an important branch of the power management chip, the low dropout linear regulator (LDO) is widely used. Nowadays, electronic products have more and more functions, and the scene applications are becoming more and more complex. People may turn on or off multiple functions at the same time. The changes in the power load will become faster and larger, so a high-stability LDO is needed to provide a stable power output. In LDO, the lighter the load, the worse the stability. Starting from this direction, this article designs a circuit design to improve the stability of LDO under light load. Not only does it achieve the problem of improving the stability of LDO under light load, but it also does not increase additional power consumption. Summary of the invention

[0003] Based on the above records, the present invention provides a low voltage drop linear regulator with high stability under light load, aiming to solve the technical problem in the prior art that the stability of LDO under light load needs to be improved.

[0004] A low voltage drop linear regulator with high stability under light load, comprising:

[0005] A current comparison circuit is used to compare the sampling current of the sampling current source with the reference current to obtain a current comparison result;

[0006] A module logic generating circuit, the input end of which is connected to the output end of the current comparison circuit, and is used to: generate a first logic output signal when the current comparison result is that the sampling current is less than the reference current, and generate a second logic output signal when the current comparison result is that the sampling current is greater than the reference current;

[0007] The tail current control switch is arranged in the three-stage operational amplifier circuit of the main loop of the low voltage difference linear regulator, and the input end is connected to the output end of the module logic generation circuit, and is used for: being in the on state when the first logic output signal is input to increase the additional tail current, and being in the off state when the second logic output signal is input.

[0008] Further, the current comparison circuit includes a first PMOS tube, a second PMOS tube, a first NMOS tube, and a second NMOS tube;

[0009] The source of the first PMOS tube and the source of the second PMOS tube are both connected to the operating voltage;

[0010] The drain of the first PMOS tube is connected to the sampling current source, the gate of the first PMOS tube is connected to the drain of the first PMOS tube, and the gate of the first PMOS tube is also connected to the gate of the second PMOS tube;

[0011] The gate of the first NMOS tube is connected to the second bias voltage, and the drain of the first NMOS tube is connected to the drain of the second PMOS tube;

[0012] The gate of the second NMOS tube is connected to the first bias voltage, the drain of the second NMOS tube is connected to the source of the first NMOS tube, and the source of the second NMOS tube is grounded.

[0013] Furthermore, the current comparison circuit also includes a third PMOS tube, a fourth PMOS tube, a first-level inverter and a second-level inverter;

[0014] The input end of the first-stage inverter is connected to the drain of the second NMOS tube, and the output end of the first-stage inverter is connected to the input end of the second-stage inverter;

[0015] The output end of the secondary inverter is used as the output end of the current comparison circuit and is connected to the input end of the module logic generation circuit;

[0016] The source of the third PMOS tube is connected to the working voltage, the gate of the third PMOS tube is connected to the gate of the first PMOS tube, and the drain of the third PMOS tube is connected to the source of the fourth PMOS tube;

[0017] The drain of the fourth PMOS tube is connected to the drain of the second NMOS tube, and the gate of the fourth PMOS tube is connected to the output end of the first-stage inverter.

[0018] Further, the module logic generation circuit includes a fifth PMOS transistor, a sixth PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a first capacitor;

[0019] The source of the fifth PMOS tube and the source of the sixth PMOS tube are connected to the operating voltage;

[0020] The gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube, and the drain of the fifth PMOS tube is connected to the source of the eighth PMOS tube;

[0021] The drain of the sixth PMOS tube is connected to the source of the ninth PMOS tube;

[0022] The gate of the eighth PMOS tube is connected to the output end of the current comparison circuit, and the drain of the eighth PMOS tube is connected to the source of the tenth PMOS tube;

[0023] The gate of the ninth PMOS tube is connected to the gate of the eighth PMOS tube, and the drain of the ninth PMOS tube is connected to the drain of the fifth NMOS tube;

[0024] The gate of the tenth PMOS tube is connected to the gate of the fourth NMOS tube and is connected to a low-level enable logic control signal, and the drain of the tenth PMOS tube is connected to the drain of the fourth NMOS tube;

[0025] The source of the fourth NMOS tube is grounded;

[0026] The gate of the fifth NMOS tube is connected to the gate of the eighth PMOS tube, and the source of the fifth NMOS tube is connected to the drain of the tenth PMOS tube;

[0027] The drain of the sixth NMOS tube is connected to the drain of the tenth PMOS tube, the gate of the sixth NMOS tube is connected to the third bias voltage, and the source of the sixth NMOS tube is grounded;

[0028] The first end of the first capacitor is grounded, and the second end of the first capacitor is connected to the drain of the ninth PMOS tube and serves as the output end of the module logic generation circuit.

[0029] Further, the main loop three-stage operational amplifier circuit includes a first-stage differential amplifier module;

[0030] The tail current control switch includes a first tail current control switch;

[0031] The first tail current control switch is arranged in the first stage differential amplifier module, and is used to be in the on state when the first logic output signal is input to increase the tail current of the first stage differential amplifier module, and is in the off state when the second logic output signal is input.

[0032] Furthermore, the main loop three-stage operational amplifier circuit includes a common source amplifier module, and the input end of the common source amplifier module is connected to the output end of the first stage differential amplifier module;

[0033] The tail current control switch includes a second tail current control switch;

[0034] The second tail current control switch is arranged in the common source amplifier module, and is used to be in an on state when a first logic output signal is input to additionally increase the tail current of the common source amplifier module, and is in an off state when a second logic output signal is input.

[0035] Furthermore, the low voltage drop linear regulator also includes a third NMOS tube;

[0036] The drain of the third NMOS tube is connected to the drain of the second PMOS tube;

[0037] The gate of the third NMOS tube is connected to a one-time programmable low-level enable logic control signal;

[0038] The source of the third NMOS tube is grounded.

[0039] Furthermore, the low voltage drop linear regulator also includes a seventh PMOS tube;

[0040] The drain of the seventh PMOS tube is connected to the drain of the sixth PMOS tube;

[0041] The gate of the seventh PMOS tube is connected to a high level enable logic control signal;

[0042] The source of the seventh PMOS tube is connected to the operating voltage.

[0043] The beneficial technical effect of the present invention is that: by comparing the sampling current with the fixed bias current, when the circuit is lightly loaded, the sampling current is small, the bias current is large, and the output is high level, which turns on the tail current switch tube of the three-stage operational amplifier circuit of the main loop, increases the tail current, reduces the low-frequency gain, increases the loop bandwidth, and increases the stability; as the load increases, the comparator flips, turns off the tail current switch tube, and effectively enhances the stability of the LDO under light load, with the advantages of simple structure, easy adjustment of the comparison point, and no additional power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1-2 It is a schematic diagram of a partial circuit structure of a low voltage difference linear regulator with high stability under light load according to the present invention;

[0045] Figure 3 The figure is a working schematic diagram of a low voltage difference linear regulator with high stability under light load according to the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0048] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0049] See also Figure 1-2 The present invention provides a low voltage drop linear regulator with high stability under light load, comprising:

[0050] A current comparison circuit is used to compare the sampling current of the sampling current source (ISK_SAM) with the reference current to obtain a current comparison result;

[0051] A module logic generating circuit, the input end of which is connected to the output end of the current comparison circuit, and is used to: generate a first logic output signal when the current comparison result is that the sampling current is less than the reference current, and generate a second logic output signal when the current comparison result is that the sampling current is greater than the reference current;

[0052] The tail current control switch is arranged in the three-stage operational amplifier circuit of the main loop of the low voltage difference linear regulator, and the input end is connected to the output end of the module logic generation circuit, and is used for: being in the on state when the first logic output signal is input to increase the additional tail current, and being in the off state when the second logic output signal is input.

[0053] See also Figure 3 , VIN is the LDO input voltage, EN is the enable control of LDO, VOUT is the LDO output voltage, and GND is the ground signal. CIN is the LDO input capacitor, and COUT is the LDO output capacitor. The LDO of the present invention processes the input voltage VIN and outputs the voltage VOUT. The LDO of the present invention comprises a current comparison circuit, a module logic generation circuit, and a main loop three-stage operational amplifier circuit comprising a tail current control switch. The output of the main loop three-stage operational amplifier circuit is VOUT. The sampling current is compared with the fixed bias current. When the circuit is lightly loaded, the sampling current is small, the bias current is large, and the output is a high level. The high level turns on the tail current control switch of the main loop three-stage operational amplifier circuit, increases the tail current, reduces the low-frequency gain, increases the loop bandwidth, and increases the stability; as the load increases, the comparator flips, turns off the tail current switch tube, effectively enhances the stability of the LDO under light load, and has the advantages of simple structure, easy adjustment of the comparison point, and no additional power consumption.

[0054] Furthermore, the current comparison circuit includes a first PMOS transistor (PM1), a second PMOS transistor (PM2), a first NMOS transistor (NM1), and a second NMOS transistor (NM2);

[0055] The source of the first PMOS transistor (PM1) and the source of the second PMOS transistor (PM2) are both connected to the operating voltage (V DD , that is, the power supply voltage);

[0056] The drain of the first PMOS tube (PM1) is connected to the sampling current source, the gate of the first PMOS tube (PM1) is connected to the drain of the first PMOS tube (PM1), and the gate of the first PMOS tube (PM1) is also connected to the gate of the second PMOS tube (PM2);

[0057] The gate of the first NMOS transistor (NM1) is connected to the second bias voltage (VBIAS1), and the drain of the first NMOS transistor (NM1) is connected to the drain of the second PMOS transistor (PM2);

[0058] The gate of the second NMOS tube (NM2) is connected to the first bias voltage (VBIAS0), the drain of the second NMOS tube (NM2) is connected to the source of the first NMOS tube (NM1), and the source of the second NMOS tube (NM2) is grounded (GND).

[0059] Furthermore, the current comparison circuit also includes a third PMOS tube (PM3), a fourth PMOS tube (PM4), a first-level inverter (INV1) and a second-level inverter (INV2);

[0060] The input end of the first-stage inverter (INV1) is connected to the drain of the second NMOS tube (NM2), and the output end of the first-stage inverter (INV1) is connected to the input end of the second-stage inverter (INV2);

[0061] The output end of the secondary inverter (INV2) is used as the output end of the current comparison circuit and is connected to the input end of the module logic generation circuit;

[0062] The source of the third PMOS tube (PM3) is connected to the operating voltage (V DD ), a gate of the third PMOS tube (PM3) is connected to the gate of the first PMOS tube (PM1), and a drain of the third PMOS tube (PM3) is connected to the source of the fourth PMOS tube (PM4);

[0063] The drain of the fourth PMOS tube (PM4) is connected to the drain of the second NMOS tube (NM2), and the gate of the fourth PMOS tube (PM4) is connected to the output end of the first-stage inverter (INV1).

[0064] The third PMOS tube (PM3) and the fourth PMOS tube (PM4) form a hysteresis circuit, so that the current comparison circuit has hysteresis and delay functions, thereby preventing the circuit from fluctuating back and forth near the flip threshold.

[0065] The primary inverter (INV1) and the secondary inverter (INV2) invert the current comparison signal twice, and the final output current comparison signal is the same as the original input current comparison signal. This design can be used to ensure the correct polarity of the signal. The two inverters form a buffer structure, which can enhance the signal driving capability and suppress noise to a certain extent.

[0066] Furthermore, the module logic generation circuit includes a fifth PMOS tube (PM5), a sixth PMOS tube (PM6), an eighth PMOS tube (PM8), a ninth PMOS tube (PM9), a tenth PMOS tube (PM10 ), a fourth NMOS transistor (NM4), a fifth NMOS transistor (NM5), a sixth NMOS transistor (NM6) and a first capacitor (C1);

[0067] The source of the fifth PMOS transistor (PM5) and the source of the sixth PMOS transistor (PM6) are connected to the operating voltage (V DD );

[0068] The gate of the fifth PMOS tube (PM5) is connected to the gate of the sixth PMOS tube (PM6), the gate of the fifth PMOS tube (PM5) is connected to the drain of the fifth PMOS tube (PM5), and the drain of the fifth PMOS tube (PM5) is connected to the source of the eighth PMOS tube (PM8);

[0069] The drain of the sixth PMOS tube (PM6) is connected to the source of the ninth PMOS tube (PM9);

[0070] The gate of the eighth PMOS tube (PM8) is connected to the output end of the current comparison circuit, and the drain of the eighth PMOS tube (PM8) is connected to the tenth PMOS tube (PM 10 ) source;

[0071] The gate of the ninth PMOS transistor (PM9) is connected to the gate of the eighth PMOS transistor (PM8), and the drain of the ninth PMOS transistor (PM9) is connected to the drain of the fifth NMOS transistor (NM5);

[0072] The tenth PMOS tube (PM 10 ) is connected to the gate of the fourth NMOS tube (NM4), and is connected to the low level enable logic control signal (EN_L), the tenth PMOS tube (PM 10 ) is connected to the drain of the fourth NMOS tube (NM4);

[0073] The source of the fourth NMOS tube (NM4) is grounded (GND);

[0074] The gate of the fifth NMOS transistor (NM5) is connected to the gate of the eighth PMOS transistor (PM8), and the source of the fifth NMOS transistor (NM5) is connected to the tenth PMOS transistor (PM 10 ) of the drain;

[0075] The drain of the sixth NMOS transistor (NM6) is connected to the tenth PMOS transistor (PM 10 ), a drain of a sixth NMOS tube (NM6) is connected to a third bias voltage (VBIAS2), and a source of the sixth NMOS tube (NM6) is grounded (GND);

[0076] The first end (cathode end) of the first capacitor (C1) is grounded (GND), and the second end (anode end) of the first capacitor (C1) is connected to the drain of the ninth PMOS tube (PM9) and serves as the output end of the module logic generation circuit. Further, the main loop three-stage operational amplifier circuit includes a first-stage differential amplifier module;

[0077] The tail current control switch includes a first tail current control switch;

[0078] The first tail current control switch is arranged in the first stage differential amplifier module, and is used to be in the on state when the first logic output signal is input to increase the tail current of the first stage differential amplifier module, and is in the off state when the second logic output signal is input.

[0079] Furthermore, the main loop three-stage operational amplifier circuit includes a common source amplifier module, and the input end of the common source amplifier module is connected to the output end of the first stage differential amplifier module;

[0080] The tail current control switch includes a second tail current control switch;

[0081] The second tail current control switch is arranged in the common source amplifier module, and is used to be in an on state when a first logic output signal is input to additionally increase the tail current of the common source amplifier module, and is in an off state when a second logic output signal is input.

[0082] The output high-level signal, i.e., the first logic output signal, turns on the tail current control switches of the first-stage differential amplifier circuit and the second-stage common-source amplifier circuit of the three-stage operational amplifier circuit of the main loop, increases the first-stage and second-stage tail currents, reduces the low-frequency gain, increases the loop bandwidth, and improves the stability; as the load increases, the comparator flips and turns off the first-stage and second-stage tail current control switches of the main operational amplifier.

[0083] Specifically, the first-stage differential amplifier module includes: an eleventh PMOS tube (M1), a twelfth PMOS tube (M2), a seventh NMOS tube (M3) and an eighth NMOS tube (M4), and the first tail current control switch is a ninth NMOS tube (M6);

[0084] The source of the eleventh PMOS tube (M1) and the source of the twelfth PMOS tube (M2) are connected to the operating voltage (VDD);

[0085] The gate of the eleventh PMOS tube (M1) is connected to the gate of the twelfth PMOS tube (M2), and is also connected to the drain of the eleventh PMOS tube (M1);

[0086] The drain of the seventh NMOS tube (M3) is connected to the drain of the eleventh PMOS tube (M1);

[0087] The gate of the seventh NMOS tube (M3) is connected to the reference voltage (VREF);

[0088] The source of the seventh NMOS transistor (M3) is grounded to form a tail current I7;

[0089] The drain of the eighth NMOS tube (M4) is connected to the drain of the twelfth PMOS tube (M2);

[0090] The gate of the eighth NMOS transistor (M4) is connected to a clamping voltage (VFB);

[0091] The source of the eighth NMOS tube (M4) is connected to the source of the seventh NMOS tube (M3);

[0092] The drain of the ninth NMOS tube (M6) is connected to the source of the eighth NMOS tube (M4);

[0093] The gate of the ninth NMOS transistor (M6) is connected to the second end of the first capacitor (C1) to receive the logic output signal (LIGHT_RESPONSE), and the source of the ninth NMOS transistor (M6) is grounded.

[0094] When the logic output signal (LIGHT_RESPONSE) is at a high level, that is, the first logic output signal, the ninth NMOS transistor (M6) is turned on as the first tail current control switch to generate an additional tail current I8 for the first stage differential amplifier module.

[0095] Specifically, the second-stage common-source amplifier module includes: a thirteenth PMOS tube (M5), and the second tail current control switch is a tenth NMOS tube (M7);

[0096] The source of the thirteenth PMOS tube (M5) is connected to the operating voltage (V DD );

[0097] The gate of the thirteenth PMOS tube (M5) is connected to the drain of the twelfth PMOS tube (M2);

[0098] The drain of the thirteenth PMOS tube (M5) is grounded (GND), forming a tail current I9 of the second-stage common-source amplifier module;

[0099] The drain of the tenth NMOS transistor (M7) is connected to the drain of the thirteenth PMOS transistor (M5), the source of the tenth NMOS transistor (M7) is grounded, and the gate of the tenth NMOS transistor (M7) is connected to the second end of the first capacitor (C1) to receive the logic output signal (LIGHT_RESPONSE).

[0100] When the logic output signal (LIGHT_RESPONSE) is at a high level, that is, the first logic output signal, the tenth NMOS transistor (M7) is turned on as the second tail current control switch to generate an additional tail current I10 for the second-stage common-source amplifier module.

[0101] Specifically, the third stage circuit of the main loop three-stage operational amplifier circuit is a power stage circuit, the input end of the third stage power stage circuit is connected to the output end of the second stage common source amplifier module, and the output end of the third stage power stage circuit outputs a voltage VOUT.

[0102] The third power stage circuit includes: a fourteenth PMOS tube (M P )、first resistor (R1), second resistor (R2), third resistor (R L )、The fourth resistor (R EFR ) and the second capacitor (C L );

[0103] Fourteenth PMOS tube (M P ) source connected to the operating voltage (V DD );

[0104] Fourteenth PMOS tube (M P ) has a gate connected to the drain of a thirteenth PMOS tube (M5);

[0105] Fourteenth PMOS tube (M P ) has a drain connected to a first end of a first resistor (R1); a fourteenth PMOS tube (M P ) as the output terminal of the output voltage (VOUT);

[0106] The second end of the first resistor (R1) is also connected to the first end of the second resistor (R2), the third resistor (R L ) first end, the fourth resistor (R EFR ) first end;

[0107] A second end of the second resistor (R2) is grounded;

[0108] The third resistor (R L )'s second end is grounded;

[0109] The fourth resistor (R EFR ) is connected to the second end of the second capacitor (C L ) first end;

[0110] The second capacitor (C L ) is grounded.

[0111] The second end of the first resistor (R1) forms a clamping voltage (VFB) as an input end of the gate of the eighth NMOS transistor (M4).

[0112] Furthermore, the low voltage dropout linear regulator further includes a third NMOS tube (NM3);

[0113] The drain of the third NMOS tube (NM3) is connected to the drain of the second PMOS tube (PM2);

[0114] The gate of the third NMOS tube (NM3) is connected to a one-time programmable low-level enable logic control signal (EN_OTP_L);

[0115] The source of the third NMOS transistor (NM3) is grounded (GND).

[0116] Furthermore, the low voltage dropout linear regulator further includes a seventh PMOS tube (PM7);

[0117] The drain of the seventh PMOS tube (PM7) is connected to the drain of the sixth PMOS tube (PM6);

[0118] The gate of the seventh PMOS tube (PM7) is connected to a high level enable logic control signal (EN_H);

[0119] The source of the seventh PMOS transistor (PM7) is connected to the operating voltage (V DD ).

[0120] EN_L is a low-level enable logic control signal, which is low when the circuit works normally; EN_H is a high-level enable logic control signal, which is high when the circuit works normally; EN_OTP_L is a one-time programmable low-level enable logic control signal, which is controlled by enable and OTP and is low when the circuit works normally; ISK_SAM is a bias current source signal, sampling the power tube current; VBIAS0, VBIAS1, and VBIAS2 are bias voltage signals; LIGHT_RESPONSE is a logic output signal; VDD is the power supply voltage, and GND is the power ground.

[0121] In the present invention, the seventh PMOS tube (PM7), the third NMOS tube (NM3), and the fourth NMOS tube (NM4) are switch tubes, and are all turned off when the circuit works normally.

[0122] In the present invention, when the circuit is working normally and is lightly loaded, the current of the sampling current source is I1, and a mirror current I2 is formed by mirroring. The mirror current I2 is compared with the bias current I3 generated by NM1. When the sampling current I1 is lightly loaded, the bias current I3 is greater than the sampling current I1, and point A is at a low level. After being inverted twice by the first-level inverter INV1 and the second-level inverter INV2, point B is still at a low level. PM8 and PM9 are turned on, and PM5, PM8, PM 10A path is formed with NM6 to generate bias current I5. Bias current I5 forms mirror current I6 through mirroring. I6 charges the first capacitor C1. LIGHT_RESPONSE outputs a high level, that is, outputs the first logic output signal, turns on the first-stage differential amplifier circuit of the main loop and the tail current switch tube of the second-stage common source circuit (such as Figure 2 (As shown in the figure, in addition to the tail currents I7 and I9, additional tail currents I8 and I10 are added to increase the tail current, which can reduce the low-frequency gain, increase the loop bandwidth, and increase the loop stability. As the load increases, the sampling current I1 increases, and the mirror current I2 increases. When I2=I3, it is the flip threshold. When the mirror current I2 is greater than I3, the output of point A is high, the NM5 tube opens to discharge the first capacitor C1, and LIGHT_RESPONSE outputs a low level, which is the second logic output signal, turning off the first and second tail current switch tubes of the main loop. By designing the first capacitor C1, as well as PM3 and PM4, this circuit adds delay and hysteresis functions to the circuit, which can effectively prevent the circuit from switching back and forth near the flip point.

[0123] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A low voltage drop linear regulator with high stability under light load, characterized in that: include: A current comparison circuit is used to compare the sampling current of the sampling current source with the reference current to obtain a current comparison result; A module logic generating circuit, the input end of which is connected to the output end of the current comparison circuit, and is used to: generate a first logic output signal when the current comparison result is that the sampling current is less than the reference current, and generate a second logic output signal when the current comparison result is that the sampling current is greater than the reference current; The tail current control switch is arranged in the main loop three-stage operational amplifier circuit of the low voltage difference linear regulator, and the input end is connected to the output end of the module logic generation circuit, and is used to: be in the on state when the first logic output signal is input to increase the additional tail current, and be in the off state when the second logic output signal is input.

2. A low voltage dropout linear regulator with high stability under light load as claimed in claim 1, characterized in that: The current comparison circuit includes a first PMOS tube, a second PMOS tube, a first NMOS tube, and a second NMOS tube; The source of the first PMOS tube and the source of the second PMOS tube are both connected to the operating voltage; The drain of the first PMOS tube is connected to the sampling current source, the gate of the first PMOS tube is connected to the drain of the first PMOS tube, and the gate of the first PMOS tube is also connected to the gate of the second PMOS tube; The gate of the first NMOS tube is connected to a second bias voltage, and the drain of the first NMOS tube is connected to the drain of the second PMOS tube; The gate of the second NMOS tube is connected to the first bias voltage, the drain of the second NMOS tube is connected to the source of the first NMOS tube, and the source of the second NMOS tube is grounded.

3. A low voltage drop linear regulator with high stability under light load as claimed in claim 2, characterized in that: The current comparison circuit also includes a third PMOS tube, a fourth PMOS tube, a first-level inverter and a second-level inverter; The input end of the first-stage inverter is connected to the drain of the second NMOS tube, and the output end of the first-stage inverter is connected to the input end of the second-stage inverter; The output end of the secondary inverter serves as the output end of the current comparison circuit and is connected to the input end of the module logic generation circuit; The source of the third PMOS tube is connected to the operating voltage, the gate of the third PMOS tube is connected to the gate of the first PMOS tube, and the drain of the third PMOS tube is connected to the source of the fourth PMOS tube; The drain of the fourth PMOS tube is connected to the drain of the second NMOS tube, and the gate of the fourth PMOS tube is connected to the output end of the first-stage inverter.

4. A low voltage dropout linear regulator with high stability under light load as claimed in claim 1, characterized in that: The module logic generation circuit includes a fifth PMOS tube, a sixth PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a first capacitor; The source of the fifth PMOS tube and the source of the sixth PMOS tube are connected to an operating voltage; The gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube, and the drain of the fifth PMOS tube is connected to the source of the eighth PMOS tube; The drain of the sixth PMOS tube is connected to the source of the ninth PMOS tube; The gate of the eighth PMOS tube is connected to the output end of the current comparison circuit, and the drain of the eighth PMOS tube is connected to the source of the tenth PMOS tube; The gate of the ninth PMOS tube is connected to the gate of the eighth PMOS tube, and the drain of the ninth PMOS tube is connected to the drain of the fifth NMOS tube; The gate of the tenth PMOS tube is connected to the gate of the fourth NMOS tube and is connected to a low-level enable logic control signal, and the drain of the tenth PMOS tube is connected to the drain of the fourth NMOS tube; The source of the fourth NMOS tube is grounded; The gate of the fifth NMOS tube is connected to the gate of the eighth PMOS tube, and the source of the fifth NMOS tube is connected to the drain of the tenth PMOS tube; The drain of the sixth NMOS tube is connected to the drain of the tenth PMOS tube, the gate of the sixth NMOS tube is connected to the third bias voltage, and the source of the sixth NMOS tube is grounded; The first end of the first capacitor is grounded, and the second end of the first capacitor is connected to the drain of the ninth PMOS tube and serves as the output end of the module logic generation circuit.

5. A low voltage dropout linear regulator with high stability under light load as claimed in claim 1, characterized in that: The main loop three-stage operational amplifier circuit includes a first-stage differential amplifier module; The tail current control switch comprises a first tail current control switch; The first tail current control switch is arranged in the first-stage differential amplifier module, and is used to be in the on state when the first logic output signal is input to additionally increase the tail current of the first-stage differential amplifier module, and is in the off state when the second logic output signal is input.

6. A low voltage dropout linear regulator with high stability under light load as claimed in claim 5, characterized in that: The main loop three-stage operational amplifier circuit comprises a common-source amplifier module, the input end of the common-source amplifier module is connected to the output end of the first-stage differential amplifier module; The tail current control switch includes a second tail current control switch; The second tail current control switch is arranged in the common source amplifier module, and is used to be in the on state when the first logic output signal is input to additionally increase the tail current of the common source amplifier module, and is in the off state when the second logic output signal is input.

7. A low voltage dropout linear regulator with high stability under light load as claimed in claim 2, characterized in that: The low voltage drop linear regulator also includes a third NMOS tube; The drain of the third NMOS tube is connected to the drain of the second PMOS tube; The gate of the third NMOS tube is connected to a one-time programmable low-level enable logic control signal; The source of the third NMOS tube is grounded.

8. A low voltage drop linear regulator with high stability under light load as claimed in claim 4, characterized in that: The low voltage drop linear regulator also includes a seventh PMOS tube; The drain of the seventh PMOS tube is connected to the drain of the sixth PMOS tube; The gate of the seventh PMOS tube is connected to a high level enable logic control signal; The source of the seventh PMOS tube is connected to the operating voltage.

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