Hybrid random number generator based on FPGA
By designing a hybrid random number generator based on FPGA, combining true random number sampling and chaotic model algorithm, the problem of difficulty in generating high-quality true random numbers in the prior art is solved, and the generation of high-complexity random numbers and efficient utilization of FPGA resources are realized.
Patent Information
- Application Number
- CN202411468230.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-03-11
AI Technical Summary
It is difficult to design a hybrid random number generator in the prior art that can effectively generate high-quality true random numbers. Especially when using simple true random number generators and low-order chaotic structures, it is difficult to ensure high-complexity random number generation.
A hybrid random number generator based on FPGA is designed, including a true random number generator module, a chaotic state update module and a chaotic random number generator module. Through the combination of true random number sampling and chaotic model algorithm, a high random number generation is achieved.
It realizes the use of simple entropy sources and low-order chaotic algorithms to generate high-complexity random numbers, improves the efficiency of FPGA resource utilization, and enhances the security and unpredictability of random numbers.
Smart Images
Figure CN119597241A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of communication information security, and in particular relates to a hybrid random number generator based on FPGA. Background Art
[0002] With the development of communication information security technology, random numbers have been widely used in the fields of cryptographic security, physical testing, and radar anti-interference. Therefore, various fields have higher and higher performance requirements for random number generators, and it is increasingly important to study random number generators with strong randomness.
[0003] At present, the mainstream random number generators are mainly divided into true random number generators and pseudo-random number generators. True random number generators are random number sequences generated by sampling real physical entropy sources and digitizing them. They are truly random numbers that cannot be predicted; however, true random number generators require a lot of resources to generate high-quality entropy sources and high-precision sampling circuits. Pseudo-random number generators are generally efficient and fast random numbers generated by deterministic algorithms, but general pseudo-random algorithms have the problem of seed values being predicted, which poses security risks.
[0004] The entropy source of a true random number generator can be divided into metastable circuits, self-timed oscillation rings, and ring oscillators. Among them, metastable circuits are easily affected by environmental factors and have poor stability; self-timed oscillation rings have higher entropy source quality, but their structure is relatively complex; ring oscillators have relatively simple structures, but to achieve a highly random entropy source, a large number of ring oscillator combinations are required. Traditional true random number generators based on ring oscillators require a large number of oscillators for random superposition, but the randomness requirements of hybrid random number generators are reduced.
[0005] At present, the mainstream pseudo-random number implementation algorithms include linear congruential algorithm, linear shift register (LFSR), Mersenne algorithm and chaos algorithm. The linear congruential algorithm and LFSR have simple structures, but poor randomness and complexity; random algorithm pseudo-random number generators such as Mersenne algorithm are efficient and fast, but have poor reshaping and high resource consumption. In contrast, the implementation of chaos algorithm is more flexible and has high nonlinear characteristics, and randomness can be guaranteed. However, there are problems with the initial value being predicted and the chaotic characteristics being degraded during the iteration process of the chaos algorithm, and for generators with higher randomness requirements, a more complex chaos model is required. Summary of the invention
[0006] 1. Technical issues to be resolved
[0007] The technical problem to be solved by the present invention is to design a hybrid random number generator to generate high-quality true random numbers, and solve the problem of using a simple true random number generator and a low-order chaotic structure to generate highly complex random numbers.
[0008] (II) Technical solution
[0009] In order to solve the above technical problems, the present invention provides a hybrid random number generator based on FPGA, comprising: a true random number generator module, a chaotic state update module and a chaotic random number generator module; wherein the true random number generator module is used to generate true random numbers by sampling a physical entropy source; the chaotic state update module is used to process the true random numbers, obtain random numbers of specified bit widths and output them regularly; the chaotic random number generator module is used to adopt an appropriate chaotic model algorithm, complete chaotic model calculations through floating-point operations, and update parameters and initial values in the chaotic model with the random numbers output by the chaotic state update module, so as to generate highly random random numbers through iteration.
[0010] Preferably, the true random number generator module specifically uses a sampling circuit to sample the ring oscillator circuit, and outputs true random numbers through multi-way XOR.
[0011] Preferably, the true random number generator module includes the following submodules:
[0012] a) Ring oscillator module, used to generate 4 ring oscillator circuits on FPGA;
[0013] b) a sampling circuit, used for sampling each ring oscillator circuit to obtain a binary sequence of four specified bit widths; wherein the sampling time width of the sampling circuit is greater than one half of the period of the ring oscillator;
[0014] c) an edge detector module, used for decoding the obtained multiple binary sequences using an LSB decoder, and determining the decoder output according to the position of the first edge in the binary sequence, wherein the decoding is performed using a method in which an odd number is 0 and an even number is 1;
[0015] d) A multi-way XOR module, used to XOR the outputs of multiple LSB decoders with each other to obtain a binary sequence of true random numbers that are randomly accumulated by multiple ring oscillator circuits.
[0016] Preferably, the chaotic state updating module specifically adopts a buffer module to receive the true random number generated by the true random number generator module through a fifo, converts it into a single-precision floating point number within a specified range, and controls the parameters and state of the chaotic algorithm operation to be changed in a timely manner.
[0017] Preferably, the chaotic state updating module includes the following submodules:
[0018] a) a buffer module, used for using fifo to buffer the received true random number;
[0019] b) a serial-to-parallel conversion module, which is used to convert the single-bit true random number output by the buffer module into parallel data as the update value of the parameters and initial values of the subsequent chaotic model; the serial-to-parallel conversion module outputs a 75-bit parallel true random number so that the parameters and initial values of the chaotic model are within a pre-selected range;
[0020] c) updating the numerical conversion module, which is used to receive the 75-bit parallel true random number output by the serial-to-parallel conversion module, and construct the initial value and parameter value of the chaos model by adding the remaining bits of the single-precision floating point number;
[0021] d) A timer module is used to use two timers to control the update of the single-precision floating-point number output by the value conversion module as the chaotic model update value, wherein one timer is used to update the parameters of the chaotic model, and the other timer is used to update the initial value of the chaotic model.
[0022] Preferably, the chaotic random number generator module specifically uses the Euler algorithm to construct the following Lorenz chaotic model on the FPGA:
[0023]
[0024] Where a, b, c are the parameters of the Lorenz chaos model, and t is the duration of the calculation iteration.
[0025] Preferably, the chaotic random number generator module includes the following submodules:
[0026] a) A state modification module is used to determine whether the chaotic state update module needs to update the parameters and initial values of the chaotic model; if the parameters need to be updated, a floating-point operator is used to calculate [1-at], [1-t], [1-ct], at and bt, and use them as the parameters of the new chaotic model; if the initial value needs to be updated, a random number output by the chaotic state update module is received, and the initial value of the chaotic model is replaced;
[0027] b) a chaos model module, which is used to calculate x(n+1), y(n+1) and z(n+1) in the chaos model by using a floating-point arithmetic unit implemented by FPGA, thereby completing the calculation of the chaos model, wherein the iteration of the chaos model needs to wait for several iterations before outputting a random number;
[0028] c) a timing output module, used to control the chaotic model to not output results in the first 30 iterations after the chaotic state is updated, and to output the results of the XOR of the lower 10 bits of x, y, and z after the iteration in the next 30 iterations;
[0029] d) A buffer module, used for using a fifo to buffer the random number output by the timing output module.
[0030] Preferably, the parameters and initial values of the chaotic model are set as follows: the value range of a is (8, 15), the value range of b is (32, 64), the value range of c is (2, 3), and the value range of the initial value is (2, 31); in the calculation of the chaotic model, only the last 23 bits of a need to be changed, only the last 24 bits of b need to be changed, only the last 22 bits of c need to be changed, and only the last 25 bits of the initial value need to be changed, and the remaining bits are fixed values.
[0031] Preferably, the hybrid random number generator is used in the field of communication information security technology.
[0032] Preferably, the hybrid random number generator is used in the field of radar anti-interference technology.
[0033] (III) Beneficial effects
[0034] The present invention designs a hybrid random number generator based on FPGA to generate high-quality true random numbers, including a true random number generator module, a chaotic state update module and a chaotic random number generator module. The hybrid random number generator uses FPGA to update the chaotic model through true random number control to generate highly complex random numbers; a simple entropy source and a low-order chaotic algorithm are used to maintain the chaotic state, which solves the problem of using a simple true random number generator and a low-order chaotic structure to generate highly complex random numbers, and improves the resource utilization efficiency of FPGA. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 This is a module diagram of the implementation of the FPGA-based hybrid random number generator of the present invention. DETAILED DESCRIPTION
[0036] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.
[0037] The present invention designs a hybrid random number generator based on FPGA to generate high-quality true random numbers. Figure 1The hybrid random number generator includes: a true random number generator module, a chaotic state update module and a chaotic random number generator module; wherein the true random number generator module is used to generate true random numbers by sampling a physical entropy source; the chaotic state update module is used to process the true random numbers, obtain random numbers of a specified bit width and output them at a fixed time; the chaotic random number generator module is used to adopt an appropriate chaotic model algorithm, complete the chaotic model calculation through floating point operations, and update the parameters and initial values in the chaotic model with the random numbers (true random numbers) output by the chaotic state update module, and generate highly random random numbers through iteration. The hybrid random number generator of the present invention uses FPGA to update the chaotic model through true random number control to generate highly complex random numbers; a simple entropy source and a low-order chaotic algorithm are used to maintain the chaotic state, thereby improving the resource utilization efficiency of the FPGA.
[0038] Among them, since general pseudo-random algorithms have the problem of seed values being predicted, there are risks to security. Therefore, the present invention selects a hybrid random number generator that uses true random numbers as the seed value of the pseudo-random number generator, which is both unpredictable and highly random. Since the hybrid random number generator has lower randomness requirements for the true random number generator, the present invention chooses to use a small amount of ring oscillator circuits as the entropy source of the true random number generator. And since a generator with a higher randomness requirement requires a more complex chaotic model, the present invention chooses to use a chaotic algorithm as the pseudo-random number generator part of the hybrid random number generator, and updates the chaotic model with true random numbers to suppress the degradation of chaotic characteristics.
[0039] The specific implementation of the present invention is as follows:
[0040] Step 1: In the true random number generator module, a sampling circuit is used to sample the ring oscillator circuit and output a true random number through a multi-way XOR.
[0041] The true random number generator module contains the following submodules:
[0042] a) Ring oscillator module, used to generate 4 ring oscillator circuits on FPGA;
[0043] b) a sampling circuit, used to sample each ring oscillator circuit to obtain a binary sequence of four specified bit widths; wherein the sampling time width of the sampling circuit needs to be greater than one-half of the ring oscillator period to ensure that the edge changes of the ring oscillator circuit can be collected each time the sampling is performed;
[0044] c) an edge detector module, used for decoding the obtained multiple binary sequences using an LSB decoder, and determining the decoder output according to the position of the first edge in the binary sequence, wherein the decoding is performed using a method in which an odd number is 0 and an even number is 1;
[0045] d) a multi-way XOR module, used to XOR the outputs of multiple LSB decoders with each other to obtain a binary sequence of true random numbers accumulated randomly by multiple ring oscillator circuits;
[0046] The above-mentioned true random number generator module is only used as an update value of the subsequent chaotic model, does not require high randomness, and can be implemented using fewer ring oscillators; therefore, the present invention can improve the resource utilization of FPGA and reduce power consumption.
[0047] Step 2: In the chaotic state update module, the buffer module is used to receive the true random number generated by the true random number generator module through the fifo, convert it into a single-precision floating-point number within the specified range, and time-controlled change of the parameters and state of the chaotic algorithm operation.
[0048] The chaos state update module contains the following submodules:
[0049] a) Buffer module, used to use fifo to cache the received true random numbers. In order to ensure that the chaotic model maintains chaotic characteristics during the iteration and update process, it is necessary to set the range of the parameters and initial values of the chaotic model. After calculation, the parameters and initial values of the chaotic model can be set as follows: the value range of a is (8, 15), the value range of b is (32, 64), the value range of c is (2, 3), and the value range of the initial value is (2, 31); because floating-point numbers are used in the subsequent calculations of the chaotic model, a only needs to change the last 23 bits, b only needs to change the last 24 bits, c only needs to change the last 22 bits, and the initial value only needs to change the last 25 bits, and the remaining bits are fixed values;
[0050] b) A serial-to-parallel conversion module is used to convert the single-bit true random number output in the buffer module into parallel data as the update value of the parameters and initial values of the subsequent chaotic model. In order to save resources and facilitate subsequent output, the serial-to-parallel conversion module is set to output 75-bit parallel true random numbers so that the parameters and initial values of the chaotic model are within the pre-selected range;
[0051] c) updating the numerical conversion module, which is used to receive the 75-bit parallel true random number output by the serial-to-parallel conversion module, and construct the initial value and parameter value of the chaos model by adding the remaining bits of the single-precision floating point number;
[0052] d) A timer module is used to use two timers to control the update of the single-precision floating-point number output by the value conversion module as the chaotic model update value, wherein one timer is used to update the parameters of the chaotic model, and the other timer is used to update the initial value of the chaotic model.
[0053] Step 3: In the chaotic random number generator module, the Euler algorithm is used to construct the following Lorenz chaos model on the FPGA:
[0054]
[0055] Where a, b, c are the parameters of the Lorenz chaos model, and t is the duration of the calculation iteration; random numbers can be output through iteration and timing output to the buffer module.
[0056] The chaotic random number generator module contains the following submodules:
[0057] a) A state modification module is used to determine whether the chaotic state update module needs to update the parameters and initial values of the chaotic model; if the parameters need to be updated, a floating-point operator is used to calculate [1-at], [1-t], [1-ct], at and bt, and use them as the parameters of the new chaotic model; if the initial value needs to be updated, a random number output by the chaotic state update module is received, and the initial value of the chaotic model is replaced;
[0058] b) Chaos model module, used to calculate x(n+1), y(n+1) and z(n+1) in the chaos model by using a floating-point operator implemented by FPGA to complete the calculation of the chaos model; in the FPGA implementation of the chaos model, the use of a floating-point operator can improve the accuracy of the chaos mapping and suppress the degradation of chaos, and floating-point operations are also more convenient for modifying chaos parameters and initial values; in order to eliminate the influence of the initial value of chaos, the iteration of the chaos model needs to wait for several iterations before outputting a random number.
[0059] c) A timing output module is used to control the chaotic model to not output results in the first 30 iterations after the chaotic state is updated, and to output the results of the XOR of the lower 10 bits of x, y, and z after the iteration in the next 30 iterations as the output of the mixed random number generator module.
[0060] d) A buffer module, used for using a fifo to buffer the random number output by the timing output module.
[0061] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A hybrid random number generator based on FPGA, characterized in that: include: A true random number generator module, a chaotic state update module and a chaotic random number generator module; wherein the true random number generator module is used to generate true random numbers by sampling a physical entropy source; the chaotic state update module is used to process the true random numbers, obtain random numbers of a specified bit width and output them regularly; The chaotic random number generator module is used to adopt an appropriate chaotic model algorithm, complete the chaotic model calculation through floating-point operations, and update the parameters and initial values in the chaotic model with the random numbers output by the chaotic state update module, and generate highly random random numbers through iteration.
2. The hybrid random number generator according to claim 1, characterized in that: The true random number generator module specifically uses a sampling circuit to sample the ring oscillator circuit and outputs true random numbers through multi-channel XOR.
3. The hybrid random number generator as claimed in claim 2, characterized in that The true random number generator module contains the following submodules: a) Ring oscillator module, used to generate 4 ring oscillator circuits on FPGA; b) a sampling circuit, used for sampling each ring oscillator circuit to obtain a binary sequence of four specified bit widths; Wherein the sampling time width of the sampling circuit is greater than one half of the period of the ring oscillator; c) an edge detector module, used for decoding the obtained multiple binary sequences using an LSB decoder, and determining the decoder output according to the position of the first edge in the binary sequence, wherein the decoding is performed using a method in which an odd number is 0 and an even number is 1; d) A multi-way XOR module, used to XOR the outputs of multiple LSB decoders with each other to obtain a binary sequence of true random numbers that are randomly accumulated by multiple ring oscillator circuits.
4. The hybrid random number generator as claimed in claim 3, characterized in that: The chaotic state update module specifically adopts the buffer module to receive the true random number generated by the true random number generator module through the fifo, converts it into a single-precision floating point number within a specified range, and controls the parameters and state of the chaotic algorithm operation to be changed in a timely manner.
5. The hybrid random number generator as claimed in claim 4, characterized in that The chaos state update module contains the following submodules: a) a buffer module, used for using fifo to buffer the received true random number; b) a serial-to-parallel conversion module, which is used to convert the single-bit true random number output by the buffer module into parallel data as the update value of the parameters and initial values of the subsequent chaotic model; the serial-to-parallel conversion module outputs a 75-bit parallel true random number so that the parameters and initial values of the chaotic model are within a pre-selected range; c) updating the numerical conversion module, which is used to receive the 75-bit parallel true random number output by the serial-to-parallel conversion module, and construct the initial value and parameter value of the chaos model by adding the remaining bits of the single-precision floating point number; d) A timer module is used to use two timers to control the update of the single-precision floating-point number output by the value conversion module as the chaotic model update value, wherein one timer is used to update the parameters of the chaotic model, and the other timer is used to update the initial value of the chaotic model.
6. The hybrid random number generator as claimed in claim 5, characterized in that The chaotic random number generator module specifically uses the Euler algorithm to construct the following Lorenz chaos model on the FPGA: Where a, b, c are the parameters of the Lorenz chaos model, and t is the duration of the calculation iteration.
7. The hybrid random number generator as claimed in claim 6, characterized in that The chaotic random number generator module contains the following submodules: a) A state modification module is used to determine whether the chaotic state update module needs to update the parameters and initial values of the chaotic model; if the parameters need to be updated, a floating-point operator is used to calculate [1-at], [1-t], [1-ct], at and bt, and use them as the parameters of the new chaotic model; if the initial value needs to be updated, a random number output by the chaotic state update module is received, and the initial value of the chaotic model is replaced; b) a chaos model module, which is used to calculate x(n+1), y(n+1) and z(n+1) in the chaos model by using a floating-point arithmetic unit implemented by FPGA, thereby completing the calculation of the chaos model, wherein the iteration of the chaos model needs to wait for several iterations before outputting a random number; c) a timing output module, used to control the chaotic model to not output results in the first 30 iterations after the chaotic state is updated, and to output the results of the XOR of the lower 10 bits of x, y, and z after the iteration in the next 30 iterations; d) A buffer module, used for using a fifo to buffer the random number output by the timing output module.
8. The hybrid random number generator as claimed in claim 6, characterized in that: The parameters and initial values of the chaos model are set as follows: the value range of a is (8, 15), the value range of b is (32, 64), the value range of c is (2, 3), and the value range of the initial value is (2, 31); in the calculation of the chaos model, only the last 23 bits of a need to be changed, only the last 24 bits of b need to be changed, only the last 22 bits of c need to be changed, and only the last 25 bits of the initial value need to be changed, and the remaining bits are fixed values.
9. The hybrid random number generator according to any one of claims 1 to 8, characterized in that: The hybrid random number generator is used in the field of communication information security technology.
10. The hybrid random number generator according to any one of claims 1 to 8, characterized in that: The hybrid random number generator is used in the field of radar anti-interference technology.