Parallel computing method for number-theory transformation, computer equipment and storage medium

Abstract

The invention discloses a parallel computing method for number-theory transformation, computer equipment and a computer storage medium. The method comprises the following steps: determining a target modulus, a target primitive root and an optimization factor for optimizing parallel computing according to an input first input polynomial; and determining a second input polynomial according to the first input polynomial and the target modulus. And according to the target primitive root, performing bit inverse permutation processing on the second input polynomial to obtain a third input polynomial. And according to the optimization factor, the target modulus and the target primitive root, performing butterfly operation processing on the third input polynomial to obtain target output data so as to realize parallel calculation of number-theory transformation. Thus, through deep analysis of the first input polynomial, the optimization factor is obtained, the calculation complexity of the algorithm is effectively reduced, excellent expandability and wide applicability are shown, and a flexible and efficient solution is provided for calculation tasks of different scales.

Description

Technical Field

[0001] The present application relates to the field of information security technology, and more specifically, to a parallel computing method, computer device and computer storage medium for number theory transformation. Background Art

[0002] In today's era of rapid development of information technology, lattice-based cryptographic algorithms have attracted much attention due to their unique advantages in security. However, lattice-based cryptographic algorithms have bottlenecks in computing performance, especially the long time-consuming polynomial multiplication operations on the lattice, which restricts their widespread application. In related technologies, number theoretic transformation algorithms are used as optimization methods to improve the efficiency of polynomial multiplication. In this way, the efficiency of number theoretic transformation algorithms affects the efficiency of lattice-based cryptographic algorithms. Summary of the invention

[0003] The present application provides a parallel computing method, a computer device and a computer storage medium for number theory transformation.

[0004] The present application embodiment provides a parallel computing method for number theory transformation, the method comprising:

[0005] Determine a target modulus, a target primitive root, and an optimization factor for optimizing the parallel calculation according to a first input polynomial inputted;

[0006] Determining a second input polynomial according to the first input polynomial and the target modulus;

[0007] Performing bit-reversal permutation processing on the second input polynomial according to the target primitive root to obtain a third input polynomial;

[0008] According to the optimization factor, the target modulus and the target primitive root, the third input polynomial is processed by butterfly operation to obtain target output data, so as to realize parallel calculation of the number theory transformation.

[0009] In this way, the computer device determines the target modulus, the target primitive root and the optimization factor for optimizing parallel computing based on the input first input polynomial. Next, the second input polynomial is determined based on the first input polynomial and the target modulus. Then, the computer device performs bit-reversal permutation processing on the second input polynomial based on the target primitive root to obtain the third input polynomial. Finally, the computer device performs butterfly operation processing on the third input polynomial based on the optimization factor, the target modulus and the target primitive root to obtain the target output data to realize the parallel computing of number theory transformation. In this way, by performing in-depth analysis on the first input polynomial, the optimization factor obtained effectively reduces the computational complexity of the algorithm, and demonstrates excellent scalability and wide applicability, providing flexible and efficient solutions for computing tasks of different scales, thereby providing strong technical support for the promotion and deepening of number theory transformation in practical applications.

[0010] In some embodiments, determining a target modulus, a target primitive root, and an optimization factor for optimizing the parallel computing according to the input first input polynomial includes:

[0011] Determine the target modulus and the target primitive root according to the first input polynomial;

[0012] Performing logarithmic processing on the first input polynomial to obtain the number of operation stages;

[0013] Determining, based on the first input polynomial, a factor of the number of terms of the first input polynomial;

[0014] The optimization factor is determined according to the number of operation stages and the factor.

[0015] In this way, the computer device determines the target modulus and the target primitive root according to the first input polynomial. The computer device performs logarithmic processing on the first input polynomial to obtain the number of operation stages. Then, the computer device determines the factor of the number of terms of the first input polynomial according to the first input polynomial. Finally, the computer device determines the optimization factor according to the number of operation stages and the factor. In this way, by deeply analyzing the first input polynomial, the optimization factor most suitable for the first input polynomial is accurately calculated to ensure the maximum utilization of computing resources.

[0016] In certain embodiments, the method further comprises:

[0017] Based on the target modulus, the target primitive root is verified.

[0018] In this way, the computer device verifies the target primitive root according to the target modulus. In this way, the computer device ensures that the inverse transformation of the number theory transformation can correctly restore the first input polynomial, which is the basis of the number theory transformation and the key to its efficient operation.

[0019] In some embodiments, determining a second input polynomial according to the first input polynomial and the target modulus includes:

[0020] According to the target modulus, performing a modulo operation on the coefficients of the first input polynomial to obtain first coefficients;

[0021] The coefficients of the first input polynomial are updated according to the first coefficients to determine the second input polynomial.

[0022] In this way, the computer device performs a modular operation on the coefficients of the first input polynomial according to the target modulus to obtain the first coefficient. Then, the computer device updates the coefficients of the first input polynomial according to the first coefficient to determine the second input polynomial. In this way, the computer device can effectively process the input polynomial and obtain the coefficient representation for number theory transformation, and prevent integer overflow and ensure that the result is within the finite field, thereby ensuring the correctness and validity of the result, which is particularly important when processing large number operations and polynomial operations on finite fields.

[0023] In some implementations, performing bit-reversal permutation processing on the second input polynomial according to the target primitive root to obtain a third input polynomial includes:

[0024] The first coefficients are subjected to bit-reversal permutation processing according to the target primitive roots to obtain the third input polynomial.

[0025] In this way, the computer device performs a bit-reversal permutation process on the first coefficient according to the target primitive root to obtain the third input polynomial. In this way, the computer device can ensure that the data points can be correctly paired and operated at each stage of the butterfly operation, reducing data dependence and communication overhead, thereby improving the calculation speed and efficiency.

[0026] In some implementations, performing bit-reversal processing on the first coefficient according to the target primitive root to obtain the third input polynomial includes:

[0027] Performing binary coding processing on the first coefficient to obtain an initial binary coefficient;

[0028] Reversing the bit order of the binary coefficients to obtain target binary coefficients;

[0029] The third input polynomial is determined based on the target binary coefficients.

[0030] In this way, the computer device performs binary encoding processing on the first coefficient to obtain an initial binary coefficient. Next, the computer device performs bit reverse processing on the binary coefficient to obtain a target binary coefficient. Finally, the computer device determines the third input polynomial according to the target binary coefficient. In this way, the computer device can transform the recursive process into an iterative process through bit reverse permutation processing, thereby optimizing the execution efficiency of the number theory transformation algorithm and reducing memory consumption.

[0031] In some embodiments, the target primitive root includes a plurality of roots, and the butterfly operation is performed on the third input polynomial according to the optimization factor, the target modulus and the target primitive root to obtain target output data to realize parallel calculation of number theory transformation, including:

[0032] Determining the number of data synchronizations according to the number of operation stages and the optimization factor, the number of data synchronizations including at least one operation stage;

[0033] In each data synchronization process, the third input polynomial is subjected to butterfly operation according to the target modulus and the current primitive root to obtain the target output data, so as to realize parallel calculation of number theory transformation.

[0034] In this way, the computer device determines the number of data synchronizations according to the number of operation stages and the optimization factor, and the number of data synchronizations includes at least one operation stage. Then, in each data synchronization process, the computer device performs butterfly operation processing on the third input polynomial according to the target modulus and the current primitive root to obtain target output data to realize parallel calculation of number theory transformation. In this way, by expanding the iterative loop of number theory transformation according to the determined optimization factor, the parallelism of butterfly operation is improved, the time overhead required for data synchronization is reduced, and the overall calculation efficiency of the number theory transformation algorithm is improved.

[0035] In some implementations, during each data synchronization process, the butterfly operation is performed i*2^(i-1) times, where i is the optimization factor.

[0036] Thus, in each data synchronization process, the number of butterfly operations is i*2^(i-1), where i is the optimization factor. In this way, by expanding the iterative loop of the number theory transformation according to the determined optimization factor, the parallelism of the butterfly operation is improved, the time overhead required for data synchronization is reduced, and the overall computational efficiency of the number theory transformation algorithm is improved.

[0037] In certain embodiments, the method further comprises:

[0038] Determine the next primitive root of the current primitive root according to the target primitive root;

[0039] According to the optimization factor, the target modulus and the next primitive root, the third input polynomial is processed by butterfly operation to obtain the target output data, so as to realize parallel calculation of number theory transformation.

[0040] In this way, the computer device determines the next primitive root of the current primitive root according to the target primitive root. Then, the computer device performs butterfly operation processing on the third input polynomial according to the optimization factor, the target modulus and the next primitive root to obtain the target output data to realize the parallel calculation of the number theory transformation. In this way, the performance of parallel calculation can be improved by using multiple target primitive roots and optimized data synchronization strategies. By performing data synchronization at each operation stage or a specific stage and selecting a suitable target primitive root, the computer device can perform the number theory transformation more efficiently.

[0041] An embodiment of the present application provides a computer device, which includes a memory, a processor, and a computer program stored in the memory, and the processor executes the computer program to implement the above method.

[0042] An embodiment of the present application provides a computer storage medium, wherein the computer-readable storage medium memory stores a computer program, and when the computer program is executed by one or more processors, the above method is implemented.

[0043] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0045] Figure 1 It is one of the flow charts of the implementation method of the present application;

[0046] Figure 2 is a schematic diagram of a butterfly operation unit according to an embodiment of the present application;

[0047] Figure 3 This is the second flow chart of the implementation method of the present application;

[0048] Figure 4 This is the third flow chart of the implementation method of this application;

[0049] Figure 5 This is the fourth flow chart of the implementation method of the present application;

[0050] Figure 6This is the fifth flow chart of the implementation method of the present application;

[0051] Figure 7 This is the sixth flow chart of the implementation method of this application;

[0052] Figure 8 This is the seventh flow chart of the implementation method of the present application;

[0053] Fig. 9 It is one of the butterfly operation schematic diagrams of the example implementation mode of the present application;

[0054] Fig.10 This is the second schematic diagram of butterfly operation of an example of an implementation method of the present application;

[0055] Fig.11 This is the eighth flow chart of the implementation method of the present application. DETAILED DESCRIPTION

[0056] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application, and cannot be understood as limiting the embodiments of the present application.

[0057] In today's era of rapid development of informatization, information security has become the cornerstone of the stable operation of digital enterprises. However, the development of quantum computing technology poses a challenge to traditional public key cryptographic algorithms, which can crack the number theory problems they rely on and threaten the security of existing encryption systems. To this end, cryptography experts at home and abroad are studying post-quantum cryptographic algorithms to build encryption standards that can resist attacks from classical computers and quantum computers.

[0058] Lattice-based cryptographic algorithms have attracted much attention due to their unique advantages in security. The algorithm is based on complex mathematical problems on the lattice, which are difficult to solve for both classical and quantum computing models, and is regarded as a highly promising post-quantum encryption technology.

[0059] However, lattice-based cryptographic algorithms have bottlenecks in terms of computing performance, especially the time-consuming polynomial multiplication operations on the lattice, which restricts their widespread application. In related technologies, number theoretic transformation algorithms are used as optimization methods to improve the efficiency of polynomial multiplication. In this way, the efficiency of number theoretic transformation algorithms affects the efficiency of lattice-based cryptographic algorithms.

[0060] Based on the above questions, please refer to Figure 1 The present application embodiment provides a parallel computing method for number theory transformation, the method comprising:

[0061] 011: Determine a target modulus, a target primitive root, and an optimization factor for optimizing parallel computing according to the first input polynomial input;

[0062] 012: Determine a second input polynomial according to the first input polynomial and the target modulus;

[0063] 013: Perform bit-reversal permutation processing on the second input polynomial according to the target primitive root to obtain the third input polynomial;

[0064] 014: According to the optimization factor, the target modulus and the target primitive root, the third input polynomial is processed by butterfly operation to obtain the target output data to realize the parallel calculation of number theory transformation.

[0065] The embodiment of the present application also provides a computer device, including a memory and a processor. The parallel computing method for number theory transformation of the embodiment of the present application can be implemented by the computer device of the embodiment of the present application. Specifically, a computer program is stored in the memory, and the processor is used to determine the target modulus, the target primitive root and the optimization factor for optimizing parallel computing according to the input first input polynomial. And determine the second input polynomial according to the first input polynomial and the target modulus. The processor is also used to perform bit reverse permutation processing on the second input polynomial according to the target primitive root to obtain a third input polynomial. And perform butterfly operation processing on the third input polynomial according to the optimization factor, the target modulus and the target primitive root to obtain the target output data, so as to realize the parallel computing of number theory transformation.

[0066] The embodiment of the present application also provides a parallel device for number theoretic transformation. The parallel computing method for number theoretic transformation of the embodiment of the present application can be implemented by the parallel device for number theoretic transformation of the embodiment of the present application. Specifically, the parallel device for number theoretic transformation includes a determination module, a processing module and a butterfly operation module. The determination module is used to determine the target modulus, the target primitive root and the optimization factor for optimizing parallel computing according to the input first input polynomial. The determination module is used to determine the second input polynomial according to the first input polynomial and the target modulus. The processing module is also used to perform bit reverse permutation processing on the second input polynomial according to the target primitive root to obtain a third input polynomial. The butterfly operation module is used to perform butterfly operation processing on the third input polynomial according to the optimization factor, the target modulus and the target primitive root to obtain the target output data, so as to realize the parallel computing of number theoretic transformation.

[0067] Specifically, the number theoretic transform (NTT) refers to a discrete Fourier transform performed under integer modular operations. It is a mathematical tool used to efficiently process large amounts of data in fields such as cryptography and signal processing. The number theoretic transform can perform integer operations without losing precision, which is very important for applications such as homomorphic encryption and digital signature algorithms in cryptography. In addition, due to the structure of butterfly operations and the properties of integer operations, the number theoretic transform is very suitable for parallel computing and can efficiently process large amounts of data. The number theoretic transform algorithm is suitable for lattice-based cryptographic algorithms.

[0068] Parallel computing refers to a computing method that improves computing speed and efficiency by executing multiple computing tasks simultaneously. In parallel computing, a large computing problem is broken down into multiple small sub-problems that can be solved simultaneously by multiple processors or computing units. Parallel computing can be used in various computing environments, including multi-core CPUs, graphics processing units (GPUs), distributed systems, cluster computing, etc.

[0069] The first input polynomial refers to the polynomial that is initially input into the computer device for transformation. The coefficients of this polynomial are integers, and they constitute the initial data set for the number theory transformation. The first input polynomial can be expressed as: P(x) = a0 + a1*x + a2*x^2 + ... + an*x^n, where ai is the coefficient of the polynomial, n is the order of the polynomial, that is, the degree of the highest order term in the polynomial, and x is the variable of the polynomial. During the number theory transformation process, the coefficients of the first input polynomial will undergo multiple processing steps, including modular operation processing, bit reversal permutation, butterfly operation, etc., to obtain the final transformation result, thereby improving the efficiency and speed of the number theory transformation.

[0070] The target modulus refers to a specific prime number that ensures that the transformation is performed in the integer domain, which is usually relatively large. This prime number is one of the key parameters of number theory transformation and can determine the modulus of all operations in the transformation process. Using a prime number as the target modulus can ensure the existence of inverse elements of division and multiplication, so that the number theory transformation can be performed correctly. In addition, if the target modulus is large enough, it can accommodate all intermediate results and final results in the transformation process. If the modulus is too small, it may cause data overflow or loss of precision.

[0071] The target primitive root refers to a specific number that has special properties when performing operations modulo the target modulus. First, the target primitive root must be a primitive root of the target modulus so that all its powers modulo the target modulus can generate a complete field. Second, the target primitive root must be small enough to allow efficient multiplication and division operations during the calculation process. If the primitive root is too large, it may lead to reduced computational efficiency. Third, the target primitive root must be an integer because number theory transformations are performed in the integer field.

[0072] The optimization factor refers to the parameters used to adjust and optimize the butterfly operation process, which is usually related to the structure and efficiency of parallel computing and can help computer devices perform number theory transformations more efficiently. The optimization factor can be used to determine the number of butterfly operations performed by each GPU thread. It is a factor of the polynomial length N to facilitate parallel computing and resource allocation. The selection of the optimization factor is based on the parallel processing characteristics of the GPU and the optimal use of computing resources.

[0073] The second input polynomial refers to a polynomial obtained by updating each coefficient of the first input polynomial using integers of each coefficient of the first input polynomial under the target modulus.

[0074] Bit-reversal permutation is a step in number theory transformation algorithms that rearranges the order of input data. In a parallel computing environment, the execution of butterfly operations can be optimized by performing bit-reversal permutation.

[0075] The third input polynomial refers to the third input polynomial obtained by performing bit-reversal processing on the first coefficient of the second input polynomial.

[0076] In some embodiments, the number theoretic transformation algorithm may be as follows:

[0077] Algorithm 1Number Theoretical Transform

[0078] Input:a∈R, and N = a.length;

[0079] Output: A = NTT(a);

[0080] 1: A = a;

[0081] 2: m = 0;

[0082] 3: for(s=128; s>0; s>>=1)do

[0083] 4: for(k=0;k <N;k=i+s)do

[0084] 5:zeta=zetas[++m];

[0085] 6: for(i=k; i <k+s;++i)do

[0086] 7: t = zeta × A[i + s];

[0087] 8: A[i+s]=A[i]-t mod q;

[0088] 9: A[i] = A[i] + t mod q;

[0089] 10: end for

[0090] 11: end for

[0091] 12: end for

[0092] 13: return A.

[0093] Where Zq represents the set of integers in the interval [0,q). Polynomial ring Rq = Zq[x] / <xn+1> Contains all polynomials of degree less than n in Zq[x], where q = 1 mod 2n, and Zq[x] contains all polynomials whose coefficients are in Zq. a is a polynomial over the polynomial ring Rq, and zetas is a preset rotation factor.

[0094] See also Figure 2 , Figure 2 Schematic diagram of a butterfly unit, where lines 7-9 can be represented as a complete butterfly unit (BU) when implemented in hardware.

[0095] The computer device first determines the target modulus, the target primitive root and the optimization factor for optimizing parallel computing according to the input first input polynomial. The target modulus is a specific prime number used to ensure that the transformation is performed in the integer domain. The target primitive root is one of the key parameters of the number theory transformation, which is used to ensure that the transformation is performed in the integer domain. The optimization factor is a parameter used to determine the number of butterfly operations performed by each GPU thread in the parallel computing method of the number theory transformation. Next, the computer device determines the second input polynomial according to the first input polynomial and the target modulus. Then, the computer device performs a bit reversal permutation process on the second input polynomial according to the target primitive root to obtain a third input polynomial. Bit reversal permutation is a method of rearranging the order of data, which is very important for optimizing the execution of butterfly operations. Finally, the computer device performs a butterfly operation on the third input polynomial according to the optimization factor, the target modulus and the target primitive root to obtain target output data. Butterfly operation is an efficient data reorganization method, which obtains target output data by grouping data and performing operations.

[0096] For example, the first input polynomial is A(x)=2+3*x+4*x^2+5*x^3.

[0097] The computer device determines the target modulus p=7, the target primitive root g=3 and the optimization factor i=2 according to A(x). Next, the second input polynomial is determined according to the first input polynomial and the target modulus. Then, the computer device performs a bit-reversal permutation process on the second input polynomial according to the target primitive root to obtain a third input polynomial. Finally, the computer device performs a butterfly operation process on the third input polynomial according to the optimization factor, the target modulus and the target primitive root to obtain the target output data, so as to realize the parallel calculation of number theory transformation.

[0098] In summary, in the parallel computing method and computer device for number theoretic transformation of the implementation mode of the present application, the computer device determines the target modulus, the target primitive root and the optimization factor for optimizing parallel computing according to the first input polynomial input. Then, according to the first input polynomial and the target modulus, the first coefficient of the input polynomial is determined. Then, the computer device performs a bit-reversal permutation process on the first coefficient according to the target primitive root to obtain a third input polynomial. Finally, the computer device performs a butterfly operation process on the third input polynomial according to the optimization factor, the target modulus and the target primitive root to obtain the target output data to realize the parallel computing of number theoretic transformation. In this way, by performing an in-depth analysis of the first input polynomial, the optimization factor obtained effectively reduces the computational complexity of the algorithm, and demonstrates excellent scalability and wide applicability, providing a flexible and efficient solution for computing tasks of different scales, thereby providing strong technical support for the promotion and deepening of number theoretic transformation in practical applications.

[0099] See also Figure 3 In some embodiments, step 011 (determining a target modulus, a target primitive root, and an optimization factor for optimizing the parallel computation according to the input first input polynomial) includes:

[0100] 0111: Determine the target modulus and target primitive root according to the first input polynomial;

[0101] 0112: Perform logarithmic processing on the first input polynomial to obtain the number of operation stages;

[0102] 0113: Determine factors of the number of terms of the first input polynomial according to the first input polynomial;

[0103] 0114: Determine the optimization factor based on the number and factors of operation stages.

[0104] In some embodiments, the determination module is used to determine the target modulus and the target primitive root according to the first input polynomial. The processing module is used to perform logarithmic processing on the first input polynomial to obtain the number of operation stages. The determination module is used to determine the factor of the number of terms of the first input polynomial according to the first input polynomial. And determine the optimization factor according to the number of operation stages and the factor.

[0105] In some embodiments, the processor is further configured to determine a target modulus and a target primitive root based on the first input polynomial. And perform logarithmic processing on the first input polynomial to obtain the number of operation stages. The processor is further configured to determine a factor of the number of terms of the first input polynomial based on the first input polynomial. And determine an optimization factor based on the number of operation stages and the factor.

[0106] Specifically, logarithmic processing refers to processing the first input polynomial using log2, because each stage of the butterfly operation divides the data into two halves for processing.

[0107] Factors are integers that divide the number of terms evenly.

[0108] The computer device first determines a target modulus and a target primitive root based on a first input polynomial. Subsequently, the computer device performs logarithmic processing on the number of terms of the first input polynomial to determine the number of operation stages required to perform the number theory transformation. Next, the computer device analyzes the number of terms of the first input polynomial to determine its factors. Finally, the computer device determines an optimization factor based on the number of operation stages and the factors of the number of terms of the first input polynomial.

[0109] For example, when a polynomial of length N = 32768 needs to be multiplied, the computer device calculates that the number theory transformation has 15 stages, and then determines that the optimization factor i can be 5 based on the factors of N. In this way, 5*16 butterfly operations are performed in each thread, which only requires 3 data synchronizations. We only need to use 1 thread block, and each thread block contains 1024 5*16BUs.

[0110] In this way, by deeply analyzing the first input polynomial, the optimization factor most suitable for the first input polynomial is accurately calculated to ensure maximum utilization of computing resources.

[0111] See also Figure 4 In some embodiments, the method further comprises:

[0112] 015: Verify the target primitive root based on the target modulus.

[0113] In some embodiments, the processing module is used to verify the target primitive root based on the target modulus.

[0114] In some embodiments, the processor is further configured to verify the target primitive root based on the target modulus.

[0115] Specifically, first, it is necessary to determine the order of the target modulus, that is, the number of prime numbers less than the modulus. In some embodiments, it can be obtained by calculating the Euler function φ(p) of the target modulus, where p is the target modulus.

[0116] Then, check the properties of the target primitive root. If a number is a primitive root modulo p, for every prime number m less than p, the primitive root to the power of m modulo p is not equal to 1. In other words, the primitive root needs to satisfy g^((φ(p)) / m)≠1(mod p) for all prime factors mofφ(p), where g is the primitive root to be verified.

[0117] By calculating the various powers of the target primitive root and checking whether they satisfy the above conditions, a computer device can verify whether a given number is a target primitive root of the target modulus. If all conditions are met, the number is a valid primitive root and can be used for number theoretic transformations.

[0118] In this way, the computer device ensures that the inverse transform of the number-theoretic transformation can correctly restore the first input polynomial, which is the basis of the number-theoretic transformation and the key to its efficient operation.

[0119] See also Figure 5 In some embodiments, step 012 (determining a second input polynomial based on the first input polynomial and the target modulus) includes:

[0120] 0121: Perform a modular operation on the coefficients of the first input polynomial according to the target modulus to obtain a first coefficient;

[0121] 0122: According to the first coefficient, update the coefficient of the first input polynomial to determine the second input polynomial.

[0122] In some embodiments, the processing module is used to perform a modular operation on the coefficients of the first input polynomial according to the target modulus to obtain the first coefficients, and to update the coefficients of the first input polynomial according to the first coefficients to determine the second input polynomial.

[0123] In some embodiments, the processor is further configured to perform a modular operation on the coefficients of the first input polynomial according to the target modulus to obtain the first coefficients, and to update the coefficients of the first input polynomial according to the first coefficients to determine the second input polynomial.

[0124] Specifically, the computer device performs a modular operation on each coefficient of the first input polynomial, that is, divides each coefficient by the target modulus and takes the remainder. In this way, a first coefficient can be obtained, which is a representation of the first input polynomial under the target modulus. Then, the computer device updates the coefficient of the first input polynomial according to the first coefficient to determine the second input polynomial.

[0125] In this way, the computer device can effectively process the input polynomial and obtain the coefficient representation for number theory transformation, prevent integer overflow and ensure that the result is within the finite field, thereby ensuring the correctness and effectiveness of the result, which is especially important when dealing with large number operations and polynomial operations on finite fields.

[0126] See also Figure 6 In some embodiments, step 013 (performing bit-reversal permutation processing on the second input polynomial according to the target primitive root to obtain a third input polynomial) includes:

[0127] 0131: Perform bit-reversal permutation on the first coefficient according to the target primitive root to obtain the third input polynomial.

[0128] In some implementations, the processing module is used to perform bit-reversal permutation processing on the first coefficient according to the target primitive root to obtain a third input polynomial.

[0129] In some embodiments, the processor is further configured to perform bit-reversal permutation processing on the first coefficient according to the target primitive root to obtain a third input polynomial.

[0130] Specifically, the computer device performs a bit-reversal permutation process on the first coefficient. Bit-reversal permutation is a method of rearranging the order of data. Reversing the index positions of data points can ensure that the data points can be correctly paired and operated, thereby optimizing the parallel computing process of butterfly operations.

[0131] In this way, the computer equipment can ensure that data points are correctly paired and calculated at each stage of the butterfly operation, reducing data dependencies and communication overhead, thereby improving computing speed and efficiency.

[0132] See also Figure 7 In some embodiments, step 0131 (performing a bit-reversal permutation process on the first coefficient according to the target primitive root to obtain a third input polynomial) includes:

[0133] 01311: perform binary encoding processing on the first coefficient to obtain an initial binary coefficient;

[0134] 01312: Reverse the bit order of the binary coefficient to obtain the target binary coefficient;

[0135] 01313: Determine the third input polynomial based on the target binary coefficients.

[0136] In some embodiments, the processing module is used to perform binary coding processing on the first coefficient to obtain an initial binary coefficient. The processing module is also used to reverse the bit order of the binary coefficient to obtain a target binary coefficient. The determination module is used to determine the third input polynomial based on the target binary coefficient.

[0137] In some embodiments, the processor is further configured to perform binary encoding processing on the first coefficient to obtain an initial binary coefficient, and to perform bit order reversal processing on the binary coefficient to obtain a target binary coefficient, and to determine a third input polynomial according to the target binary coefficient.

[0138] Specifically, binary encoding is a method of representing data as binary numbers.

[0139] Bit reversal is a method of rearranging the order of data. Reversing the bit order of the initial binary coefficients can ensure that the data points can be correctly paired and operated, thereby optimizing the parallel computing process of the butterfly operation. The workflow can be as follows: First, convert the index (or position) of each data into a binary representation. Then, reverse the binary number, that is, reverse its bit order. Finally, convert the reversed binary number back to decimal to obtain a new index.

[0140] For an array with 8 data points, the original indices and the corresponding binary representations are as follows: Index 0: 000, Index 1: 001, Index 2: 010, Index 3: 011, Index 4: 100, Index 5: 101, Index 6: 110, Index 7: 111.

[0141] After reversing the bits of these binary representations, the new indexes are as follows: Index 0: 000 => 000, Index 1: 001 => 100, Index 2: 010 => 010, Index 3: 011 => 110, Index 4: 100 => 001, Index 5: 101 => 101, Index 6: 110 => 011, Index 7: 111 => 111. The obtained indexes are: 4, 2, 6, 1, 5, 3, and 7.

[0142] The computer device performs binary coding processing on the first coefficient, converts each coefficient into a binary representation, and obtains an initial binary coefficient. Then, the computer device performs a bit order reverse processing on the initial binary coefficient to obtain a target binary coefficient. Finally, the computer device determines a third input polynomial according to the target binary coefficient.

[0143] In this way, the computer device can transform the recursive process into an iterative process through bit reversal permutation processing, thereby optimizing the execution efficiency of the number theory transformation algorithm and reducing memory consumption.

[0144] See also Figure 8 In some embodiments, the target primitive root includes multiple, step 014 (performing butterfly operation on the third input polynomial according to the optimization factor, the target modulus and the target primitive root to obtain target output data to achieve parallel calculation of number theory transformation) includes:

[0145] 0141: Determine the number of data synchronizations based on the number of operation stages and the optimization factor;

[0146] 0142: During each data synchronization process, a butterfly operation is performed on the third input polynomial according to the target modulus and the current primitive root to obtain the target output data, so as to realize parallel calculation of number theory transformation.

[0147] In some embodiments, the determination module is used to determine the number of data synchronizations according to the number of operation stages and the optimization factor. The butterfly operation module is also used to perform butterfly operation on the third input polynomial according to the target modulus and the current primitive root during each data synchronization process to obtain target output data, so as to realize parallel calculation of number theory transformation.

[0148] In some embodiments, the processor is further configured to determine the number of data synchronizations according to the number of operation stages and the optimization factor, and in each data synchronization process, perform butterfly operation on the third input polynomial according to the target modulus and the current primitive root to obtain target output data, so as to realize parallel calculation of number theory transformation.

[0149] Specifically, data synchronization times refer to the number of times the calculation results need to be synchronized back to the main memory or processor core during the number theory transformation process. Each data synchronization involves summarizing some or all of the calculation results for the next stage of calculation. Data synchronization times include at least one operation stage to ensure the continuity and correctness of the calculation.

[0150] The computer device determines the number of data synchronizations according to the number of operation stages and the optimization factor, and the number of data synchronizations includes at least one operation stage. Then, during each data synchronization process, the computer device performs butterfly operation processing on the third input polynomial according to the target modulus and the current primitive root to obtain target output data, which is the result of the third input polynomial after the butterfly operation processing, and provides correct output data for subsequent calculations or data processing.

[0151] See also Fig. 9 and Fig.10 , the number of synchronizations in the figure is abbreviated as synchronization. Taking a polynomial of length N = 16 as an example, if the for loop in the number theory transformation algorithm is fully expanded, there will be 4 stages and 4*16 / 2 = 32 butterfly operations, such as Fig. 9 As shown. In the parallel algorithm of classical number theory transformation, if only one butterfly operation BU is stored in a GPU thread, we need at least 8 GPU threads, and at each stage we need to wait for all 8 GPU threads to complete and transfer all data back to the computer device, synchronize the data, and then proceed to the next stage of operation. A total of 4 synchronizations are required. In the parallel algorithm provided in the embodiment of the present application, if the optimization factor i is 2, then 4 butterfly operations BU are performed in each thread, with Fig.10 If we use the computing structure in the middle box for calculation, then after optimization we only need 1 GPU thread block, 4 GPU threads, and only 2 data synchronizations in 2 stages, which reduces the time for data reading, writing and synchronization, and achieves the purpose of improving computing efficiency.

[0152] The basis for the computer device to determine that it can continuously perform two layers of butterfly operations is that in the log2(2s)th stage of the NTT algorithm, butterfly operations are performed on the kth and (k+2s)th coefficients to perform butterfly operations on them. And in the log2(s)th stage, operations are performed on the kth and (k+s)th coefficients to perform butterfly operations on them. In order to simplify the representation, we record a pair of coefficients operated by the butterfly operation as {first index, second index}. If in the log2(2s)th stage, the two butterfly operation units respectively operate {k, k+2s} and {k+s, k+3s} in parallel, then the new coefficients {k, k+s} and {k+2s, k+3s} can be processed in parallel in the log2(s)th stage, because the two butterfly operation units only use four numbers {k, k+s, k+2s, k+3s}, and there is no additional data dependency problem.

[0153] For another example, the calculation process of polynomial multiplication c=a*b is as follows:

[0154] Step 1: Calculate NTT(a) and NTT(b) for all lgn stages

[0155] Step 2: Calculate c1 = NTT(a)⊙NTT(b)

[0156] Step 3: Calculate INTT(c1) and get c=a*b.

[0157] When a polynomial of length N = 32768 needs to be multiplied, the computer device calculates that the number theory transformation has 15 stages, and then determines that the optimization factor i can be 5 based on the factors of N. In this way, 5*16 butterfly operations are performed in each thread, which only requires 3 data synchronizations. We only need to use 1 thread block, and each thread block contains 1024 5*16BUs. Assuming that a butterfly operation takes 8 clock cycles, it takes 400 clock cycles to read and write the GPU global memory, and it takes 40 clock cycles to read and write the shared memory of the GPU thread block.

[0158] Then, in the parallel algorithm of the classical number theory transformation, the first step needs to spend 15 stages * (1 butterfly operation * 8 clock cycles + 1 global memory read and write * 400 clock cycles) + 1 global memory read and write * 400 clock cycles = 6520 clock cycles. However, in the parallel computing method provided by the embodiment of the present application, the first step needs to spend 3 stages * (5 * 16 butterfly operations * 8 clock cycles + 1 shared memory read and write * 40 clock cycles + 1 time) + 2 global memory read and write * 400 clock cycles = 2840 clock cycles.

[0159] Next, proceed to the second step and execute c1=NTT(a)⊙NTT(b). Using the GPU for parallel execution takes 2 global memory reads and writes*400 clock cycles + 1 multiplication operation*4 clock cycles=804 clock cycles.

[0160] Finally, the parallel computing algorithm is executed to calculate INTT(c1). The time complexity of INTT and NTT is the same.

[0161] Therefore, the classical parallel computing method theoretically requires 6250*2+804=13304 clock cycles to complete a polynomial multiplication operation of length N=32768, while the parallel algorithm provided by the implementation scheme of the present application theoretically requires 6484 clock cycles, and the theoretical computing efficiency is increased by 1 times.

[0162] In this way, by expanding the iterative loop of the number-theoretic transformation according to the determined optimization factor, the parallelism of the butterfly operation is improved, the time overhead required for data synchronization is reduced, and the overall computational efficiency of the number-theoretic transformation algorithm is improved.

[0163] In some implementations, during each data synchronization process, the number of butterfly operations performed is i*2^(i-1) times, where i is an optimization factor.

[0164] Specifically, in each data synchronization process, the number of butterfly operations is i*2^(i-1) times, where i is an optimization factor.

[0165] In this way, by expanding the iterative loop of the number-theoretic transformation according to the determined optimization factor, the parallelism of the butterfly operation is improved, the time overhead required for data synchronization is reduced, and the overall computational efficiency of the number-theoretic transformation algorithm is improved.

[0166] See also Fig.11 In some embodiments, the method further comprises:

[0167] 016: According to the target primitive root, determine the next primitive root of the current primitive root;

[0168] 017: According to the optimization factor, the target modulus and the next primitive root, the third input polynomial is processed by butterfly operation to obtain the target output data to realize the parallel calculation of number theory transformation.

[0169] In some embodiments, the determination module is further used to determine the next primitive root of the current primitive root according to the target primitive root. The butterfly operation module is used to perform butterfly operation processing on the third input polynomial according to the optimization factor, the target modulus and the next primitive root to obtain the target output data to realize the parallel calculation of number theory transformation.

[0170] In some embodiments, the processor is further configured to determine the next primitive root of the current primitive root according to the target primitive root, and to perform butterfly operation on the third input polynomial according to the optimization factor, the target modulus and the next primitive root to obtain target output data, so as to realize parallel calculation of number theory transformation.

[0171] Specifically, the computer device determines the next primitive root of the current primitive root according to the target primitive root. Then, the computer device performs butterfly operation on the third input polynomial according to the optimization factor, the target modulus and the next primitive root to obtain target output data to realize parallel calculation of number theory transformation.

[0172] In this way, the performance of parallel computing can be improved by utilizing multiple target primitive roots and an optimized data synchronization strategy. By performing data synchronization at each operation stage or at a specific stage and selecting an appropriate target primitive root, the computer device can perform number theory transformations more efficiently.

[0173] The present application also provides a computer-readable storage medium containing a computer program. When the computer program is executed by one or more processors, the one or more processors execute the parallel computing method for number theory transformation of the present application.

[0174] It is understood that a computer program includes computer program code. The computer program code may be in source code form, object code form, executable file or some intermediate form. Computer readable storage media may include: any entity or device capable of carrying computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), and software distribution medium.

[0175] In the description of this specification, the descriptions with reference to the terms "specifically", "further", "particularly", "understandably", etc. are intended to mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not intended to refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0176] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0177] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A parallel computing method for number theoretic transformations, characterized in that: The method comprises: Determine a target modulus, a target primitive root, and an optimization factor for optimizing the parallel calculation according to a first input polynomial inputted; Determining a second input polynomial according to the first input polynomial and the target modulus; Performing bit-reversal permutation processing on the second input polynomial according to the target primitive root to obtain a third input polynomial; According to the optimization factor, the target modulus and the target primitive root, the third input polynomial is processed by butterfly operation to obtain target output data, so as to realize parallel calculation of the number theory transformation.

2. The method according to claim 1, characterized in that The step of determining a target modulus, a target primitive root, and an optimization factor for optimizing the parallel computing according to the input first input polynomial comprises: Determine the target modulus and the target primitive root according to the first input polynomial; Performing logarithmic processing on the first input polynomial to obtain the number of operation stages; Determining, based on the first input polynomial, a factor of the number of terms of the first input polynomial; The optimization factor is determined according to the number of operation stages and the factor.

3. The method according to claim 1, characterized in that The method further comprises: Based on the target modulus, the target primitive root is verified.

4. The method according to claim 1, characterized in that: The step of determining a second input polynomial according to the first input polynomial and the target modulus comprises: According to the target modulus, performing a modulo operation on the coefficients of the first input polynomial to obtain first coefficients; The coefficients of the first input polynomial are updated according to the first coefficients to determine the second input polynomial.

5. The method according to claim 4, characterized in that The step of performing bit-reversal permutation processing on the second input polynomial according to the target primitive root to obtain a third input polynomial includes: The first coefficients are subjected to bit-reversal permutation processing according to the target primitive roots to obtain the third input polynomial.

6. The method according to claim 5, characterized in that The performing bit-reversal permutation processing on the first coefficient according to the target primitive root to obtain the third input polynomial includes: Performing binary coding processing on the first coefficient to obtain an initial binary coefficient; Reversing the bit order of the binary coefficients to obtain target binary coefficients; The third input polynomial is determined based on the target binary coefficients.

7. The method according to claim 1, characterized in that The target primitive root includes a plurality of roots, and the butterfly operation is performed on the third input polynomial according to the optimization factor, the target modulus and the target primitive root to obtain target output data to realize parallel calculation of number theory transformation, including: Determining the number of data synchronizations according to the number of operation stages and the optimization factor, the number of data synchronizations including at least one operation stage; In each data synchronization process, the third input polynomial is subjected to butterfly operation according to the target modulus and the current primitive root to obtain the target output data, so as to realize parallel calculation of number theory transformation.

8. The method according to claim 7, characterized in that In each process of performing the data synchronization processing, the number of times the butterfly operation processing is performed is i*2^(i-1), where i is the optimization factor.

9. The method according to claim 8, characterized in that The method further comprises: Determine the next primitive root of the current primitive root according to the target primitive root; According to the optimization factor, the target modulus and the next primitive root, the third input polynomial is processed by butterfly operation to obtain the target output data, so as to realize parallel calculation of number theory transformation.

10. A computer device, characterized in that: The computer device comprises a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the method according to any one of claims 1 to 9.

11. A computer storage medium, characterized in that: The computer-readable storage medium memory stores a computer program, and when the computer program is executed by one or more processors, the method according to any one of claims 1 to 9 is implemented.

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