Abnormal chip positioning method and device in multi-chip transmission, terminal and storage medium

Abstract

The invention discloses an abnormal chip positioning method and device in multi-chip transmission, a terminal and a storage medium, and relates to the technical field of chip detection. The method comprises the following steps: carrying out 3D-FFT calculation detection on a multi-chip machine for multiple times; and determining a plurality of transmission problem links according to the transmission error data during the subsequent 3D-FFT calculation detection for multiple times, and recording chips at cross points of the plurality of transmission problem links as abnormal chips. The invention provides an abnormal chip positioning method and device in multi-chip transmission, a terminal and a storage medium, and aims at a specific structure of a multi-chip machine system, 3D-FFT calculation is adopted to screen a defective chip, and the defective chip in a multi-chip machine can be quickly positioned, so that a designer can replace the defective chip in time, and the working efficiency of the designer is improved. Subsequent calculation errors can be avoided, and the design efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the field of chip detection technology, and in particular relates to a method, device, terminal and storage medium for locating abnormal chips in multi-chip transmission. Background Art

[0002] Semiconductor chip testing can be used to verify chip functions and performance, screen defective chips, and ensure product reliability, etc. It is of great significance in chip manufacturing and chip applications. With the development of the semiconductor industry, higher requirements are also placed on the performance and efficiency of semiconductor chip testing equipment.

[0003] Existing multi-chip machines are generally composed of M×N×K chips, and each chip is interconnected with adjacent chips. During the machine calculation process, data needs to be transmitted within the chip and between chips. Due to the use and wear of the machine, the chip may not be able to complete the transmission task correctly. When data is transmitted within the chip and between chips, occasional data jumps will occur, resulting in subsequent calculation errors. Therefore, a method is needed to locate abnormal transmission chips in a machine composed of multiple interconnected chips, so as to facilitate the subsequent timely replacement of abnormal chips and avoid subsequent calculation errors. Summary of the invention

[0004] In view of this, the present invention aims to propose a method, device, terminal and storage medium for locating abnormal chips in multi-chip transmission, so as to solve the problem of locating abnormal chips in transmission in a machine composed of multiple chips interconnected.

[0005] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0006] In a first aspect, the present invention provides a method for locating abnormal chips in multi-chip transmission, comprising:

[0007] Perform multiple 3D-FFT calculation tests on a multi-chip machine, and obtain the calculation status of each chip in the multi-chip machine during each 3D-FFT calculation test, to obtain the initial calculation result of the chip that stopped calculating during the first 3D-FFT calculation test, and the subsequent multiple calculation results of the chip that stopped calculating during the subsequent multiple 3D-FFT calculation tests; wherein each 3D-FFT calculation test includes multiple rounds of calculation and transmission, and each corresponding calculation result includes multiple single-round calculation sub-results;

[0008] Compare the subsequent multiple calculation results of the multiple 3D-FFT calculation detection with each single-round calculation sub-result in the initial calculation result one by one to obtain a comparison result, and determine the transmission error data of the subsequent multiple 3D-FFT calculation detection according to the comparison result;

[0009] A plurality of transmission problem links are determined according to the transmission error data during the subsequent multiple 3D-FFT calculation detections, and the chips at the intersections of the plurality of transmission problem links are recorded as abnormal chips.

[0010] Further, the multi-chip machine is subjected to multiple 3D-FFT calculation tests, and the calculation status of each chip in the multi-chip machine is obtained during each 3D-FFT calculation test, so as to obtain the initial calculation result of the chip that stops calculating during the first 3D-FFT calculation test, and the subsequent calculation results of the chip that stops calculating during the subsequent multiple 3D-FFT calculation tests, including:

[0011] Perform multiple 3D-FFT calculation tests on multi-chip machines; each 3D-FFT calculation test includes six rounds of calculations: X_FFT, Y_FFT, Z_FFT, Z_IFFT, X_IFFT, and Y_IFFT, and six rounds of transmission: Mesh2X, X2Y, Y2Z, Z2Y, Y2X, and X2Mesh;

[0012] Obtain the calculation status of the chip in the multi-chip machine during each 3D-FFT calculation detection, and obtain the chip that stops calculating after each 3D-FFT calculation detection;

[0013] The calculation result when the stopped calculation chip stops calculating for the first time is recorded as the initial calculation result, and the calculation results when the stopped calculation chip stops calculating multiple times subsequently are recorded as subsequent calculation results respectively; wherein each calculation result includes six single-round calculation sub-results.

[0014] Further, the subsequent multiple calculation results during the multiple 3D-FFT calculation detection are compared one by one with each single-round calculation sub-result in the initial calculation result to obtain a comparison result, and the transmission error data during the subsequent multiple 3D-FFT calculation detection is determined according to the comparison result to obtain the comparison result, including:

[0015] Compare the subsequent multiple calculation results during multiple 3D-FFT calculation detection with each single-round calculation sub-result in the initial calculation result one by one, and obtain the flag bits where the subsequent multiple calculation results are different from the initial calculation result; wherein the flag bits correspond one by one to the single-round calculation in the 3D-FFT calculation detection;

[0016] According to the different flag bits, the address of the transmission error in each subsequent 3D-FFT calculation detection is determined, and the data in the address where the initial calculation result is different from the subsequent multiple calculation results is obtained and recorded as the transmission error data.

[0017] Further, the determining of multiple transmission problem links according to the transmission error data during the subsequent multiple 3D-FFT calculation detections, and recording the chips at the intersections of the multiple transmission problem links as abnormal chips, includes:

[0018] Determine a transmission error chip according to the transmission error data;

[0019] Recording the transmission link between the stopped computing chip and the transmission error chip corresponding to each of the transmission error data as a transmission problem link;

[0020] The chips at the intersections of the multiple transmission problem links are recorded as abnormal chips.

[0021] Further, determining the transmission error chip according to the transmission error data includes:

[0022] A search is performed in a calculation round preceding the 3D-FFT calculation detection calculation round corresponding to the transmission error data to obtain the chip where the transmission error data is located, and the chip is recorded as the transmission error chip.

[0023] In a second aspect, an embodiment of the present invention further provides a device for locating abnormal chips in multi-chip transmission, comprising:

[0024] A calculation module is used to perform multiple 3D-FFT calculation tests on a multi-chip machine, and obtain the calculation status of the chips in the multi-chip machine during each 3D-FFT calculation test, to obtain the initial calculation result of the chip that stopped calculating during the first 3D-FFT calculation test, and the subsequent multiple calculation results of the chip that stopped calculating during the subsequent multiple 3D-FFT calculation tests; wherein each 3D-FFT calculation test includes multiple rounds of calculation and multiple rounds of transmission, and the calculation result of each 3D-FFT calculation test includes multiple single-round calculation sub-results;

[0025] A comparison module is used to compare the subsequent multiple calculation results of multiple 3D-FFT calculation detections with each single-round calculation sub-result in the initial calculation result one by one to obtain a comparison result, and determine the transmission error data of the subsequent multiple 3D-FFT calculation detections according to the comparison result;

[0026] The determination module is used to determine multiple transmission problem links according to the transmission error data during the subsequent multiple 3D-FFT calculation detections, and record the chips at the intersections of the multiple transmission problem links as abnormal chips.

[0027] Furthermore, the calculation module includes:

[0028] A multiple calculation unit is used to perform multiple 3D-FFT calculation tests on a multi-chip machine; each 3D-FFT calculation test includes six rounds of calculations, namely X_FFT, Y_FFT, Z_FFT, Z_IFFT, X_IFFT, and Y_IFFT, and six rounds of transmissions, namely Mesh2X, X2Y, Y2Z, Z2Y, Y2X, and X2Mesh;

[0029] A state monitoring unit is used to obtain the calculation state of the chips in the multi-chip machine during each 3D-FFT calculation detection, and obtain the chip that stops calculation after each 3D-FFT calculation detection;

[0030] The recording unit is used to record the calculation result when the stopped calculation chip stops calculating for the first time as the initial calculation result, and to record the calculation results when the stopped calculation chip stops calculating multiple times subsequently as the subsequent multiple calculation results; wherein each calculation result includes six single-round calculation sub-results.

[0031] Furthermore, the comparison module includes:

[0032] A comparison unit is used to compare the subsequent multiple calculation results during multiple 3D-FFT calculation detection with each single-round calculation sub-result in the initial calculation result, and obtain a flag bit where the subsequent multiple calculation results are different from the initial calculation result; wherein the flag bit corresponds to the single-round calculation in the 3D-FFT calculation detection;

[0033] The detection unit is used to determine the address of the transmission error in each subsequent 3D-FFT calculation detection according to the different flag bits, and obtain the data in the address where the initial calculation result is different from the subsequent multiple calculation results, and record it as transmission error data.

[0034] Furthermore, the determination module includes:

[0035] A search unit, used for determining a transmission error chip according to the transmission error data;

[0036] A marking unit, used for marking the transmission link between the stopped computing chip and the transmission error chip corresponding to each of the transmission error data as a transmission problem link;

[0037] The identification unit is used to mark the chips at the intersections of the multiple transmission problem links as abnormal chips.

[0038] In a third aspect, an embodiment of the present invention further provides a computing terminal, including:

[0039] one or more processors;

[0040] A storage device for storing one or more programs;

[0041] When the one or more programs are executed by the one or more processors, the one or more processors implement the method for locating abnormal chips in multi-chip transmission as described above.

[0042] In a fourth aspect, an embodiment of the present invention further provides a storage medium comprising computer executable instructions, which, when executed by a computer processor, are used to perform the method for locating abnormal chips in multi-chip transmission as described above.

[0043] Compared with the prior art, the method, device, terminal and storage medium for locating abnormal chips in multi-chip transmission described in the present invention have the following advantages:

[0044] The method for locating abnormal chips in multi-chip transmission described in this embodiment uses 3D-FFT calculation to screen problem chips based on the unique structure of the multi-chip machine system. It can quickly locate the problematic chips in the multi-chip machine, so that designers can replace the problematic chips in time, which is conducive to avoiding subsequent calculation errors and improving design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0046] Figure 1 This is a schematic flow chart of a method for locating an abnormal chip in multi-chip transmission according to the first embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of a 3D-FFT calculation detection process in a method for locating abnormal chips in multi-chip transmission according to the first embodiment of the present invention;

[0048] Figure 3 A schematic diagram of a data transmission process in a method for locating an abnormal chip in multi-chip transmission according to Embodiment 1 of the present invention;

[0049] Figure 4 This is a schematic diagram of the structure of a device for locating abnormal chips in multi-chip transmission according to the second embodiment of the present invention;

[0050] Figure 5 A schematic diagram of the structure of a computing terminal provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0051] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0052] Embodiment 1

[0053] Figure 1 The figure is a flow chart of a method for locating abnormal chips in multi-chip transmission according to the first embodiment of the present invention.

[0054] Since it is necessary to correct the abnormal chips when designing a multi-chip machine, the positioning method of this embodiment can quickly locate the transmission abnormal chip of a machine composed of multiple interconnected chips.

[0055] See also Figure 1 , this positioning method specifically includes the following steps:

[0056] Step 101: perform multiple 3D-FFT calculation tests on the multi-chip machine, and obtain the calculation status of each chip in the multi-chip machine during each 3D-FFT calculation test, to obtain the initial calculation result of the chip that stopped calculating during the first 3D-FFT calculation test, and the subsequent multiple calculation results of the chip that stopped calculating during subsequent multiple 3D-FFT calculation tests; wherein each 3D-FFT calculation test includes multiple rounds of calculation and transmission, and each corresponding calculation result includes multiple single-round calculation sub-results.

[0057] Since there is no method for locating transmission anomalies of multi-chip machines, this embodiment adopts the Q-point 3D-FFT method and a single-round multiple-time calculation method. 3D-FFT is a detection method here. It uses its large transmission volume and the characteristics of covering many chips during transmission to check whether there is a problem with chip transmission. It can also quickly locate the transmission abnormal chip during the machine test process to improve debugging efficiency.

[0058] At the same time, due to the transmission characteristics of multi-chip machines, when there is a problem with the transmission of the chip, the input data will jump. For example, a data with a bit width of E bits will be inverted at a certain bit, from 1 to 0, or from 0 to 1. This will cause the input of the calculation to be wrong, and ultimately lead to wrong calculation results. The above phenomenon is sporadic and does not occur in every round, so multiple calculations are required to ensure that the above phenomenon occurs. The huge amount of calculation and transmission of Q-point 3D-FFT makes Q-point 3D-FFT very suitable for locating chip transmission problems.

[0059] Based on this, this embodiment adopts a single-round multiple-time calculation method, and each calculation round in each 3D-FFT calculation test performs the same calculation, and retains the initial calculation result and the subsequent multiple calculation results. After multiple calculations, the broken chip will have the problem of unstable transmission. The purpose of this method is to catch the broken chip and replace it with a good chip in time to ensure the correct calculation of the machine.

[0060] Step 102: Compare the subsequent multiple calculation results of multiple 3D-FFT calculation detections with each single-round calculation sub-result in the initial calculation result one by one to obtain a comparison result, and determine the transmission error data of the subsequent multiple 3D-FFT calculation detections according to the comparison result.

[0061] The initial calculation result is retained because the chip device is relatively special, the initial calculation and transmission are generally relatively stable, and the calculation result is correct. Therefore, this embodiment can effectively locate the chip with unstable transmission by running multiple cycles and using the initial calculation result as the judgment standard.

[0062] In actual application, each calculation round in each 3D-FFT calculation test performs the same calculation, and the subsequent multiple calculation results during multiple 3D-FFT calculation tests are compared one by one with the single-round calculation sub-results in the initial calculation results. If there is a single-round calculation sub-result in the subsequent multiple calculation results that is different from the initial calculation result, it means that a data transmission error has occurred and the transmitted data has bit jumps, that is, transmission error data is obtained.

[0063] Step 103: Determine multiple transmission problem links according to the transmission error data during multiple 3D-FFT calculation detections, and record the chips at the intersections of the multiple transmission problem links as abnormal chips.

[0064] Since transmission error data may pass through more than one chip during transmission, each chip through which the transmission passes may cause transmission errors due to chip failure. Therefore, in order to further accurately locate the problem chip, this embodiment performs multiple 3D-FFT calculation tests, and determines multiple transmission problem links based on the transmission error data during the multiple 3D-FFT calculation tests, so that the problem chip can be displayed in multiple transmission problem links, and the chip at the intersection of multiple transmission problem links is the abnormal chip.

[0065] In actual multiple tests, if the transmission link of the transmission error data data_0 during the first 3D-FFT calculation detection is located from chip_B to chip_C, and finally reaches chip_A, during the second 3D-FFT calculation detection, the transmission link of the transmission error data data_1 is located from chip_D to chip_B, chip_E, and finally reaches chip_F. Both links pass through chip_B, so chip_B is judged to be the chip with abnormal transmission, that is, the abnormal chip.

[0066] Preferably, step 101, performing multiple 3D-FFT calculation tests on a multi-chip machine, and obtaining the calculation status of each chip in the multi-chip machine during each 3D-FFT calculation test, obtaining the initial calculation result of the chip that stops calculating during the first 3D-FFT calculation test, and the subsequent multiple calculation results of the chip that stops calculating during the subsequent multiple 3D-FFT calculation tests, specifically includes the following steps:

[0067] Step 1011, perform multiple 3D-FFT calculation tests on the multi-chip machine; wherein each 3D-FFT calculation test includes six rounds of calculations, namely X_FFT, Y_FFT, Z_FFT, Z_IFFT, X_IFFT, and Y_IFFT, and six rounds of transmission, namely Mesh2X, X2Y, Y2Z, Z2Y, Y2X, and X2Mesh.

[0068] Figure 2 This is a schematic diagram of the 3D-FFT calculation detection process in a method for locating abnormal chips in multi-chip transmission according to the first embodiment of the present invention. Figure 2 A single 3D-FFT calculation detection includes six rounds of calculation: X_FFT, Y_FFT, Z_FFT, Z_IFFT, X_IFFT, and Y_IFFT, as well as six rounds of transmission: Mesh2X, X2Y, Y2Z, Z2Y, Y2X, and X2Mesh. The huge amount of calculation and transmission makes Q-point 3D-FFT very suitable for locating chip transmission problems.

[0069] Step 1012: Obtain the computing status of the chips in the multi-chip machine during each 3D-FFT computing detection, and obtain the chip that stops computing after each 3D-FFT computing detection.

[0070] In actual application, it is common to make judgments in the program. If the transmission results are inconsistent, the program will be stuck at this step, that is, the chip stops calculating here. At this time, a flag indicating inconsistent transmission at this place can be written at a specific address, so that the address of the erroneous data can be determined later based on the flag.

[0071] Step 1013, record the calculation result when the stopped calculation chip stops calculating for the first time as the initial calculation result, and record the calculation results when the stopped calculation chip stops calculating multiple times subsequently as subsequent calculation results; wherein each calculation result includes six single-round calculation sub-results.

[0072] In actual applications, when performing multiple 3D-FFT calculation tests on a multi-chip machine, different stopped calculation chips may appear. Therefore, it is necessary to record the initial calculation results and subsequent multiple calculation results of each stopped calculation chip.

[0073] Preferably, step 102, comparing the subsequent multiple calculation results during multiple 3D-FFT calculation detections with each single-round calculation sub-result in the initial calculation result one by one to obtain a comparison result, and determining the transmission error data during the subsequent multiple 3D-FFT calculation detections according to the comparison result to obtain the comparison result, specifically includes the following steps:

[0074] Step 1021: Compare the subsequent multiple calculation results during multiple 3D-FFT calculation detection with each single-round calculation sub-result in the initial calculation result one by one to obtain a flag bit where the subsequent multiple calculation results are different from the initial calculation result; wherein the flag bit corresponds one by one to the single-round calculation in the 3D-FFT calculation detection.

[0075] Step 1022: Determine the address of the transmission error in each subsequent 3D-FFT calculation detection according to the different flag bits, and obtain data in the address where the initial calculation result is different from the subsequent multiple calculation results, and record it as transmission error data.

[0076] For example, taking flag 4 (Z_FFT) as an example, this flag indicates that the input of Z_FFT after multiple 3D-FFT calculations and detections is different from the result of the first calculation. First, by comparing addr_z_fft_in and addr_z_fft_in_0, the different data in the two addresses are found. The different data in addr_z_fft_in is recorded as wrong_data, and the different data in addr_z_fft_in_0 is recorded as data_0 (that is, the corresponding transmission error data during the current 3D-FFT calculation detection).

[0077] In actual application, through multiple 3D-FFT calculations and detections, when there is an abnormal chip, it is highly likely that multiple transmission error data can be obtained, and these transmission error data can be found in different addresses.

[0078] Preferably, step 103, determining multiple transmission problem links according to the transmission error data during the subsequent multiple 3D-FFT calculation detections, and recording the chips at the intersections of the multiple transmission problem links as abnormal chips, specifically includes the following steps:

[0079] Step 1031: Determine a transmission error chip according to the transmission error data.

[0080] In actual application, a search may be performed in a calculation round before the 3D-FFT calculation detection calculation round corresponding to the transmission error data to obtain the chip where the transmission error data is located and record it as the transmission error chip.

[0081] Step 1032: Record the transmission link between the stopped computing chip and the transmission error chip corresponding to each of the transmission error data as a transmission problem link;

[0082] Step 1033: Record the chips at the intersections of the multiple transmission problem links as abnormal chips.

[0083] In actual application, you can search for data_0 (i.e., the transmission error data during the initial 3D-FFT calculation test) in addr_y_fft_out, and record the chip where data_0 is located as chip_B. Then it can be determined that the data with bit jumps is sent from chip_B to chip_A, and this step can determine the data transmission link. However, since the data from chip_B to chip_A may pass through more than one chip, multiple 3D-FFT calculation tests are required.

[0084] Figure 3 This is a schematic diagram of the data transmission process in a method for locating abnormal chips in multi-chip transmission according to the first embodiment of the present invention. Figure 2 In multiple 3D-FFT calculation tests, at least two 3D-FFT calculation tests are required. If the transmission link of the abnormal data data_0 is located first as chip_B to chip_C, and finally reaches chip_A. Then after the second calculation, the transmission link of the abnormal data data_1 (that is, the transmission error data during the second 3D-FFT calculation test) is located as chip_D to chip_B, chip_E, and finally reaches chip_F. Both links pass through chip_B, so it can be determined that chip_B is the chip with abnormal transmission.

[0085] The method for locating abnormal chips in multi-chip transmission described in this embodiment performs multiple 3D-FFT calculation tests on the multi-chip machine, and obtains the calculation status of each chip in the multi-chip machine during each 3D-FFT calculation test, so as to obtain the initial calculation result of the chip that stops calculating during the first 3D-FFT calculation test, and the subsequent multiple calculation results of the chip that stops calculating during the subsequent multiple 3D-FFT calculation tests; wherein each 3D-FFT calculation test includes multiple rounds of calculation and transmission, and each corresponding calculation result includes multiple single-round calculation sub-results; then, the subsequent multiple calculation results during the multiple 3D-FFT calculation tests are compared one by one with each single-round calculation sub-result in the initial calculation result to obtain a comparison result, and the transmission error data during the subsequent multiple 3D-FFT calculation tests is determined according to the comparison result; finally, multiple transmission problem links are determined according to the transmission error data during the subsequent multiple 3D-FFT calculation tests, and the chips at the intersection of the multiple transmission problem links are recorded as abnormal chips.

[0086] Compared with the prior art, the method for locating abnormal chips in multi-chip transmission described in this embodiment targets the unique structure of the multi-chip machine system and uses Q-point 3D-FFT calculation to screen problem chips. It can quickly locate problematic chips in the multi-chip machine, so that designers can replace the problematic chips in time, which is conducive to avoiding subsequent calculation errors and improving design efficiency.

[0087] Embodiment 2

[0088] Figure 4 This is a schematic diagram of the structure of a device for locating abnormal chips in multi-chip transmission according to the second embodiment of the present invention. Figure 4 , such a device comprises:

[0089] The calculation module 201 is used to perform multiple 3D-FFT calculation tests on the multi-chip machine, and obtain the calculation status of the chips in the multi-chip machine during each 3D-FFT calculation test, to obtain the initial calculation result of the chip that stopped calculating during the first 3D-FFT calculation test, and the subsequent multiple calculation results of the chip that stopped calculating during subsequent multiple 3D-FFT calculation tests; wherein each 3D-FFT calculation test includes multiple rounds of calculation and multiple rounds of transmission, and the calculation result of each 3D-FFT calculation test includes multiple single-round calculation sub-results.

[0090] The comparison module 202 is used to compare the subsequent multiple calculation results during multiple 3D-FFT calculation detection with each single-round calculation sub-result in the initial calculation result one by one to obtain a comparison result, and determine the transmission error data during the subsequent multiple 3D-FFT calculation detection according to the comparison result.

[0091] The determination module 203 is used to determine multiple transmission problem links according to the transmission error data during the subsequent multiple 3D-FFT calculation detections, and record the chips at the intersections of the multiple transmission problem links as abnormal chips.

[0092] Preferably, the calculation module 201 includes:

[0093] A multiple calculation unit is used to perform multiple 3D-FFT calculation tests on a multi-chip machine; each 3D-FFT calculation test includes six rounds of calculations, namely X_FFT, Y_FFT, Z_FFT, Z_IFFT, X_IFFT, and Y_IFFT, and six rounds of transmissions, namely Mesh2X, X2Y, Y2Z, Z2Y, Y2X, and X2Mesh;

[0094] A state monitoring unit is used to obtain the calculation state of the chips in the multi-chip machine during each 3D-FFT calculation detection, and obtain the chip that stops calculation after each 3D-FFT calculation detection;

[0095] The recording unit is used to record the calculation result when the stopped calculation chip stops calculating for the first time as the initial calculation result, and to record the calculation results when the stopped calculation chip stops calculating multiple times subsequently as the subsequent multiple calculation results; wherein each calculation result includes six single-round calculation sub-results.

[0096] Preferably, the comparison module 202 includes:

[0097] A comparison unit is used to compare the subsequent multiple calculation results during multiple 3D-FFT calculation detection with each single-round calculation sub-result in the initial calculation result, and obtain a flag bit where the subsequent multiple calculation results are different from the initial calculation result; wherein the flag bit corresponds to the single-round calculation in the 3D-FFT calculation detection;

[0098] The detection unit is used to determine the address of the transmission error in each subsequent 3D-FFT calculation detection according to the different flag bits, and obtain the data in the address where the initial calculation result is different from the subsequent multiple calculation results, and record it as transmission error data.

[0099] Preferably, the determining module 203 includes:

[0100] A search unit, used for determining a transmission error chip according to the transmission error data;

[0101] A marking unit, used for marking the transmission link between the stopped computing chip and the transmission error chip corresponding to each of the transmission error data as a transmission problem link;

[0102] The identification unit is used to mark the chips at the intersections of the multiple transmission problem links as abnormal chips.

[0103] An apparatus for locating abnormal chips in multi-chip transmission provided by an embodiment of the present invention can execute a method for locating abnormal chips in multi-chip transmission provided by any embodiment of the present invention, and has corresponding functional modules and beneficial effects of the execution method.

[0104] Embodiment 3

[0105] Figure 5 A schematic diagram of the structure of a computing terminal provided in Embodiment 3 of the present invention; Figure 5 A block diagram of an exemplary terminal suitable for implementing embodiments of the present invention is shown. Figure 5 The terminal shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0106] like Figure 5As shown, the terminal 12 is in the form of a general purpose computing device. The components of the terminal 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0107] Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or a local bus using any of a variety of bus architectures. By way of example, these architectures include, but are not limited to, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MAC) bus, an Enhanced ISA bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0108] Terminal 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by terminal 12, including volatile and non-volatile media, removable and non-removable media.

[0109] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Terminal 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media ( Figure 5 not shown, usually called a "hard drive"). Although Figure 5 Not shown in the figure, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present invention.

[0110] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described herein.

[0111] The terminal 12 may also communicate with one or more external devices 14 (e.g., keyboards, pointing devices, displays 24, etc.), may communicate with one or more devices that enable a user to interact with the terminal 12, and / or may communicate with any device that enables the terminal 12 to communicate with one or more other computing devices (e.g., network cards, modems, etc.). Such communication may be performed via an input / output (I / O) interface 22. Furthermore, the terminal 12 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 20. As shown, the network adapter 20 communicates with other modules of the terminal 12 via a bus 18. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the terminal 12, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0112] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the method for locating abnormal chips in multi-chip transmission provided by the embodiment of the present invention.

[0113] Embodiment 4

[0114] Embodiment 4 of the present invention further provides a storage medium containing computer executable instructions, which, when executed by a computer processor, are used to execute any of the methods for locating abnormal chips in multi-chip transmission provided in the above embodiments.

[0115] The computer storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0116] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0117] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0118] Computer program code for performing the operations of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0119] Embodiment 5

[0120] Embodiment 5 of the present invention further provides a computer product, including a computer program, which, when executed by a processor, implements the method for locating abnormal chips in multi-chip transmission as described in the above embodiments.

[0121] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for locating abnormal chips in multi-chip transmission, characterized in that: include: Perform multiple 3D-FFT calculation tests on a multi-chip machine, and obtain the calculation status of each chip in the multi-chip machine during each 3D-FFT calculation test, to obtain the initial calculation result of the chip that stopped calculating during the first 3D-FFT calculation test, and the subsequent multiple calculation results of the chip that stopped calculating during the subsequent multiple 3D-FFT calculation tests; wherein each 3D-FFT calculation test includes multiple rounds of calculation and transmission, and each corresponding calculation result includes multiple single-round calculation sub-results; Compare the subsequent multiple calculation results of the multiple 3D-FFT calculation detection with each single-round calculation sub-result in the initial calculation result one by one to obtain a comparison result, and determine the transmission error data of the subsequent multiple 3D-FFT calculation detection according to the comparison result; A plurality of transmission problem links are determined according to the transmission error data during the subsequent multiple 3D-FFT calculation detections, and the chips at the intersections of the plurality of transmission problem links are recorded as abnormal chips.

2. The method according to claim 1, characterized in that The method performs multiple 3D-FFT calculation tests on the multi-chip machine, obtains the calculation status of each chip in the multi-chip machine during each 3D-FFT calculation test, obtains the initial calculation result of the chip that stops calculating during the first 3D-FFT calculation test, and obtains the subsequent calculation results of the chip that stops calculating during the subsequent multiple 3D-FFT calculation tests, including: Perform multiple 3D-FFT calculation tests on multi-chip machines; each 3D-FFT calculation test includes six rounds of calculations: X_FFT, Y_FFT, Z_FFT, Z_IFFT, X_IFFT, and Y_IFFT, and six rounds of transmission: Mesh2X, X2Y, Y2Z, Z2Y, Y2X, and X2Mesh; Obtain the calculation status of the chip in the multi-chip machine during each 3D-FFT calculation detection, and obtain the chip that stops calculating after each 3D-FFT calculation detection; The calculation result when the stopped calculation chip stops calculating for the first time is recorded as the initial calculation result, and the calculation results when the stopped calculation chip stops calculating multiple times subsequently are recorded as subsequent calculation results respectively; wherein each calculation result includes six single-round calculation sub-results.

3. The method according to claim 1, characterized in that The subsequent multiple calculation results of the multiple 3D-FFT calculation detections are compared one by one with each single-round calculation sub-result in the initial calculation result to obtain a comparison result, and the transmission error data of the subsequent multiple 3D-FFT calculation detections is determined according to the comparison result to obtain the comparison result, including: Compare the subsequent multiple calculation results during multiple 3D-FFT calculation detection with each single-round calculation sub-result in the initial calculation result one by one, and obtain the flag bits where the subsequent multiple calculation results are different from the initial calculation result; wherein the flag bits correspond one by one to the single-round calculation in the 3D-FFT calculation detection; According to the different flag bits, the address of the transmission error in each subsequent 3D-FFT calculation detection is determined, and the data in the address where the initial calculation result is different from the subsequent multiple calculation results is obtained and recorded as the transmission error data.

4. The method according to claim 1, characterized in that The determining of multiple transmission problem links according to the transmission error data during the subsequent multiple 3D-FFT calculation detections, and marking the chips at the intersections of the multiple transmission problem links as abnormal chips, includes: Determine a transmission error chip according to the transmission error data; Recording the transmission link between the stopped computing chip and the transmission error chip corresponding to each of the transmission error data as a transmission problem link; The chips at the intersections of the multiple transmission problem links are recorded as abnormal chips.

5. The method according to claim 4, characterized in that The step of determining the transmission error chip according to the transmission error data comprises: A search is performed in a calculation round preceding the 3D-FFT calculation detection calculation round corresponding to the transmission error data to obtain the chip where the transmission error data is located, and the chip is recorded as the transmission error chip.

6. A device for locating abnormal chips in multi-chip transmission, characterized in that: include: A calculation module is used to perform multiple 3D-FFT calculation tests on a multi-chip machine, and obtain the calculation status of the chips in the multi-chip machine during each 3D-FFT calculation test, to obtain the initial calculation result of the chip that stopped calculating during the first 3D-FFT calculation test, and the subsequent multiple calculation results of the chip that stopped calculating during the subsequent multiple 3D-FFT calculation tests; wherein each 3D-FFT calculation test includes multiple rounds of calculation and multiple rounds of transmission, and the calculation result of each 3D-FFT calculation test includes multiple single-round calculation sub-results; A comparison module is used to compare the subsequent multiple calculation results of multiple 3D-FFT calculation detections with each single-round calculation sub-result in the initial calculation result one by one to obtain a comparison result, and determine the transmission error data of the subsequent multiple 3D-FFT calculation detections according to the comparison result; The determination module is used to determine multiple transmission problem links according to the transmission error data during the subsequent multiple 3D-FFT calculation detections, and record the chips at the intersections of the multiple transmission problem links as abnormal chips.

7. The device according to claim 6, characterized in that The calculation module comprises: A multiple calculation unit is used to perform multiple 3D-FFT calculation tests on a multi-chip machine; each 3D-FFT calculation test includes six rounds of calculations, namely X_FFT, Y_FFT, Z_FFT, Z_IFFT, X_IFFT, and Y_IFFT, and six rounds of transmissions, namely Mesh2X, X2Y, Y2Z, Z2Y, Y2X, and X2Mesh; A state monitoring unit is used to obtain the calculation state of the chips in the multi-chip machine during each 3D-FFT calculation detection, and obtain the chip that stops calculation after each 3D-FFT calculation detection; The recording unit is used to record the calculation result when the stopped calculation chip stops calculating for the first time as the initial calculation result, and to record the calculation results when the stopped calculation chip stops calculating multiple times subsequently as the subsequent multiple calculation results; wherein each calculation result includes six single-round calculation sub-results.

8. The device according to claim 6, characterized in that The comparison module comprises: A comparison unit is used to compare the subsequent multiple calculation results during multiple 3D-FFT calculation detection with each single-round calculation sub-result in the initial calculation result, and obtain a flag bit where the subsequent multiple calculation results are different from the initial calculation result; wherein the flag bit corresponds to the single-round calculation in the 3D-FFT calculation detection; The detection unit is used to determine the address of the transmission error in each subsequent 3D-FFT calculation detection according to the different flag bits, and obtain the data in the address where the initial calculation result is different from the subsequent multiple calculation results, and record it as transmission error data.

9. The device according to claim 6, characterized in that The determination module comprises: A search unit, used for determining a transmission error chip according to the transmission error data; A marking unit, used for marking the transmission link between the stopped computing chip and the transmission error chip corresponding to each of the transmission error data as a transmission problem link; The identification unit is used to mark the chips at the intersections of the multiple transmission problem links as abnormal chips.

10. A computing terminal, characterized in that: include: one or more processors; A storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the abnormal chip locating method in multi-chip transmission as described in any one of claims 1-5.

11. A storage medium containing computer executable instructions, characterized in that: The computer executable instructions are used to execute the abnormal chip locating method in multi-chip transmission according to any one of claims 1 to 5 when executed by a computer processor.

12. A computer product, comprising a computer program, characterized in that: When the computer program is executed by a processor, the method for locating abnormal chips in multi-chip transmission according to any one of claims 1 to 5 is implemented.

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