Chip test data analysis method

Abstract

The invention provides a chip test data analysis method. The chip test data analysis method comprises the following steps: 1, firstly, collecting test data by adopting a data collection module, and then dividing the data into single-table data and multi-table data through a single-table data processing module and a multi-table data processing module, in the process, the data processed by the single-table data processing module is judged through a judgment module; and 2, if the data is qualified, forming a data table and displaying the data table through a single table data display module, and if the data is unqualified, processing the data table through a failure data processing module. According to the chip test data analysis method provided by the invention, the test data of different test systems can be quickly and automatically arranged and analyzed through the method. And data arrangement can be completed conveniently and quickly in a time-saving and labor-saving Parameter differences of chips of different batches can be found through data arrangement and analysis and are fed back to a design end to effectively analyze a failure mode, design is improved, and the manufacturing yield is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of chip test data analysis, and in particular to a chip test data analysis method. Background Art

[0002] Chip testing, system-level chip testing in the early stage of design, the basis of SoC is deep submicron technology, therefore, a new method is needed to test Soc devices. Since each functional component has its own testing requirements, design engineers must make test plans in the early stage of design.

[0003] Semiconductor finished product testing is the last testing stage after the chip is packaged. Its purpose is to ensure the performance and reliability of the chip in actual applications. FT testing includes environmental testing, aging testing and specific application performance testing.

[0004] A large amount of data will be generated during the testing process, which are all valuable first-hand information. In the FT testing stage, by sorting and analyzing a large amount of test data, the differences in chip parameters in different batches can be discovered. By checking the differences in the data, it is easy to locate the problem points, improve the design and increase the manufacturing yield. Due to the large amount of test data, it will be time-consuming and laborious to manually calculate the mean, standard deviation, etc.

[0005] Therefore, it is necessary to provide a chip test data analysis method to solve the above technical problems. Summary of the invention

[0006] The present invention provides a chip test data analysis method, which solves the problem that it is time-consuming and laborious to manually calculate the mean and standard deviation of a large amount of chip test data.

[0007] In order to solve the above technical problems, the chip test data analysis method provided by the present invention comprises the following steps:

[0008] Step 1: First, the data acquisition module is used to collect the test data, and then the data is divided into single-table data and multi-table data through the single-table data processing module and the multi-table data processing module. In this process, the judgment module judges the data processed by the single-table data processing module;

[0009] Step 2: If the data is qualified, a data table is formed and displayed through the single-table data display module. If it is unqualified, it is processed by the failure data processing module. After the multi-table data processing module completes the processing, it is displayed through the multi-table data display module.

[0010] Step 3: After the data is sorted, import the prepared test data into the running test software, judge the data by data format, if it is valid, raise the upper and lower limits of IC test items, put it into the container for standby, if it is invalid, exit and give the invalid reason;

[0011] Step 4: If you select A for valid data, only the defective data will be marked with color, and the failure data of each test item will be displayed, and then the software will be exited. If you select B, it will be determined whether it is multiple data from different batches of the same IC. If multiple data are selected, it is necessary to determine whether the parameter name and upper and lower limits of each item in the multiple data are consistent. If the result is no, then exit. If the invalid reason is given and the result is yes, then it will be determined as a single data, and the mean value u, standard deviation 0, maximum value, minimum value, failure number, failure rate, etc. of each test item of the IC will be displayed;

[0012] Step 5: Generate a table with mean u, standard deviation, maximum value, minimum value, number of failures, failure rate, failure histogram, and 6sigma diagram;

[0013] During the test data analysis process, the failed data in the test data are marked in red, highlighting the bad parameter items for quick location, and calculating and displaying the failure number and failure rate of each test parameter. This allows for a general and detailed grasp of the product, while analyzing the test data as a whole, displaying the mean, standard deviation, and distribution range of each parameter item, and collating and analyzing the parameters of different batches of the same IC. It is developed using VBA, loaded into EXCEL, and can be started and run through shortcut keys after opening the data to be analyzed.

[0014] Preferably, the single-table data processing module comprises a user login unit, and the output end of the user login unit is connected to the input end of the invalid data highlighting unit;

[0015] The user login unit requires the operator's name to be entered to facilitate locating the individual who is processing the data.

[0016] Preferably, a chip test data analysis method, wherein the data acquisition module is a data acquisition device, further comprising two support frames, the tops of the two support frames are fixedly connected with a test bench, the top of the test bench is equipped with an operating computer, and the top of the test bench is equipped with a mounting frame;

[0017] The mounting bracket is located on the top of the test bench near the side.

[0018] Preferably, a processing device is installed on the top of the mounting frame, and a wire placing box is installed on the front of the mounting frame;

[0019] The processing equipment is used synchronously with the data collector.

[0020] Preferably, the top and bottom of the wire-releasing box are provided with threading openings, the insides of the threading openings are provided with soft wool lines, and a mounting plate is installed on the back of the inner wall of the wire-releasing box;

[0021] Soft wool wire can prevent dust from entering the wire box through the wire threading port.

[0022] Preferably, a fixing plate is installed on the back of the inner wall of the wire placing box near the top and the bottom, a plurality of wire buckles are installed on the front of the fixing plate, a cover is provided on the front of the wire placing box, and a sealing plug is installed on the back of the cover;

[0023] The wire buckle can limit the line, and the line is inserted into the inside of the wire buckle

[0024] Preferably, a data collector is installed on the front of the mounting frame, and a connecting line is provided at the bottom of the data collector;

[0025] Wire clips also need to be installed at the locations where the connecting wires are distributed.

[0026] Preferably, a control switch is installed on one side of the mounting frame through a mounting base, and a control box with a door is installed on one side of one of the support frames;

[0027] The control box is equipped with a power switch and a controller for controlling the operation of the equipment, and a lock is provided on the door of the box.

[0028] A chip test data analysis method comprises the following steps:

[0029] Step 1: First, sort the data collected by the data acquisition module through the data sorting module, and then classify it through the data classification module to ensure data stability analysis and consistency analysis, and classify it according to data failure ratio and data distribution:

[0030] Step 2: After the classification, the data is stored in the data storage module. When testing is required, the data testing module extracts data from the data storage module. Then the data is judged by the data judgment module. If it is valid, it is displayed in the result display module:

[0031] Step 3: If invalid, it will be marked by the data marking module and then displayed by the result display module. The valid or invalid test data will be stored separately by the data storage module.

[0032] The data classification module includes single data and multiple data, and the data sorting module can calculate the mean u, standard deviation, maximum value, minimum value, number of failures, failure rate, and failure histogram of the data.

[0033] Compared with the related art, the chip test data analysis method provided by the present invention has the following beneficial effects:

[0034] The present invention provides a chip test data analysis method. In order to improve the chip test data analysis efficiency, a data acquisition module is first used to collect test data, and then the data is divided into single-table data and multi-table data through a single-table data processing module and a multi-table data processing module. In this process, the data processed by the single-table data processing module is judged by a judgment module. If qualified, a data table is formed and displayed by a single-table data display module. If unqualified, it is processed by a failure data processing module, and after the multi-table data processing module completes the processing, it is displayed by a multi-table data display module. After the data is sorted, the prepared test data is imported into the running test software, and the data is judged by a data format judgment. If the upper and lower limits of IC test items are effectively raised, the data is put into a container for standby use. If the result is invalid, exit and give the invalid reason. If the valid data is selected A, only the defective data is marked with color, and the failure data of each test item is displayed, and then exit the software. If B is selected to determine whether it is multiple data from different batches of the same IC, and multiple data need to determine whether the parameter name and upper and lower limits of each item in the multiple data are consistent, the result is no, exit, give the invalid reason, and the result is yes and judged as a single data. The mean value u, standard deviation 0, maximum value, minimum value, number of failures, failure rate, etc. of each test item of IC are finally generated with the mean u, standard deviation maximum value, minimum value, number of failures, failure rate, failure histogram, and 6sigma chart. This method can quickly and automatically organize and analyze the test data of different test systems, which is convenient, fast, and time-saving and labor-saving to complete data organization. Through data organization and analysis, the differences in chip parameters of different batches can be found, and feedback can be given to the design end to effectively analyze the failure mode, improve the design and increase the manufacturing yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the structure of a first embodiment of a chip test data analysis method provided by the present invention;

[0036] Figure 2 A schematic diagram of data format determination is provided for the present invention;

[0037] Figure 3 A schematic diagram of a single-table data processing module is provided for the present invention;

[0038] Figure 4 A structural schematic diagram of a mounting frame is provided for the present invention;

[0039] Figure 5 A structural schematic diagram of a control switch is provided for the present invention;

[0040] Figure 6 A structural schematic diagram of a mounting plate is provided for the present invention;

[0041] Figure 7 A structural schematic diagram of a sealing plug is provided for the present invention;

[0042] Figure 8 A schematic diagram of the structure of a second embodiment of the chip test data analysis method provided by the present invention;

[0043] Fig. 9 A schematic diagram of a data testing module is provided for the present invention;

[0044] Fig.10 A schematic diagram of a data classification module is provided for the present invention.

[0045] Numbers in the figure: 1. Support frame, 2. Test bench, 3. Connecting wire, 4. Data logger, 5. Mounting frame, 6. Lighting, 7. Wire box, 8. Processing equipment, 9. Operating computer, 10. Mounting base, 11. Control switch, 12. Box door, 13. Control box, 14. Mounting plate, 15. Wire buckle, 16. Fixing plate, 17. Soft wool wire, 18. Threading port, 19. Sealing plug, 20. Cover. DETAILED DESCRIPTION

[0046] The present invention will be further described below in conjunction with the accompanying drawings and implementation modes.

[0047] Please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 ,in, Figure 1 A schematic diagram of the structure of a first embodiment of a chip test data analysis method provided by the present invention; Figure 2 A schematic diagram of data format determination is provided for the present invention; Figure 3 A schematic diagram of a single-table data processing module is provided for the present invention;

[0048] Figure 4 A structural schematic diagram of a mounting frame is provided for the present invention; Figure 5 A structural schematic diagram of a control switch is provided for the present invention; Figure 6 A structural schematic diagram of a mounting plate is provided for the present invention; Figure 7 The present invention provides a structural schematic diagram of a sealing plug. The chip test data analysis method comprises the following steps:

[0049] Step 1: First, the data acquisition module is used to collect the test data, and then the data is divided into single-table data and multi-table data through the single-table data processing module and the multi-table data processing module. In this process, the judgment module judges the data processed by the single-table data processing module;

[0050] Step 2: If the data is qualified, a data table is formed and displayed through the single-table data display module. If it is unqualified, it is processed by the failure data processing module. After the multi-table data processing module completes the processing, it is displayed through the multi-table data display module.

[0051] Step 3: After the data is sorted, import the prepared test data into the running test software, judge the data by data format, if it is valid, raise the upper and lower limits of IC test items, put it into the container for standby, if it is invalid, exit and give the invalid reason;

[0052] Step 4: If you select A for valid data, only the defective data will be marked with color, and the failure data of each test item will be displayed, and then the software will be exited. If you select B, it will be determined whether it is multiple data from different batches of the same IC. If multiple data are selected, it is necessary to determine whether the parameter name and upper and lower limits of each item in the multiple data are consistent. If the result is no, then exit. If the invalid reason is given and the result is yes, then it will be determined as a single data, and the mean value u, standard deviation 0, maximum value, minimum value, failure number, failure rate, etc. of each test item of the IC will be displayed;

[0053] Step 5: Generate a table with mean u, standard deviation, maximum value, minimum value, number of failures, failure rate, failure histogram, and 6sigma diagram;

[0054] During the test data analysis process, the failed data in the test data are marked in red, highlighting the bad parameter items for quick location, and calculating and displaying the failure number and failure rate of each test parameter. This allows for a general and detailed grasp of the product, while analyzing the test data as a whole, displaying the mean, standard deviation, and distribution range of each parameter item, and collating and analyzing the parameters of different batches of the same IC. It is developed using VBA, loaded into EXCEL, and can be started and run through shortcut keys after opening the data to be analyzed.

[0055] The single-table data processing module comprises a user login unit, an output end of the user login unit is connected to an input end of the invalid data highlighting unit;

[0056] The user login unit requires the operator's name to be entered to facilitate the individual location of the staff member processing the data, and the invalid data highlighting unit can color-code abnormal data.

[0057] A chip test data analysis method, wherein the data acquisition module is a data acquisition device 4, and further comprises two support frames 1, the tops of the two support frames 1 are fixedly connected with a test bench 2, the tops of the test bench 2 are installed with an operating computer 9, and the tops of the test bench 2 are installed with a mounting frame 5;

[0058] The mounting frame 5 is located at a position on the top of the test bench 2 near one side, and the operating computer 9 is located at a position on the top of the test bench 2 near the other side. The operating computer includes a host, a display screen, a keyboard and a mouse.

[0059] A processing device 8 is installed on the top of the mounting frame 5, and a wire placing box 7 is installed on the front of the mounting frame 5;

[0060] The processing device 8 is used synchronously with the data collector 4 and can process and classify the collected data. The wire-laying box 7 is located between the processing device and the data collector 4 .

[0061] The top and bottom of the wire-releasing box 7 are provided with threading openings 18, and soft wool lines 17 are arranged inside the threading openings 18. A mounting plate 14 is installed on the back of the inner wall of the wire-releasing box 7.

[0062] The soft wool line 17 can prevent dust from entering the interior of the wire-releasing box 7 from the threading port 18 . A threaded hole is provided on the mounting plate 14 , and the mounting plate 14 is located at the middle position of the back side of the inner wall of the wire-releasing box 7 .

[0063] A fixing plate 16 is installed on the back of the inner wall of the wire-releasing box 7 near the top and the bottom, and a plurality of wire buckles 15 are installed on the front of the fixing plate 16. A cover 20 is provided on the front of the wire-releasing box 7, and a sealing plug 19 is installed on the back of the cover 20.

[0064] The wire buckle 15 can limit the line, the line is snapped into the inside of the wire buckle 15, and the sealing plug 19 is snapped into the inside of the wire box 7.

[0065] A data collector 4 is installed on the front of the mounting frame 5, and a connecting line 6 is provided at the bottom of the data collector 4;

[0066] It is also necessary to install wire buckles 15 at the locations where the connecting wires 3 are distributed, so as to avoid the connecting wires 3 being placed in a disorderly manner.

[0067] A control switch 11 is installed on one side of the mounting frame 5 through a mounting base 10, and a control box 13 with a box door 12 is installed on one side of one of the support frames 1;

[0068] A power switch and a controller for controlling the operation of the equipment are installed inside the control box 13 , and a lock is provided on the box door 12 .

[0069] The working principle of the chip test data analysis method provided by the present invention is as follows:

[0070] First, the data acquisition module is used to collect the test data, and then the data is divided into single-table data and multi-table data through the single-table data processing module and the multi-table data processing module. In this process, the judgment module judges the data processed by the single-table data processing module. If it is qualified, a data table is formed and displayed by the single-table data display module. If it is unqualified, it is processed by the failure data processing module, and after the multi-table data processing module completes the processing, it is displayed by the multi-table data display module. After the data is sorted, the prepared test data is imported into the running test software, and the data is judged by the data format judgment. If it effectively raises the upper and lower limits of the IC test items, put it into The container is ready for use. If it is invalid, exit and give the invalid reason. For valid data, select A to only mark the defective data with color, and display the failure data of each test item, and then exit the software. If you select B to determine whether it is multiple data from different batches of the same IC, and multiple data need to determine whether the parameter name and upper and lower limits of each item in the multiple data are consistent, if the result is no, exit and give the invalid reason. If the result is yes and it is judged as a single data, set the mean u, standard deviation 0, maximum value, minimum value, failure number, failure rate, etc. of each test item of IC to finally generate a form with mean u, standard deviation maximum value, minimum value, failure number, failure rate, failure histogram, and 6sigma chart;

[0071] In order to facilitate the regular distribution of lines of the data collector and processing equipment 8 during data transmission and collection, a wire box 7 is installed on the mounting frame 5 on which the data collector 4 is installed, and a plurality of wire buckles 15 are installed inside the wire box 7 through a fixing plate 16. Then, the required equipment is installed on the mounting plate 14, and the lines to be connected are buckled through the wire buckles 15 and then passed through the wire threading port 18, so that the lines can be laid regularly to avoid scattered placement of the lines, which is convenient for later operation by staff.

[0072] Compared with the related art, the chip test data analysis method provided by the present invention has the following beneficial effects:

[0073] In order to improve the efficiency of chip test data analysis, the data acquisition module is first used to collect the test data, and then the data is divided into single-table data and multi-table data through the single-table data processing module and the multi-table data processing module. In this process, the judgment module judges the data processed by the single-table data processing module. If it is qualified, it will be displayed through the single-table data display module. If it is unqualified, it will be processed by the failure data processing module, and after the multi-table data processing module completes the processing, it will be displayed through the multi-table data display module. After the data is sorted, the prepared test data will be imported into the running test software, and the data will be judged by the data format judgment. If it is effective, the upper and lower limits of the IC test items will be raised and put into the container for standby. If Invalid exit, give the invalid reason, and valid data selection A only marks the defective data with color, and displays the failure data of each test item, and then exits the software. If you select B to determine whether it is multiple copies of data from different batches of the same IC, and multiple copies of data need to determine whether the parameter name and upper and lower limits of each copy of the data are consistent, the result is no, exit, give the invalid reason, the result is yes, and judge it as a single copy of data. The mean u, standard deviation 0, maximum value, minimum value, number of failures, failure rate, etc. of each test item of IC are finally generated with the mean u, standard deviation maximum value, minimum value, number of failures, failure rate, failure histogram, and 6sigma chart. This method can quickly and automatically organize and analyze the test data of different test systems. It is convenient and fast, saving time and effort to complete data sorting. Through data sorting and analysis, the differences in chip parameters of different batches can be found, and feedback can be given to the design end to effectively analyze the failure mode, improve the design and increase the manufacturing yield.

[0074] Second embodiment

[0075] Please refer to Figure 8-Figure 9 - Fig.10 , Figure 8 A schematic diagram of the structure of a second embodiment of the chip test data analysis method provided by the present invention; Fig. 9 A schematic diagram of a data testing module is provided for the present invention; Fig.10 The present invention provides a schematic diagram of a data classification module; based on the chip test data analysis method provided in the first embodiment of the present application, the second embodiment of the present application proposes another chip test data analysis method. The second embodiment is only a preferred method of the first embodiment, and the implementation of the second embodiment will not affect the independent implementation of the first embodiment.

[0076] Specifically, the chip test data analysis method provided in the second embodiment of the present application is different in that a chip test data analysis method includes the following steps:

[0077] Step 1: First, sort the data collected by the data acquisition module through the data sorting module, and then classify it through the data classification module to ensure data stability analysis and consistency analysis, and classify it according to data failure ratio and data distribution:

[0078] Step 2: After the classification, the data is stored in the data storage module. When testing is required, the data testing module extracts data from the data storage module. Then the data is judged by the data judgment module. If it is valid, it is displayed in the result display module:

[0079] Step 3: If invalid, it will be marked by the data marking module and then displayed by the result display module. The valid or invalid test data will be stored separately by the data storage module.

[0080] The data classification module includes single data and multiple data, and the data sorting module can calculate the mean u, standard deviation, maximum value, minimum value, number of failures, failure rate, and failure histogram of the data.

[0081] Compared with the related art, the chip test data analysis method provided by the present invention has the following beneficial effects:

[0082] In order to simplify and improve the chip test data analysis method, the data collected by the data acquisition module is sorted by the data sorting module, and then classified by the data classification module to ensure data stability analysis and consistency analysis. At the same time, the data is classified according to the data failure ratio and data distribution. The classified data is stored in the data storage module. When testing is required, the data testing module extracts data from the data storage module, and then the data is judged by the data judgment module. If valid, it is displayed by the result display module. If invalid, it is marked by the data marking module and then displayed by the result display module. The valid or invalid test data will be stored separately by the data storage module for later review. This method simplifies the process and steps of data analysis and improves the efficiency of large-scale chip test data analysis.

[0083] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip test data analysis method, characterized in that: The following steps are involved: Step 1: First, the data acquisition module is used to collect the test data, and then the data is divided into single-table data and multi-table data through the single-table data processing module and the multi-table data processing module. In this process, the judgment module judges the data processed by the single-table data processing module; Step 2: If the data is qualified, a data table is formed and displayed through the single-table data display module. If it is unqualified, it is processed by the failure data processing module. After the multi-table data processing module completes the processing, it is displayed through the multi-table data display module. Step 3: After the data is sorted, import the prepared test data into the running test software, judge the data by data format, if it is valid, raise the upper and lower limits of IC test items, put it into the container for standby, if it is invalid, exit and give the invalid reason; Step 4: If you select A for valid data, only the defective data will be marked with color, and the failure data of each test item will be displayed, and then the software will be exited. If you select B, it will be determined whether it is multiple data from different batches of the same IC. If multiple data are selected, it is necessary to determine whether the parameter name and upper and lower limits of each item in the multiple data are consistent. If the result is no, then exit. If the invalid reason is given and the result is yes, then it will be determined as a single data, and the mean value u, standard deviation 0, maximum value, minimum value, failure number, failure rate, etc. of each test item of the IC will be displayed; Step 5: Generate a table with mean u, standard deviation, maximum value, minimum value, number of failures, failure rate, failure histogram, and 6sigma chart.

2. The chip test data analysis method according to claim 1, characterized in that: The single-table data processing module comprises a user login unit, and an output end of the user login unit is connected to an input end of a failed data highlighting unit.

3. A chip test data analysis method, wherein the data acquisition module is a data collector, characterized in that: It also includes two support frames, the tops of the two support frames are fixedly connected with a test bench, the top of the test bench is installed with an operating computer, and the top of the test bench is installed with a mounting frame.

4. The chip test data analysis method according to claim 3, characterized in that: A processing device is installed on the top of the mounting frame, and a wire placing box is installed on the front of the mounting frame.

5. The chip test data analysis method according to claim 4, characterized in that: The top and the bottom of the wire-releasing box are both provided with threading openings, and soft wool lines are arranged inside the threading openings. A mounting plate is installed on the back of the inner wall of the wire-releasing box.

6. The chip test data analysis method according to claim 4, characterized in that: A fixing plate is installed on the back of the inner wall of the wire release box near the top and the bottom, a plurality of wire buckles are installed on the front of the fixing plate, a cover is provided on the front of the wire release box, and a sealing plug is installed on the back of the cover.

7. The chip test data analysis method according to claim 3, characterized in that: A data collector is installed on the front of the mounting frame, and a connecting line is arranged at the bottom of the data collector.

8. The chip test data analysis method according to claim 3, characterized in that: A control switch is installed on one side of the mounting frame through a mounting base, and a control box with a box door is installed on one side of one of the support frames.

9. A chip test data analysis method, characterized in that: The steps include: Step 1: First, sort the data collected by the data acquisition module through the data sorting module, and then classify it through the data classification module to ensure data stability analysis and consistency analysis, and classify it according to data failure ratio and data distribution: Step 2: After the classification, the data is stored in the data storage module. When testing is required, the data testing module extracts data from the data storage module. Then the data is judged by the data judgment module. If it is valid, it is displayed in the result display module: Step 3: If invalid, it will be marked by the data marking module and then displayed by the result display module. The valid or invalid test data will be stored separately by the data storage module.

10. The chip test data analysis method according to claim 9, characterized in that: The data classification module includes single data and multiple data, and the data sorting module can calculate the mean u, standard deviation, maximum value, minimum value, number of failures, failure rate, and failure histogram of the data.

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