Test method and circuit, electronic equipment and storage medium

Abstract

The invention provides a test method and circuit, an electronic device and a storage medium, the method is applied to a serial test circuit, the serial test circuit comprises a serial communication interface, a test conversion unit and a test unit, and the method comprises the following steps: configuring a target serial communication protocol for the serial communication interface according to a test demand of a to-be-tested chip, the serial communication interface is connected with each chip to be tested by using a second number of interfaces based on the target serial communication protocol; wherein the second number is smaller than the first number; sending a test signal corresponding to the target serial communication protocol to a port to be tested by using the test conversion unit; and testing each to-be-tested port based on the test signal by using the test unit, and determining the quality of the to-be-tested chip. When the to-be-tested chips are tested, the use number of the interfaces is reduced, the number of the to-be-tested chips is increased, and the test efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip detection technology, and more specifically, to a testing method, circuit, electronic device and storage medium. Background Art

[0002] CP (Chip Probing) testing is also called wafer testing, which means testing the wafer before the chip is packaged, so that the problematic chips can be removed before packaging, saving the cost of packaging FT. CP testing is between wafer manufacturing and packaging in the entire chip manufacturing process. After the wafer is made, thousands of bare DIEs (unpackaged chips) are regularly distributed throughout the wafer. Since the chip has not yet been diced and packaged, the pins of the chip are all exposed. These extremely small pins need to be connected to the tester through finer probes.

[0003] The conventional method for wafer testing is SPI (Serial Peripheral Interface), which requires more communication interfaces, limits the number of test chips, and results in low test efficiency. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a testing method, a circuit, an electronic device and a storage medium to overcome the problems in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a test method, which acts on a serial test circuit, wherein the serial test circuit includes a serial communication interface, a test conversion unit, and a test unit, wherein the serial communication interface is connected to the test conversion unit, and the test conversion unit is also connected to the test unit; the serial communication interface is connected to each chip to be tested through a first number of interfaces; the method includes:

[0006] According to the test requirements of the chip under test, a target serial communication protocol is configured for the serial communication interface, and the serial communication interface uses a second number of interfaces to connect to each chip under test based on the target serial communication protocol; wherein the second number is less than the first number;

[0007] Using the test conversion unit to send a test signal corresponding to the target serial communication protocol to the port to be tested;

[0008] The test unit is used to test each of the ports to be tested based on the test signal to determine the quality of the chip to be tested.

[0009] In some technical solutions of the present application, the target serial communication protocol is configured for the serial communication interface according to the test requirements of the chip to be tested, and the serial communication interface uses a second number of interfaces to connect to each chip to be tested based on the target serial communication protocol; wherein the second number is less than the first number, including:

[0010] According to the requirement for the clock in the test requirement, configuring a target clock signal for the serial communication interface;

[0011] According to the data requirements in the test requirements, the target data signal is configured for the serial communication interface; the serial communication interface uses a second number of interfaces to connect to each chip under test based on the target clock signal and the target data signal; wherein the second number is less than the first number.

[0012] In some technical solutions of the present application, the step of configuring a target data signal for the serial communication interface according to the data requirements in the test requirements includes:

[0013] According to the data requirements in the test requirements, register addresses and target data are configured for the serial communication interface.

[0014] In some technical solutions of the present application, the method of using the test conversion unit to send the test signal corresponding to the target serial communication protocol to the port to be tested includes:

[0015] If the test signal corresponding to the target serial communication protocol is a write operation, receiving a register address and target data of the write operation;

[0016] The target data is updated into the register address.

[0017] In some technical solutions of the present application, the method of using the test conversion unit to send the test signal corresponding to the target serial communication protocol to the port to be tested includes:

[0018] If the test signal corresponding to the target serial communication protocol is a read operation, receiving a register address of the read operation;

[0019] The direction of the interface is switched to output, and the data of the register address of the read operation is output serially.

[0020] In some technical solutions of the present application, the above-mentioned using the test unit to test each of the ports to be tested based on the test signal to determine the quality of the chip to be tested includes:

[0021] If the test output result does not meet the preset test standard, the test parameters are adjusted; the test is performed again until the output result meets the preset test standard.

[0022] In some technical solutions of the present application, the above method further includes:

[0023] Generate different test modes corresponding to different test numbers; wherein each of the test modes corresponds to a test parameter;

[0024] If all the test parameters are incorrect, the chip under test is output as a failed chip.

[0025] In a second aspect, an embodiment of the present application provides a test circuit, the test circuit comprising a serial communication interface, a test conversion unit and a test unit, the serial communication interface is connected to the test conversion unit, and the test conversion unit is also connected to the test unit; the serial communication interface is connected to each chip to be tested through a first number of interfaces;

[0026] The serial communication interface is configured with a target serial communication protocol according to the test requirements of the chip under test, and the serial communication interface is connected to each chip under test using a second number of interfaces based on the target serial communication protocol; wherein the second number is less than the first number;

[0027] The test conversion unit is used to send a test signal corresponding to the target serial communication protocol to the port to be tested;

[0028] The testing unit is used to test each of the ports to be tested based on the test signal to determine the quality of the chip to be tested.

[0029] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned test method when executing the computer program.

[0030] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned test method are executed.

[0031] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0032] The present application provides a testing method, which acts on a serial test circuit, wherein the serial test circuit includes a serial communication interface, a test conversion unit and a test unit, wherein the serial communication interface is connected to the test conversion unit, and the test conversion unit is also connected to the test unit; the serial communication interface is connected to each chip to be tested through a first number of interfaces; the method includes configuring a target serial communication protocol for the serial communication interface according to the test requirements of the chip to be tested, wherein the serial communication interface is connected to each chip to be tested using a second number of interfaces based on the target serial communication protocol; wherein the second number is less than the first number; using the test conversion unit to send a test signal corresponding to the target serial communication protocol to a port to be tested; and using the test unit to test each port to be tested based on the test signal to determine the quality of the chip to be tested.

[0033] When testing a chip to be tested, the present application reduces the number of interfaces used, increases the number of chips to be tested, and improves test efficiency.

[0034] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A schematic diagram of a test method provided in an embodiment of the present application is shown;

[0037] Figure 2 A schematic diagram of a target serial communication protocol provided by an embodiment of the present application is shown;

[0038] Figure 3 A schematic diagram showing another target serial communication protocol provided by an embodiment of the present application is shown;

[0039] Figure 4 A schematic diagram of parsing a target serial communication protocol provided by an embodiment of the present application is shown;

[0040] Figure 5 A schematic diagram of a test process provided in an embodiment of the present application;

[0041] Figure 6 A schematic diagram of a test signal waveform provided in an embodiment of the present application;

[0042] Figure 7 A schematic diagram of a test circuit provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0045] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0046] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0047] CP (Chip Probing) testing is also called wafer testing, which means testing the wafer before the chip is packaged, so that the problematic chips can be removed before packaging, saving the cost of packaging FT. CP testing is between wafer manufacturing and packaging in the entire chip manufacturing process. After the wafer is made, thousands of bare DIEs (unpackaged chips) are regularly distributed throughout the wafer. Since the chip has not yet been diced and packaged, the pins of the chip are all exposed. These extremely small pins need to be connected to the tester through finer probes.

[0048] The conventional method for wafer testing is SPI (Serial Peripheral Interface), which requires more communication interfaces, limits the number of test chips, and results in low test efficiency.

[0049] Based on this, the embodiments of the present application provide a testing method, a circuit, an electronic device and a storage medium, which are described below through embodiments.

[0050] Figure 1 A flow chart of a test method provided by an embodiment of the present application is shown, which acts on a serial test circuit, wherein the serial test circuit includes a serial communication interface, a test conversion unit and a test unit, wherein the serial communication interface is connected to the test conversion unit, and the test conversion unit is also connected to the test unit; the serial communication interface is connected to each chip to be tested through a first number of interfaces; wherein the method includes steps S101-S104; specifically:

[0051] S101. According to the test requirements of the chip under test, configure a target serial communication protocol for the serial communication interface, and the serial communication interface uses a second number of interfaces to connect to each chip under test based on the target serial communication protocol; wherein the second number is less than the first number;

[0052] S102, using the test conversion unit to send a test signal corresponding to the target serial communication protocol to the port to be tested;

[0053] S103: Use the test unit to test each of the ports to be tested based on the test signal to determine the quality of the chip to be tested.

[0054] When testing a chip to be tested, the present application reduces the number of interfaces used, increases the number of chips to be tested, and improves test efficiency.

[0055] Some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0056] The present application provides a test method that acts on a serial test circuit. The serial test circuit in the prior art is connected to each chip to be tested through a first number of interfaces. In order to reduce the number of interfaces used, the present application needs to first configure the target serial communication protocol for the serial communication interface. The communication protocol, also known as the communication procedure, refers to an agreement between the communicating parties on data transmission control. The agreement includes unified regulations on issues such as data format, synchronization mode, transmission speed, transmission steps, error detection and correction methods, and control character definitions. Both communicating parties must abide by it. It is also called a link control procedure.

[0057] Based on the target serial communication protocol, the serial test circuit is connected to each chip to be tested through a second number of interfaces, and the second number is less than the first number. In other words, the present application can reduce the number of interfaces connected to the chip to be tested, increase the number of chips to be tested at the same time, and improve the test efficiency.

[0058] The target serial communication protocol includes a target clock signal and a target data signal, that is, the interface configuration process includes configuring the target clock signal for the serial communication interface according to the requirements for the clock in the test requirements; configuring the target data signal for the serial communication interface according to the requirements for the data in the test requirements. The data signal includes a register address and target data. Specifically, the target serial communication protocol is as follows: Figure 2 and Figure 3 As shown, SEL[3:0] is the address of the configuration register, and D[7:0] is the configuration data. The corresponding address is assigned according to the port of the IP actually tested, such as providing the test address A[13:0] for FLASH and the control signal of FLASH IP. The specific allocation is shown in the following table:

[0059] Table 1:

[0060] Signal name IO meaning illustrate FTCLK Input serial clock Input test clock FTDIO Bidirectional IO port Test input / output data pins

[0061] Table 2:

[0062]

[0063] That is, A13 to A0 can be controlled through the above target serial communication protocol, and other FLASH key control signals can also be controlled through the 2 / 3 addresses selected by SEL.

[0064] After the serial communication interface is configured, the test conversion unit is used to send the test signal corresponding to the target serial communication protocol to the port to be tested. That is, the test conversion unit implements the analysis of the target serial communication protocol and implements content read and write access according to the target serial communication protocol. Figure 4As shown, if the test signal corresponding to the target serial communication protocol is a write operation, the register address and target data of the write operation are received; and the target data is updated to the register address. If the test signal corresponding to the target serial communication protocol is a read operation, the register address of the read operation is received; the direction of the interface is switched to output, and the data of the register address of the read operation is output serially. Specifically, when the serial communication interface is working, it is first determined whether the serial communication protocol is a write operation or a read operation. If it is a write operation, the address of the write operation, that is, the information of SEL[3:0] is received. After the reception is completed, the subsequent 8-bit data D7-0 is received; after receiving the data, the data is updated to the register selected by the SEL address; if it is a read operation, the read operation address is received first, and then the direction of the IO is switched to output, and the data of the read address is output serially.

[0065] Afterwards, the test unit is used to test each of the ports to be tested based on the test signal to determine the quality of the chip to be tested. Figure 5 As shown, a test enable signal is generated through the serial port: that is, the TEST_EN signal is 1, and the test item number is generated: according to the actual needs of the installation, the test serial number is generated, such as test serial number 1, 2, 3... and other test serial numbers; then the test signal waveform required by the test item is generated, that is, the signal required for the IP port test. This part of the signal is a signal that changes with time. The specific signal is as follows Figure 6 shown.

[0066] The erase function signal of FLASH needs to be based on the serial port signal to realize the CHIP WEB and other signals of the port, and install the above waveform to generate, where Tws, Tnvs, and Tsce in the figure are time parameters. That is, the time the signal needs to wait and maintain. That is, the interval time required when configuring these signals through the serial port.

[0067] Test process: Perform relevant tests on the test number. If the test output result is inaccurate, adjust the relevant parameters of the IP, and then perform the test again until the test result is OK, and write the adjusted parameters to the calibration address. If the results of traversing all IP parameters are incorrect, the chip is considered to be a failed chip and the chip is discarded.

[0068] Figure 7 A structural schematic diagram of a test circuit provided in an embodiment of the present application is shown, wherein the test circuit comprises a serial communication interface, a test conversion unit and a test unit, wherein the serial communication interface is connected to the test conversion unit, and the test conversion unit is also connected to the test unit; the serial communication interface is connected to each chip to be tested through a first number of interfaces;

[0069] The serial communication interface is configured with a target serial communication protocol according to the test requirements of the chip under test, and the serial communication interface is connected to each chip under test using a second number of interfaces based on the target serial communication protocol; wherein the second number is less than the first number;

[0070] The test conversion unit is used to send a test signal corresponding to the target serial communication protocol to the port to be tested;

[0071] The testing unit is used to test each of the ports to be tested based on the test signal to determine the quality of the chip to be tested.

[0072] The method further comprises: configuring a target serial communication protocol for the serial communication interface according to the test requirements of the chip under test, wherein the serial communication interface uses a second number of interfaces to connect to each chip under test based on the target serial communication protocol; wherein the second number is less than the first number, comprising:

[0073] According to the requirement for the clock in the test requirement, configuring a target clock signal for the serial communication interface;

[0074] According to the data requirements in the test requirements, the target data signal is configured for the serial communication interface; the serial communication interface uses a second number of interfaces to connect to each chip under test based on the target clock signal and the target data signal; wherein the second number is less than the first number.

[0075] The configuring a target data signal for the serial communication interface according to the data requirement in the test requirement includes:

[0076] According to the data requirements in the test requirements, register addresses and target data are configured for the serial communication interface.

[0077] The step of using the test conversion unit to send a test signal corresponding to the target serial communication protocol to the port to be tested includes:

[0078] If the test signal corresponding to the target serial communication protocol is a write operation, receiving a register address and target data of the write operation;

[0079] The target data is updated into the register address.

[0080] The step of using the test conversion unit to send a test signal corresponding to the target serial communication protocol to the port to be tested includes:

[0081] If the test signal corresponding to the target serial communication protocol is a read operation, receiving a register address of the read operation;

[0082] The direction of the interface is switched to output, and the data of the register address of the read operation is output serially.

[0083] The using the test unit to test each of the ports to be tested based on the test signal to determine the quality of the chip to be tested includes:

[0084] If the test output result does not meet the preset test standard, the test parameters are adjusted; the test is performed again until the output result meets the preset test standard.

[0085] Generate different test modes corresponding to different test numbers; wherein each of the test modes corresponds to a test parameter;

[0086] If all the test parameters are incorrect, the chip under test is output as a failed chip.

[0087] like Figure 8 As shown, an embodiment of the present application provides an electronic device for executing the test method in the present application, the device includes a memory, a processor, a bus, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the test method when executing the computer program.

[0088] Specifically, the above-mentioned memory and processor may be general-purpose memory and processor, which are not specifically limited here. When the processor runs the computer program stored in the memory, the above-mentioned test method can be executed.

[0089] Corresponding to the test method in the present application, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned test method are executed.

[0090] Specifically, the storage medium can be a general storage medium, such as a mobile disk, a hard disk, etc. When the computer program on the storage medium is run, the above-mentioned test method can be executed.

[0091] In the embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. The system embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0092] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0093] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0094] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0095] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0096] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A testing method, characterized in that: Acting on a serial test circuit, the serial test circuit includes a serial communication interface, a test conversion unit and a test unit, the serial communication interface is connected to the test conversion unit, and the test conversion unit is also connected to the test unit; The serial communication interface is connected to each chip to be tested through a first number of interfaces; the method comprises: According to the test requirements of the chip under test, a target serial communication protocol is configured for the serial communication interface, and the serial communication interface uses a second number of interfaces to connect to each chip under test based on the target serial communication protocol; wherein the second number is less than the first number; Using the test conversion unit to send a test signal corresponding to the target serial communication protocol to the port to be tested; The test unit is used to test each of the ports to be tested based on the test signal to determine the quality of the chip to be tested.

2. The method according to claim 1, characterized in that The method further comprises: configuring a target serial communication protocol for the serial communication interface according to the test requirements of the chip under test, wherein the serial communication interface uses a second number of interfaces to connect to each chip under test based on the target serial communication protocol; wherein the second number is less than the first number, comprising: According to the requirement for the clock in the test requirement, configuring a target clock signal for the serial communication interface; According to the data requirements in the test requirements, the target data signal is configured for the serial communication interface; the serial communication interface uses a second number of interfaces to connect to each chip under test based on the target clock signal and the target data signal; wherein the second number is less than the first number.

3. The method according to claim 2, characterized in that The configuring a target data signal for the serial communication interface according to the data requirement in the test requirement includes: According to the data requirements in the test requirements, register addresses and target data are configured for the serial communication interface.

4. The method according to claim 3, characterized in that The step of using the test conversion unit to send a test signal corresponding to the target serial communication protocol to the port to be tested includes: If the test signal corresponding to the target serial communication protocol is a write operation, receiving a register address and target data of the write operation; The target data is updated into the register address.

5. The method according to claim 3, characterized in that: The step of using the test conversion unit to send a test signal corresponding to the target serial communication protocol to the port to be tested includes: If the test signal corresponding to the target serial communication protocol is a read operation, receiving a register address of the read operation; The direction of the interface is switched to output, and the data of the register address of the read operation is output serially.

6. The method according to claim 1, characterized in that The using the test unit to test each of the ports to be tested based on the test signal to determine the quality of the chip to be tested includes: If the test output result does not meet the preset test standard, the test parameters are adjusted; the test is performed again until the output result meets the preset test standard.

7. The method according to claim 6, characterized in that The method further comprises: Generate different test modes corresponding to different test numbers; wherein each of the test modes corresponds to a test parameter; If all the test parameters are incorrect, the chip under test is output as a failed chip.

8. A test circuit, characterized in that: The test circuit comprises a serial communication interface, a test conversion unit and a test unit, wherein the serial communication interface is connected to the test conversion unit, and the test conversion unit is also connected to the test unit; the serial communication interface is connected to each chip to be tested through a first number of interfaces; The serial communication interface is configured with a target serial communication protocol according to the test requirements of the chip under test, and the serial communication interface is connected to each chip under test using a second number of interfaces based on the target serial communication protocol; wherein the second number is less than the first number; The test conversion unit is used to send a test signal corresponding to the target serial communication protocol to the port to be tested; The testing unit is used to test each of the ports to be tested based on the test signal to determine the quality of the chip to be tested.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the test method as described in any one of claims 1 to 7 are performed.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the testing method according to any one of claims 1 to 7 are executed.

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