FPGA (Field Programmable Gate Array) parallel password operation method, device and equipment based on simple scheduling, medium and program product

Abstract

The invention provides an FPGA (Field Programmable Gate Array) parallel password operation method, device and equipment based on simple scheduling, a medium and a program product. The method comprises the following steps: receiving and caching a to-be-processed packet; based on protocol unpacking and table lookup, extracting a payload to be processed from the packet to be processed and completing algorithm scheduling and kernel scheduling; according to algorithm scheduling and kernel scheduling results, corresponding algorithms and algorithm kernels in the FPGA are adopted to complete cryptographic operation on the payload to be processed; according to algorithm scheduling and kernel scheduling results, protocol packaging is carried out on the cryptographic operation result; and sending and caching the protocol packaging result. According to the method, the password performance can be quickly improved at low cost under an application layer, the password types are expanded, and meanwhile, the parallel scheduling complexity is reduced.

Description

Technical Field

[0001] The present invention relates to the field of FPGA parallel cryptographic operation technology, and in particular to an FPGA parallel cryptographic operation method, device, equipment, medium and program product based on simple scheduling. Background Art

[0002] In response to the increasing number of individual encryption needs, people try to integrate the cryptographic resources in the network through cloud technology, and provide a wide variety of cryptographic services (hereinafter referred to as "cloud cryptography") to a large number of users in a unified manner, thereby avoiding the need to deploy a full set of (differentiated) cryptographic equipment at each location. The advantage of this approach is that it provides a wide variety of cryptographic services for the application layer, but the disadvantage is that it lacks innovation at the design level (it only repeats the design of "distributed computing" and "cloud computing" in cryptographic operations), and fails to solve the problem of local cryptographic acceleration at the practical level, including the bottlenecks encountered in cryptographic performance in key centers (network layer) below the application layer and trunk nodes (data link layer). The contradiction between cryptographic diversification and high performance still exists below the application layer.

[0003] In order to accelerate cryptography at bottleneck points and bottleneck positions and improve cryptographic computing performance, the current common method is to stack physical devices, including cryptographic machines, cryptographic boards, and even cryptographic chips. Compared with the direct use of a single machine, a single board, and a single chip, the normal use of the stacked cryptographic devices must solve a scheduling (or "deployment" problem). Therefore, in order to give full play to the performance of the stacked devices, people have introduced complex scheduling algorithms to achieve dynamic use and management of stacked devices. However, the stacking method uses the same strategy as "cloud cryptography", that is, by increasing the complexity of management ( / scheduling) to balance the stacking output to improve the overall performance of cryptographic computing. At the same time, the stacking method also faces a limitation, that is, there are many external interfaces (of each device), and unified scheduling is often limited by the interface rate and latency, making it difficult to achieve the ideal effect.

[0004] Some people have thought of the on-chip multi-core approach, similar to the multi-core CPU (i.e. "processor") structure, which not only realizes the stacking of circuits, but also avoids the bottleneck of external interfaces. The multi-core CPU approach has been successful in the computer field, but has not achieved the same results in the field of cryptographic operations, because the CPU is not good at logical operations such as cryptography. Compared with the CPU, the FPGA (i.e. "field programmable gate array") developed from the application-specific integrated circuit (ASIC) has experienced mixed packaging with the CPU in a chip, independent single chip, and multiple algorithm cores in a single chip, showing better and better performance in the field of high-performance cryptographic operations. However, it is easy to instantiate multiple algorithm cores, but it is more complicated to coordinate the balanced parallel operation of the algorithm cores, and there is currently no unified and easy-to-expand method. The high complexity of multi-core scheduling also hinders the motivation of FPGA designers to change a single algorithm core to multiple algorithm cores in the later stage to improve performance. Summary of the invention

[0005] The present invention aims to provide a method, device, equipment, medium and program product for FPGA parallel cryptographic operation based on simple scheduling, aiming at the application scenarios of improving the cryptographic performance below the application layer and expanding the cryptographic types, and the demand for simply implementing FPGA parallel cryptographic operation scheduling, and solves at least one of the following technical problems:

[0006] (1) It is difficult to improve the performance of cryptography below the application layer and to expand the types of cryptography.

[0007] (2) Stacking the same or deploying a full set of cryptographic equipment in various locations is costly and operationally complex.

[0008] (3) In order to improve the performance of cryptographic operations, complex management ( / scheduling) must be introduced after stacking devices to achieve balanced output.

[0009] (4) Due to the limitations of external interface rates and latency limits, it is difficult to fully exploit the cryptographic performance of each stacked device and stacked chip. After switching to a multi-core solution, the CPU-based high-performance cryptographic computing performs poorly, and the FPGA-based solution lacks a scalable and simple scheduling method.

[0010] The present invention provides an FPGA parallel cryptographic operation method based on simple scheduling, comprising:

[0011] Receive and cache packets to be processed;

[0012] Based on protocol unpacking and table lookup, the payload to be processed is extracted from the packet to be processed and algorithm scheduling and core scheduling are completed;

[0013] According to the algorithm scheduling and core scheduling results, the corresponding algorithm and algorithm check in the FPGA are used to complete the cryptographic operation of the payload to be processed;

[0014] According to the algorithm scheduling and core scheduling results, the cryptographic operation results are packaged into protocols;

[0015] The protocol grouping results are cached externally.

[0016] In some embodiments, the protocol-based unpacking and table lookup to extract the payload to be processed from the packet to be processed and complete algorithm scheduling and core scheduling include:

[0017] Protocol unpacking: reading the packet to be processed, parsing the service type from the packet to be processed; finding the protocol corresponding to the service type by querying the service-algorithm mapping table; further unpacking with the corresponding protocol to extract the payload to be processed and the algorithm query result;

[0018] Algorithm scheduling: based on the algorithm query result, sending the payload to be processed to the corresponding algorithm;

[0019] Core scheduling: by querying the busy-idle status table, the payload to be processed is sent to the most idle algorithm core in the algorithm that does not need to be switched; if no algorithm core that does not need to be switched is found, the most idle algorithm core is selected to switch and load according to the algorithm query result.

[0020] In some embodiments, the algorithm query result includes the queried algorithm, mode number and key number.

[0021] In some embodiments, the algorithm core that does not need to be switched refers to the algorithm core whose mode number and key number of the previous packet are completely consistent with those of the current packet.

[0022] In some embodiments, when the cryptographic operation is completed by using the corresponding algorithm in the FPGA and the algorithm to check the payload to be processed:

[0023] For algorithm cores that do not need to be switched or loaded, the cryptographic operation is directly run to obtain the cryptographic operation result;

[0024] When it is necessary to switch, load and update the key in the algorithm core, if the key is retained in the FPGA register, the key is read from the register to the algorithm core first; if the FPGA register does not contain the key, the key is read from the external memory to the algorithm core.

[0025] In some embodiments, the step of performing protocol packaging on the cryptographic operation results according to the algorithm scheduling and core scheduling results includes:

[0026] Core order preservation: record and arrange the cryptographic operation results in the order of core scheduling, so that the next level algorithm can read them in order;

[0027] Algorithm order preservation: record and arrange the cryptographic operation results in the order of algorithm scheduling and send them to the next level protocol package;

[0028] Protocol packaging: complete protocol packaging according to the reverse process of protocol unpacking.

[0029] The present invention also provides an FPGA parallel cryptographic operation device based on simple scheduling, comprising:

[0030] A receiving buffer, used to receive and buffer packets to be processed;

[0031] A transfer module is used to extract the payload to be processed from the packet to be processed based on protocol unpacking and table lookup and complete algorithm scheduling and core scheduling;

[0032] An algorithm module, used to complete cryptographic operations by using corresponding algorithms and algorithm checks in the FPGA to check the payload to be processed according to the algorithm scheduling and core scheduling results;

[0033] A merging module, used to perform protocol grouping on the cryptographic operation results according to the algorithm scheduling and core scheduling results;

[0034] The outbound cache is used to cache the protocol packet grouping results.

[0035] The present invention also provides an electronic device, comprising:

[0036] at least one processor; and a memory communicatively coupled to the at least one processor;

[0037] The memory stores instructions that can be executed by the at least one processor, and the at least one processor executes the above method by executing the instructions stored in the memory.

[0038] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store instructions, and when the instructions are executed, the above method is implemented.

[0039] The present invention also provides a computer program product, which, when called by a computer, enables the computer to execute the above method.

[0040] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0041] 1. By maintaining the lookup table (business-algorithm mapping table and busy-idle status table), it is possible to complete accurate calls of multiple algorithms for different business packages and high-performance parallel cryptographic operations.

[0042] 2. By delivering the scheduling order, the output is ensured to be in the same order as the input, which is suitable for environments with strict requirements on packet sequence.

[0043] 3. By giving priority to the algorithm core whose mode number and key number are consistent with the previous package, the time-consuming switching is avoided. At the same time, the old key is stored in the internal register of the algorithm module, which reduces the time wasted by repeatedly reading the old key from the external memory.

[0044] 4. As the scale of FPGA chips continues to increase in the future, by expanding the busy and idle state table on the old design, it is possible to simply and exponentially instantiate algorithm cores that can be operated in parallel, thereby exponentially improving the cryptographic computing performance.

[0045] 5. As the demand for incremental password types increases in the future, the business-algorithm mapping table can be expanded on the old design, and reprogramming can simply and quickly meet the incremental demand for password types. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 The flowchart of the FPGA parallel cryptographic operation method based on simple scheduling in an embodiment of the present invention.

[0047] Figure 2 It is a schematic diagram of the structure of an FPGA parallel cryptographic operation device based on simple scheduling in an embodiment of the present invention.

[0048] Figure 3 This is a working principle diagram of an FPGA parallel cryptographic operation device based on simple scheduling in an embodiment of the present invention. Figure 3 The processing process includes:

[0049] ① Read the correspondence between the service type and the algorithm from the service-algorithm mapping table, and transfer the payload to be processed to a core scheduling (1~u) according to the correspondence;

[0050] ② Read the busy / idle degree of each algorithm core, as well as the corresponding mode number and key number from the busy / idle status table, and give priority to the algorithm core that does not need to be switched and is the most idle;

[0051] ③Query the core queue status and update the busyness of the algorithm core;

[0052] ④The order of algorithm core scheduling is transmitted;

[0053] ⑤The algorithm checks the mode number and key number of the latest packet in the core queue;

[0054] ⑥ According to the switching flag of the packet payload in the core queue, decide whether to perform the switching and loading operations on the algorithm core next;

[0055] ⑦ The order of transmission algorithm scheduling;

[0056] ⑧Transmission protocol unpacking record.

[0057] Figure 4 Schematic diagram of a service-algorithm mapping table in an embodiment of the present invention.

[0058] Figure 5 Schematic diagram of a busy / idle status table in an embodiment of the present invention.

[0059] Figure 6 It is a schematic diagram of the structure of an FPGA parallel cryptographic operation device based on simple scheduling in a single-port scenario and a multi-port scenario in an embodiment of the present invention. Figure 6 The processing process includes:

[0060] ⑨ Two-level scheduling of input (algorithm scheduling, core scheduling);

[0061] ⑩Two-level order preservation of output (core order preservation and algorithm order preservation).

[0062] Figure 7 It is a structural schematic diagram of a single-port scenario and a multi-port scenario when an FPGA parallel cryptographic operation device based on simple scheduling includes a key management module in an embodiment of the present invention. Figure 7 The processing process includes:

[0063] ⑨ Two-level scheduling of input (algorithm scheduling, core scheduling);

[0064] ⑩Two-level order preservation of output (core order preservation and algorithm order preservation);

[0065] The transfer module (the "protocol unpacking") directly forwards the non-business packets in the receiving buffer to the key management module without processing. After the key management module completes the processing and assembles the response packet, it returns it to the transfer module, and the response is directly sent out through the bypass channel;

[0066] The key management module updates the keys of each channel and each service in the external memory in real time;

[0067] The currently used key will be written back to the key register for subsequent use;

[0068] Key register. Figure 8 The figure is a schematic diagram of the structure of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0070] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] Example

[0072] This embodiment proposes an FPGA parallel cryptographic operation method, device, equipment, medium and program product based on simple scheduling, which can achieve low cost, quickly improve cryptographic performance, expand cryptographic types, and reduce the complexity of parallel scheduling at the application layer.

[0073] like Figure 1 As shown, an FPGA parallel cryptographic operation method based on simple scheduling provided by an embodiment of the present invention includes:

[0074] Receive and cache packets to be processed;

[0075] Based on protocol unpacking and table lookup, the payload to be processed is extracted from the packet to be processed and algorithm scheduling and core scheduling are completed;

[0076] According to the algorithm scheduling and core scheduling results, the corresponding algorithm and algorithm check in the FPGA are used to complete the cryptographic operation of the payload to be processed;

[0077] According to the algorithm scheduling and core scheduling results, the cryptographic operation results are packaged into protocols;

[0078] The protocol grouping results are cached externally.

[0079] Based on the same technical concept, such as Figure 2 As shown, an FPGA parallel cryptographic operation device based on simple scheduling provided by an embodiment of the present invention includes:

[0080] A receiving buffer, used to receive and buffer packets to be processed;

[0081] A transfer module is used to extract the payload to be processed from the packet to be processed based on protocol unpacking and table lookup and complete algorithm scheduling and core scheduling;

[0082] An algorithm module, used to complete cryptographic operations by using corresponding algorithms and algorithm checks in the FPGA to check the payload to be processed according to the algorithm scheduling and core scheduling results;

[0083] A merging module, used to perform protocol grouping on the cryptographic operation results according to the algorithm scheduling and core scheduling results;

[0084] The outbound cache is used to cache the protocol packet grouping results.

[0085] The specific working principles of the functional modules in the above-mentioned device correspond to the steps in the method. For the convenience of description, the technical solution of the present invention is described in detail below based on the specific working principles of the functional modules in the device.

[0086] like Figure 3 As shown, the working principle of an FPGA parallel cryptographic operation device based on simple scheduling is as follows:

[0087] (1) The receiving buffer receives and buffers the packets to be processed, and the buffered packets to be processed can be read by the transfer module in sequence.

[0088] (2) The transfer module extracts the payload to be processed from the packet to be processed based on protocol unpacking and table lookup and completes algorithm scheduling and core scheduling. The transfer module includes three parts: protocol unpacking, algorithm scheduling and core scheduling, which are as follows:

[0089] Protocol unpacking: reading the packet to be processed and parsing the service type from the packet to be processed; Figure 3 Processing process ① in the above method is to find the protocol corresponding to the service type by querying the service-algorithm mapping table; further unpack the package using the corresponding protocol, extract the payload to be processed and pass the algorithm query result to the next level; in some embodiments, the algorithm query result includes the algorithm, mode number and key number. The service-algorithm mapping table is as follows: Figure 4 As shown, it records the mapping relationship between the business number, protocol, algorithm, mode number and key number. The corresponding protocol, algorithm, mode number and key number can be queried according to the business number of the business type.

[0090] Algorithm scheduling: Based on the algorithm query result, the payload to be processed is sent to the corresponding algorithm; wherein, the algorithm scheduling needs to pass the algorithm scheduling order to the algorithm in the merging module in order, such as Figure 3 The processing process in ⑦.

[0091] Core Scheduling: Figure 3 In the processing step ②, by querying the busy-idle status table, the payload to be processed is sent to the algorithm core that does not need to be switched and is the most idle in the algorithm; if no algorithm core that does not need to be switched is found, the most idle algorithm core is selected to switch and load according to the algorithm query result. In some embodiments, the specific processing flow of the core scheduling is as follows:

[0092] The busy / idle status table is as follows: Figure 5 As shown in FIG. 1 , it records the busy and idle programs, mode numbers and key numbers of the algorithm cores. By querying the busy and idle status table, the payload to be processed is passed to the algorithm core that does not need to be switched (the mode number and key number of the previous packet are completely consistent with the current packet) and is the most idle (that is, the core queue is the emptiest), and the busy and idle status table is updated at the same time, as shown in FIG. Figure 3 Processing process ③. Among them, the core scheduling needs to pass the order of core scheduling to the core order preservation in the merging module, such as Figure 3 In the processing process ④. In addition, if no algorithm core that does not need to be switched is found, the most idle algorithm core is selected to switch and load according to the algorithm query result, such as Figure 3 In the processing process ⑥, find the algorithm core with the emptiest core queue among the remaining algorithm cores, and send the payload to be processed containing the switching flag (complete mode switching and key loading during loading processing).

[0093] (3) The algorithm module uses the corresponding algorithm and algorithm core in the FPGA to complete the cryptographic operation of the payload to be processed according to the algorithm scheduling and core scheduling results: the various algorithm cores of the algorithm are independent of each other, but all support switching and loading operations before the operation. For algorithm cores that do not need to be switched or loaded, the cryptographic operation is directly run to obtain the cryptographic operation result; when it is necessary to switch and load the key in the algorithm core, if the key is retained in the register of the FPGA, the key is read from the register to the algorithm core first; if the register of the FPGA does not contain the key, the key is read from the external memory to the algorithm core. In this case, the key is rewritten into the register to cover the position of the earliest rewritten and unused old key.

[0094] (4) The merging module performs protocol grouping on the cryptographic operation results according to the algorithm scheduling and core scheduling results. The merging module includes three parts: core order preservation, algorithm order preservation and protocol grouping, which are as follows:

[0095] Underwriting sequence: Figure 3 In the processing step ④, the cryptographic operation results are recorded and arranged in the order of core scheduling for the next level algorithm to read in order;

[0096] Algorithm order preservation: Figure 3 In the processing process ⑦, the cryptographic operation results are recorded and arranged in the order of algorithm scheduling, and sent to the next level protocol package;

[0097] Protocol package: such as Figure 3 In the processing process ⑧, the protocol package is completed according to the reverse process of protocol unpacking, and the final assembled package will be sent to the outbound cache.

[0098] (5) The outbound cache performs outbound caching on the protocol packet grouping results, stores them, and sequentially provides the external interface with the final grouped packets that have completed the cryptographic operation.

[0099] like Figure 6 As shown, the embodiments of the present invention correspond to two typical application scenarios, namely, one with only one external interface (referred to as "single-port") and one with multiple external interfaces (referred to as "multi-port").

[0100] like Figure 2In the device shown, the algorithm module is usually implemented on the FPGA, while the modules such as the receiving cache, the outgoing cache, the protocol unpacking, and the protocol assembly can be implemented on the FPGA or on the processor. For protocol unpacking and protocol assembly, when the protocol is single, the number of protocols is small, and the protocol processing speed is required to be high, it can be implemented on the FPGA; when there are too many protocols to process, the FPGA space is insufficient, and the protocol processing speed is not required to be high, it can be implemented on the processor, and the processor and the FPGA are connected through a bus.

[0101] (1) The single-port scenario is a scenario where both the input packets to be processed and the output processed packets pass through the same physical interface. The embodiment consists of eight parts: high-speed interface, receiving buffer, protocol depacketization, input two-level scheduling (including algorithm scheduling, core scheduling, such as Figure 6 Processing process in ⑨), algorithm module, output two-level order preservation (including core order preservation and algorithm order preservation, such as Figure 6 Processing process ⑩), protocol group packaging, outbound cache.

[0102] (2) The multi-port scenario is a scenario in which the input packets to be processed and the output processed packets are divided into different physical interfaces. The embodiment consists of sixteen parts: high-speed interface 1, receiving buffer 1, protocol unpacking 1, input two-level scheduling 1, encryption core of algorithm module, output two-level order preservation 1, protocol packet assembly 1, outbound buffer 1, high-speed interface 2, receiving buffer 2, protocol unpacking 2, input two-level scheduling 2, decryption core of algorithm module, output two-level order preservation 2, protocol packet assembly 2, outbound buffer 2.

[0103] like Figure 7 As shown, it is shown that after adding the key management module in the embodiment of the present invention, it corresponds to two typical application scenarios with only one external interface (referred to as "single port") and multiple interfaces (referred to as "multi-ports") respectively. Among them, the key management module can be implemented on both FPGA and processor.

[0104] (1) The implementation scheme of the single-port scenario consists of eleven parts: high-speed interface, receive buffer, protocol unpacking, input two-level scheduling (including algorithm scheduling, core scheduling, such as Figure 7 Processing process in ⑨), algorithm module, output two-level order preservation (including core order preservation and algorithm order preservation, such as Figure 7 Processing process ⑩), protocol group package, outbound cache, key management module, memory, key register.

[0105] (2) The multi-port scenario is a scenario in which the input packets to be processed and the output processed packets are divided into different physical interfaces. The embodiment consists of nineteen parts: a high-speed interface 1, a receiving buffer 1, a protocol unpacking 1, an input two-level scheduling 1, an encryption core of an algorithm module, an output two-level order preservation 1, a protocol packet assembly 1, an outbound buffer 1, a high-speed interface 2, a receiving buffer 2, a protocol unpacking 2, an input two-level scheduling 2, a decryption core of an algorithm module, an output two-level order preservation 2, a protocol packet assembly 2, an outbound buffer 2, a key management module, a memory, and a key register.

[0106] From the above, it can be seen that the beneficial effects of the present invention at least include:

[0107] 1. By maintaining the lookup table (business-algorithm mapping table and busy-idle status table), it is possible to complete accurate calls of multiple algorithms for different business packages and high-performance parallel cryptographic operations.

[0108] 2. By delivering the scheduling order, the output is ensured to be in the same order as the input, which is suitable for environments with strict requirements on packet sequence.

[0109] 3. By giving priority to the algorithm core with the same mode number and key number as the previous package, the time-consuming switching is avoided, and the old key is stored in the internal register of the algorithm module (see Appendix Figure 7 Processing in ), reducing the time wasted by repeatedly reading old keys from external storage.

[0110] 4. As the scale of FPGA chips continues to increase in the future, by expanding the busy and idle state table on the old design, it is possible to simply and exponentially instantiate algorithm cores that can be operated in parallel, thereby exponentially improving the cryptographic computing performance.

[0111] 5. As the demand for incremental password types increases in the future, the business-algorithm mapping table can be expanded on the old design, and reprogramming can simply and quickly meet the incremental demand for password types.

[0112] Based on the same technical concept, the embodiment of the present application also provides an electronic device, which can implement the FPGA parallel cryptographic operation method based on simple scheduling provided in the above embodiment of the present application. In one embodiment, the electronic device can be a server, or a terminal device or other electronic device. Figure 8 As shown, the electronic device may include:

[0113] At least one processor, and a memory connected to the at least one processor. The specific connection medium between the processor and the memory is not limited in the embodiment of the present application. Figure 8 The example in this article is that the processor and memory are connected through a bus. Figure 8The connections between other components are shown in bold lines, which are only for illustration and are not intended to be limiting. The bus can be divided into address bus, data bus, control bus, etc. Figure 8 In the diagram, only one thick line is used, but this does not mean that there is only one bus or only one type of bus. Alternatively, a processor can also be called a controller, and there is no limitation on the name.

[0114] In the embodiment of the present application, the memory stores instructions that can be executed by at least one processor. By executing the instructions stored in the memory, at least one processor can execute the FPGA parallel cryptographic operation method based on simple scheduling discussed above. The processor can implement Figure 8 The functions of each module in the device shown.

[0115] Among them, the processor is the control center of the device, which can use various interfaces and lines to connect the various parts of the entire control device, and monitor the device as a whole by running or executing instructions stored in the memory and calling data stored in the memory, various functions of the device and processing data.

[0116] In an optional design, the processor may include one or more processing units, and the processor may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the modem processor may not be integrated into the processor. In some embodiments, the processor and the memory may be implemented on the same chip, and in some embodiments, they may also be implemented separately on separate chips.

[0117] The processor may be a general-purpose processor, such as a CPU, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, which may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of a FPGA parallel cryptographic operation method based on simple scheduling disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0118] As a non-volatile computer-readable storage medium, the memory can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory can include at least one type of storage medium, for example, it can include flash memory, hard disk, multimedia card, card-type memory, random access memory (Random Access s Memory, RAM), static random access memory (Static Random Access Memory, SRAM), programmable read-only memory (Programmable Read Only Memory, PROM), read-only memory (Read Only Memory, ROM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic storage, disk, optical disk, etc. The memory is any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0119] By designing and programming the processor, the code corresponding to the FPGA parallel cryptographic operation method based on simple scheduling introduced in the above embodiment can be fixed into the chip, so that the chip can perform the steps of the FPGA parallel cryptographic operation method based on simple scheduling in the above embodiment when running. How to design and program the processor is a technology well known to those skilled in the art and will not be described here.

[0120] Based on the same inventive concept, an embodiment of the present application also provides a storage medium, which stores computer instructions. When the computer instructions are executed on a computer, the computer executes an FPGA parallel cryptographic operation method based on simple scheduling discussed above.

[0121] In some optional embodiments, the present application also provides various aspects of an FPGA parallel cryptographic operation method based on simple scheduling, which can also be implemented in the form of a program product, which includes a program code. When the program product is run on an apparatus, the program code is used to enable the control device to execute the steps of an FPGA parallel cryptographic operation method based on simple scheduling according to various exemplary embodiments of the present application described above in this specification.

[0122] It should be noted that, although several units or subunits of the device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of a unit described above can be further divided into multiple units to be embodied. In addition, although the operation of the method of the present application is described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step for execution, and / or one step can be decomposed into multiple steps for execution.

[0123] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0124] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a server, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0125] Program code for performing the operations of the present application may be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0126] Where a remote computing device is involved, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0127] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A FPGA parallel cryptographic operation method based on simple scheduling, characterized in that: include: Receive and cache packets to be processed; Based on protocol unpacking and table lookup, the payload to be processed is extracted from the packet to be processed and algorithm scheduling and core scheduling are completed; According to the algorithm scheduling and core scheduling results, the corresponding algorithm and algorithm check in the FPGA are used to complete the cryptographic operation of the payload to be processed; According to the algorithm scheduling and core scheduling results, the cryptographic operation results are packaged into protocols; The protocol grouping results are cached externally.

2. The FPGA parallel cryptographic operation method based on simple scheduling according to claim 1 is characterized in that: The protocol-based unpacking and table lookup, extracting the payload to be processed from the packet to be processed and completing algorithm scheduling and core scheduling, includes: Protocol unpacking: reading the packet to be processed, parsing the service type from the packet to be processed; finding the protocol corresponding to the service type by querying the service-algorithm mapping table; further unpacking with the corresponding protocol to extract the payload to be processed and the algorithm query result; Algorithm scheduling: based on the algorithm query result, sending the payload to be processed to the corresponding algorithm; Core scheduling: by querying the busy-idle status table, the payload to be processed is sent to the most idle algorithm core in the algorithm that does not need to be switched; if no algorithm core that does not need to be switched is found, the most idle algorithm core is selected to switch and load according to the algorithm query result.

3. The FPGA parallel cryptographic operation method based on simple scheduling according to claim 2 is characterized in that: The algorithm query result includes the queried algorithm, mode number and key number.

4. The FPGA parallel cryptographic operation method based on simple scheduling according to claim 3 is characterized in that: The algorithm core that does not need to be switched refers to the algorithm core whose mode number and key number of the previous package are completely consistent with those of the current package.

5. The FPGA parallel cryptographic operation method based on simple scheduling according to claim 1 is characterized in that: When the cryptographic operation is completed by using the corresponding algorithm in the FPGA and the algorithm to check the payload to be processed: For algorithm cores that do not need to be switched or loaded, the cryptographic operation is directly run to obtain the cryptographic operation result; When it is necessary to switch, load and update the key in the algorithm core, if the key is retained in the FPGA register, the key is read from the register to the algorithm core first; if the FPGA register does not contain the key, the key is read from the external memory to the algorithm core.

6. The FPGA parallel cryptographic operation method based on simple scheduling according to claim 1 is characterized in that: The method of performing protocol packaging on the cryptographic operation results according to the algorithm scheduling and core scheduling results includes: Core order preservation: record and arrange the cryptographic operation results in the order of core scheduling, so that the next level algorithm can read them in order; Algorithm order preservation: record and arrange the cryptographic operation results in the order of algorithm scheduling and send them to the next level protocol package; Protocol packaging: complete protocol packaging according to the reverse process of protocol unpacking.

7. An FPGA parallel cryptographic computing device based on simple scheduling, characterized in that: include: A receiving buffer, used to receive and buffer packets to be processed; A transfer module is used to extract the payload to be processed from the packet to be processed based on protocol unpacking and table lookup and complete algorithm scheduling and core scheduling; An algorithm module, used to complete cryptographic operations by using corresponding algorithms and algorithm checks in the FPGA to check the payload to be processed according to the algorithm scheduling and core scheduling results; A merging module, used to perform protocol grouping on the cryptographic operation results according to the algorithm scheduling and core scheduling results; The outbound cache is used to cache the protocol packet grouping results.

8. An electronic device, characterized in that: include: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the at least one processor executes the method as described in any one of claims 1 to 7 by executing the instructions stored in the memory.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store instructions, and when the instructions are executed, the method according to any one of claims 1 to 7 is implemented.

10. A computer program product, characterized in that When the computer program product is called by a computer, the computer is caused to execute the method according to any one of claims 1 to 7.

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