Timing constraint method, device, equipment and medium

Abstract

The invention discloses a time sequence constraint method, device and equipment and a medium, and the method comprises the steps: obtaining a top-layer time sequence constraint file matched with a to-be-segmented FPGA design drawing, and extracting each clock constraint from the top-layer time sequence constraint file; according to the FPGA segmentation design drawing matched with the to-be-segmented FPGA design drawing, identifying a target clock constraint which acts on the FPGA segmentation boundary and crosses the FPGA after clock segmentation in each clock constraint; and according to the type of each target clock constraint, generating new clock constraints, and adding the new clock constraints into the time sequence constraint file. The clock constraint acting on the cross-FPGA boundary is identified, delay value compensation and new clock generation are carried out on the clock constraint, a time sequence constraint file is regenerated and applied to the segmented FPGAs, accurate transmission of clock signals among different FPGAs is ensured, and the stability and reliability of cross-FPGA design are improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation technology, and in particular to a timing constraint method, device, equipment and medium. Background Art

[0002] During the integrated circuit design process, strict timing checks must be performed at each stage, especially timing analysis at the boundaries of design partitions when dealing with cross-FPGA (field programmable gate array) designs to ensure that the designed circuit can meet the established timing specifications.

[0003] For clock processing located at the partition boundary, existing static timing analysis methods often directly generate clock signals at the clock constraint definition point. This processing method will cause the user-set timing constraint intention to change, or make the constraint unable to function correctly, reducing the stability and reliability of cross-FPGA design. Summary of the invention

[0004] The present invention provides a timing constraint method, apparatus, device and medium to solve the problem that in cross-FPGA design, the stability and reliability of the design are reduced due to inaccurate timing constraints at the partition boundary.

[0005] According to an aspect of an embodiment of the present invention, a timing constraint method is provided, including:

[0006] Obtain a top-level timing constraint file that matches the FPGA design diagram to be segmented, and extract each clock constraint from the top-level timing constraint file;

[0007] According to an FPGA split design diagram that matches the FPGA design diagram to be split, identifying in each clock constraint a target clock constraint that acts on an FPGA split boundary and crosses FPGAs after clock splitting; wherein the FPGA split design diagram includes multiple FPGAs;

[0008] According to the clock type of each target clock constraint, a new clock constraint for cross-FPGA effect is generated, and the new clock constraint is added to the timing constraint file of the affected FPGA.

[0009] According to another aspect of an embodiment of the present invention, a timing constraint device is further provided, comprising:

[0010] A clock constraint extraction module is used to obtain a top-level timing constraint file that matches the FPGA design diagram to be segmented, and extract each clock constraint from the top-level timing constraint file;

[0011] A target clock constraint identification module is used to identify, in each clock constraint, a target clock constraint that acts on the FPGA segmentation boundary and crosses the FPGA after clock segmentation according to an FPGA segmentation design diagram that matches the FPGA design diagram to be segmented;

[0012] The new clock constraint generation module is used to generate new clock constraints for cross-FPGA action according to the clock type of each target clock constraint, and add the new clock constraints to the timing constraint files of the FPGAs acted on.

[0013] According to another aspect of an embodiment of the present invention, an electronic device is provided, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the timing constraint method described in any embodiment of the present invention.

[0017] According to another aspect of an embodiment of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the timing constraint method described in any embodiment of the present invention when executed.

[0018] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in any embodiment of the present invention are implemented.

[0019] The technical solution of the embodiment of the present invention is to obtain the top-level timing constraint file matching the FPGA design drawing to be divided, and extract each clock constraint in the top-level timing constraint file; according to the FPGA division design drawing matching the FPGA design drawing to be divided, identify the target clock constraints acting on the FPGA division boundary and across the FPGA after the clock division in each clock constraint; according to the clock type of each target clock constraint, generate a new clock constraint for acting across the FPGA, and add the new clock constraint to the timing constraint file of the FPGA to be acted on. By identifying the clock constraints acting on the cross-FPGA boundary in the design, and reallocating the clock signal that may be interrupted due to the division, the generated clock in the original design constraint is delayed and a new clock is generated, the timing constraint file is regenerated, and these constraints are applied to the FPGA after the division, to ensure the accurate transmission of the clock signal between different FPGAs, and improve the stability and reliability of the cross-FPGA design.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a flowchart of a timing constraint method provided according to Embodiment 1 of the present invention;

[0023] Figure 2 is a flowchart of another timing constraint method provided according to the second embodiment of the present invention;

[0024] Figure 3 is a constraint segmentation processing flow chart applicable to the embodiment of the present invention;

[0025] Figure 4 is a top-level schematic diagram of a clock splitting model applicable to an embodiment of the present invention;

[0026] Figure 5 is a schematic diagram of a clock division model applicable to an embodiment of the present invention;

[0027] Figure 6 is a schematic diagram of the structure of a timing constraint device provided according to Embodiment 3 of the present invention;

[0028] Figure 7 It is a schematic diagram of the structure of an electronic device for implementing the timing constraint method of an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] Embodiment 1

[0032] Figure 1 This is a flowchart of a timing constraint method provided in the first embodiment of the present invention. This embodiment can be applied to the case where timing constraints are added to the FPGAs to which each clock signal acts according to the clock type of the clock constraint in a cross-FPGA design. The method can be executed by a timing constraint device, which can be implemented in the form of hardware and / or software and can generally be configured in an electronic device. Figure 1 As shown, the method includes:

[0033] S110 , obtaining a top-level timing constraint file that matches the FPGA design drawing to be segmented, and extracting each clock constraint from the top-level timing constraint file.

[0034] In the embodiment of the present invention, the FPGA design diagram to be segmented refers to the original device connection design diagram that has not been segmented. The FPGA corresponding to each device cannot be determined from the FPGA design diagram to be segmented. It contains information such as the logical structure, functional modules, and connection relationships of the entire design. The top-level timing constraint file refers to a file used to define the timing requirements of the design, such as the clock frequency, input and output delays, and timing paths. The clock constraints in the constraint file may include: master clock constraints and generated clock constraints.

[0035] The main clock constraint refers to the external clock signal entering the FPGA. It is the main clock signal in the design used to drive most logic and synchronous operations, ensuring that the propagation and timing requirements of the clock signal in the entire design are met. The constraint statement in the corresponding constraint file can be: create_clock_name<clock_name> -period<clk_period> [get_ports<input_port> ].in,<clock_name> is the name of the clock,<clk_period> is the clock period,<input_port> It is the clock input port, which can also be understood as the clock action position.

[0036] Generated clock constraints are clock signals obtained by a phase-locked loop (PLL), a clock management module (such as a mixed-mode clock manager MMCM or a digital clock manager DCM), or other clock management logic after the master clock has been subjected to logic processing (such as frequency division, frequency multiplication, or phase shift). Generated clock constraints are used to define generated clock constraints when the clock signal has undergone logic processing, such as passing through a register or logic gate, to ensure that the timing analysis tool can correctly analyze the timing characteristics of the clock signal derived from the master clock.

[0037] The constraint statement in the corresponding constraint file can be: create_generated_clock-name<generated_clock_name> -source<source_clock> -divide_by<div_factor><pin_or_port> or create_generated_clock-name<generated_clock_name> -source<source_clock> -multiply_by<mult_factor><pin_or_port> .in,<generated_clock_name> is the name of the generated clock,<source_clock> is the name of the master clock,<div_factor> is the division factor, which is used to define how much the derived clock frequency is a fraction of the source clock frequency. For example, if the source clock frequency is 100MHz and the division factor is 2, the derived clock frequency is 50MHz.<mult_factor> is the multiplication factor, which is used to define how many times the derived clock frequency is the source clock frequency. For example, if the source clock frequency is 100MHz and the multiplication factor is 2, the derived clock frequency is 200MHz.<pin_or_port> Is the output pin or port of a generated clock. Phase shifting is usually not directly specified by the parameters of the create_generated_clock command but can be implemented by specific clock management modules such as PLL or DCM.

[0038] S120. According to the FPGA split design diagram that matches the FPGA design diagram to be split, identify in each clock constraint a target clock constraint that acts on the FPGA split boundary and crosses the FPGA after the clock split; wherein the FPGA split design diagram includes multiple FPGAs.

[0039] In an embodiment of the present invention, an FPGA split design drawing refers to a design drawing containing multiple FPGAs generated after the FPGA design drawing to be split is split, and each FPGA contains specific functions and logic. An FPGA split boundary refers to the split position between different FPGA chips in the FPGA split design drawing. A target clock constraint refers to a timing requirement that needs to be set for the clock signal at the split boundary in a cross-FPGA design, specifically manifested as: a clock constraint that acts on the FPGA split boundary, and the transmission of the clock signal after the clock split spans one or more FPGAs, and the clock transmission may be interrupted due to the split.

[0040] Specifically, extract each clock constraint, such as the master clock constraint and the generated clock constraint, from the top-level timing constraint file that matches the FPGA design diagram to be split. According to the FPGA split design diagram that matches the FPGA design diagram to be split, identify the target clock constraint that acts on the FPGA split boundary and crosses the FPGA after the clock split in each clock constraint. For example, the target clock constraint can be determined by combining the FPGA split design diagram and determining whether the constraint statement of the master clock constraint [get_ports<input_port> ], [get_pins<input_pin> ] or [get_nets<input_net> ] Whether the corresponding active port, pin or network is located and acts on the partition boundary, and the constraint statement of the generated clock constraint<pin_or_port or_net> Whether the corresponding active pin, port or network is located and acts on the partition boundary. A network refers to the signal path formed by the connection between logic units. For example, when the output of one logic gate is connected to the input of another logic gate, a network refers to the connection between logic gates.

[0041] S130 . Generate new clock constraints for acting across FPGAs according to the clock types of the target clock constraints, and add the new clock constraints to the timing constraint files of the affected FPGAs respectively.

[0042] Specifically, according to the clock type of each target clock constraint, including the master clock constraint and the generated clock constraint, a new clock constraint for cross-FPGA action is generated, and the new clock constraint is added to the timing constraint file of the FPGA to be acted on. Among them, in the cross-FPGA design, since the master clock constraint is usually set based on the global default clock constraint, these constraints are automatically applied to each trigger in all clock domains, including the interface between FPGAs, and the master clock constraint focuses more on the timing requirements of the entire system, rather than the delay on a single device or line. Therefore, for the target clock constraint whose clock type is the master clock constraint, the master constraint can be directly used as a new clock constraint for cross-FPGA action. Since the generated clock is usually generated by a clock management unit such as PLL, MMCM or DCM, these units need to accurately consider the delay time on the device and line when adjusting the clock frequency (such as frequency division and frequency multiplication) to ensure that the generated clock signal meets the specific timing requirements. Therefore, for the target clock constraint whose clock type is the generated clock constraint, the original generated clock signal plus the sum of the delays of the generated clock signal from the generation position to the action point through the line transmission between FPGAs can be used as a new clock constraint for cross-FPGA action according to the FPGA segmentation design diagram.

[0043] The technical solution of the embodiment of the present invention is to obtain the top-level timing constraint file matching the FPGA design drawing to be divided, and extract each clock constraint in the top-level timing constraint file; according to the FPGA division design drawing matching the FPGA design drawing to be divided, identify the target clock constraints acting on the FPGA division boundary and across the FPGA after the clock division in each clock constraint; according to the clock type of each target clock constraint, generate a new clock constraint for acting across the FPGA, and add the new clock constraint to the timing constraint file of the FPGA to be acted on. By identifying the clock constraints acting on the cross-FPGA boundary in the design, and reallocating the clock signal that may be interrupted due to the division, the generated clock in the original design constraint is delayed and a new clock is generated, the timing constraint file is regenerated, and these constraints are applied to the FPGA after the division, to ensure the accurate transmission of the clock signal between different FPGAs, and improve the stability and reliability of the cross-FPGA design.

[0044] Optionally, in an embodiment of the present invention, according to an FPGA split design diagram that matches the FPGA design diagram to be split, identifying in each clock constraint a target clock constraint that acts on the FPGA split boundary and crosses the FPGA after the clock split, includes:

[0045] Get the current clock name and the current clock action position in the current clock constraint;

[0046] Obtain a first positioning result of the current clock action position in the FPGA segmentation design diagram, and detect whether the first positioning result is located at the FPGA segmentation boundary;

[0047] If yes, then obtain the second positioning result of the clock source in the FPGA partition design diagram according to the current clock name;

[0048] Acquire a first clock propagation path according to the first positioning result and the second positioning result, and detect whether the first clock propagation path crosses the FPGA;

[0049] If so, the current clock constraint is determined to be the target clock constraint.

[0050] In the embodiment of the present invention, the first positioning result can be specifically understood as: according to the FPGA segmentation design diagram that matches the FPGA design diagram to be segmented, the action position of the current clock in the FPGA segmentation design diagram is used to determine whether the current clock is located at the FPGA segmentation boundary. The second positioning result can be specifically understood as: the position of the clock source of the current clock in the FPGA segmentation design diagram is used to determine the first clock propagation path. The first clock propagation path can be specifically understood as: the propagation path of the current clock from the corresponding clock source to the action point in the FPGA segmentation design diagram, that is, the propagation path from the second positioning result to the first positioning result, which is used to determine whether the first clock propagation path crosses the FPGA.

[0051] Specifically, the current clock name and the current clock action position in the current clock constraint are obtained, the first positioning result of the current clock action position in the FPGA segmentation design diagram is obtained, and it is detected whether the first positioning result is located at the FPGA segmentation boundary. If not, it means that this clock signal is not a timing constraint acting at the FPGA segmentation boundary and no processing is required; if so, the second positioning result of the clock source in the FPGA segmentation design diagram is obtained according to the current clock name, for example, through the constraint statement<clock_name> Determine the current clock name, and determine the second positioning result of the clock source in the FPGA segmentation design diagram, obtain the first clock propagation path according to the first positioning result and the second positioning result, and detect whether the first clock propagation path crosses the FPGA. If not, it means that the clock signal is directly transmitted from the clock source to the action point at the segmentation boundary across the FPGA, rather than transmitted across the FPGA to the action point, and the clock transmission will not be interrupted due to the segmentation, and no processing is required; if yes, it means that the clock signal is transmitted from the clock source to the action point at the segmentation boundary across the FPGA via the cross-FPGA, and the clock transmission may be interrupted due to the segmentation. Therefore, the current clock constraint is determined as the target clock constraint, and the clock is reallocated.

[0052] Optionally, in an embodiment of the present invention, a new clock constraint for acting across FPGAs is generated according to the clock type of each target clock constraint, including:

[0053] If the clock type of the current target clock constraint is the main clock, determine the first action FPGA that matches the current target clock constraint according to the first clock action position in the current target clock constraint, and locate the first clock driving point of the current target clock constraint in the first action FPGA;

[0054] The first clock driving point is used to replace the first clock action position in the current target clock constraint to obtain a new clock constraint whose clock type is the main clock.

[0055] In the embodiment of the present invention, the first clock action position can be specifically understood as: when the clock type of the current target clock constraint is the master clock, the action position of the current target clock constraint in the FPGA partition design diagram, such as a pin, port or network. The first action FPGA can be specifically understood as: an FPGA that matches the first clock action position of the current target clock constraint in the FPGA partition design diagram.

[0056] The first clock driving point can be specifically understood as: the target clock constraint of the current main clock type in the FPGA split design diagram actually acts on the specific pin or port in the first-acting FPGA, rather than the pin or network at the intermediate level. Because the clock signal needs to enter the chip from the external source through the dedicated clock pin or port of the FPGA to drive the internal clock resources. In addition, the static timing analysis tool needs to consider the complete clock path from the clock source to the register, including any possible delays. If the clock signal acts on the pin or network at the intermediate level, then when performing timing constraints, it is impossible to accurately obtain the complete path from the clock source to the driving point, resulting in inaccurate timing analysis results.

[0057] Specifically, if the clock type of the current target clock constraint is the main clock, then according to the constraint statement<pin_or_port_or_net> and the FPGA split design diagram, determine the action position of the current target clock constraint, and the first action FPGA in the FPGA split design diagram that matches it, and locate the first clock driving point of the current target clock constraint, such as a port or pin of the first action FPGA, and use the first clock driving point to replace the first clock action position in the current target clock constraint, and use the clock constraint of the master clock type as the new clock constraint for the cross-FPGA boundary. The main function of the master clock is to provide a common timing reference for each FPGA to ensure time synchronization of the entire system. After splitting the FPGA, each FPGA can have its own master clock pins, which are directly connected to the external clock source, so there is no need to consider the delay value caused by cross-FPGA propagation.

[0058] Furthermore, in an embodiment of the present invention, after extracting each clock constraint in the top-level timing constraint file, the following is further included:

[0059] According to the FPGA split design diagram that matches the FPGA design diagram to be split, identifying, in each clock constraint, independent clock constraints that act on the FPGA split boundary and do not cross the FPGA after the clock split;

[0060] Add each independent clock constraint directly to the timing constraint file of the affected FPGA.

[0061] In the embodiment of the present invention, the independent clock constraint can be specifically understood as: in the FPGA partition design diagram, the clock constraint that acts on the FPGA partition boundary and the clock signal is not transmitted across the FPGA after the partition. Since the clock signal is directly transmitted from the clock source to the action point at the partition boundary across the FPGA, rather than being transmitted across the FPGA to the action point, the clock transmission will not be interrupted due to the partition, and no processing is required.

[0062] Specifically, according to the FPGA split design drawing that matches the FPGA design drawing to be split, the independent clock constraints that act on the FPGA split boundary and do not cross the FPGA after the clock split are identified in each clock constraint. Since the clock transmission will not be interrupted due to the split, no processing is required. Therefore, the FPGA acted by each independent clock constraint is determined according to the FPGA split design drawing, and each independent clock constraint is directly added to the timing constraint file of the acted FPGA as the timing constraint for this FPGA in the cross-FPGA design.

[0063] Embodiment 2

[0064] Figure 2 A flowchart of another timing constraint method provided for Embodiment 2 of the present invention. This embodiment is a refinement of the method for generating a new clock constraint for cross-FPGA action according to the clock type of each target clock constraint in the above embodiment, specifically including: if the clock type of the current target clock constraint is a generated clock, then according to the second clock action position in the current target clock constraint, determine the second action FPGA that matches the current target clock constraint, and locate the second clock driving point of the current target clock constraint in the second action FPGA; according to the second clock driving point and the current target clock constraint, generate a new clock constraint whose clock type is the main clock; according to the positional relationship between the generated clock source and the second clock driving point in the current target clock constraint, calculate the clock delay of the new clock constraint relative to the generated clock source; according to the clock delay, generate a clock delay constraint that matches the new clock constraint.

[0065] Correspondingly, such as Figure 2 As shown, the method includes:

[0066] S210, obtaining a top-level timing constraint file that matches the FPGA design drawing to be segmented, and extracting each clock constraint from the top-level timing constraint file.

[0067] S220 . According to the FPGA partition design diagram that matches the FPGA design diagram to be partitioned, identify, in each clock constraint, a target clock constraint that acts on the FPGA partition boundary and crosses the FPGA after the clock partitioning.

[0068] S230. When the clock type of the current target clock constraint is a generated clock, determine a second action FPGA that matches the current target clock constraint according to the second clock action position in the current target clock constraint, and locate the second clock driving point of the current target clock constraint in the second action FPGA.

[0069] In the embodiment of the present invention, the second clock action position can be specifically understood as: when the clock type of the current target clock constraint is a generated clock, the action position of the current target clock constraint in the FPGA segmentation design diagram, such as a pin, port or network. The second action FPGA can be specifically understood as: an FPGA that matches the second clock action position of the current target clock constraint in the FPGA segmentation design diagram. The second clock driving point can be specifically understood as: the specific pin or port where the target clock constraint of the current generated clock type in the FPGA segmentation design diagram actually acts in the second action FPGA, rather than the intermediate-level pin or network.

[0070] Specifically, extract each clock constraint in the top-level timing constraint file and divide the design diagram and constraint condition statements according to the matching FPGA.<pin_or_port_or_net> Identify the target clock constraints that act on the FPGA split boundary and cross the FPGA after clock splitting. When the clock type of the current target clock constraint is a generated clock, determine the second acting FPGA based on the active pins, ports or networks in the current target clock constraint in the FPGA split design diagram, and then determine the specific pins or ports that the target clock constraint of the current generated clock type actually acts on in the second acting FPGA, that is, the second clock driving point.

[0071] S240 . Generate a new clock constraint whose clock type is a master clock according to the second clock driving point and the current target clock constraint.

[0072] Specifically, since the embodiment of the present invention ensures the accuracy of the timing constraints at the cross-FPGA boundary by adding new timing constraints to each FPGA in the cross-FPGA design, after the FPGA is divided, each FPGA can have its own master clock pins, which are directly connected to the external clock source, so that the new timing constraint type is selected as the master clock type. Therefore, according to the second clock driving point and the current target clock constraint, a new clock constraint with the clock type as the master clock is generated.

[0073] S250 , calculating a clock delay of a new clock constraint relative to the generated clock source according to a positional relationship between the generated clock source and the second clock driving point in the current target clock constraint.

[0074] Specifically, the timing constraint instruction can be used to<source_clock> Combined with the FPGA partitioning design diagram, the clock source of the current target clock constraint is determined. After determining the clock source of the current target clock constraint and the second clock driving point of action, the propagation path of the current target clock constraint from the clock source to the second clock driving point can be determined. Therefore, the FPGA processing units and cross-FPGA propagation physical connections experienced by the clock signal during the propagation process can be determined, and the total clock delay of each unit and each connection can be counted to obtain the clock delay of the new clock constraint relative to the generated clock source.

[0075] S260 . Generate a clock delay constraint that matches the new clock constraint based on the clock delay, and add the new clock constraint and the clock delay constraint to the timing constraint file of the affected FPGA.

[0076] Specifically, the clock delay calculated in S250 is added to the new clock constraint generated in S240 to obtain a clock delay constraint matching the new clock constraint.

[0077] The technical solution of the embodiment of the present invention is to obtain a top-level timing constraint file matching the FPGA design drawing to be divided, and extract each clock constraint in the top-level timing constraint file; according to the FPGA division design drawing matching the FPGA design drawing to be divided, identify the target clock constraint acting on the FPGA division boundary and crossing the FPGA after clock division in each clock constraint; according to the second clock action position in the current target clock constraint, determine the second action FPGA matching the current target clock constraint, and locate the second clock driving point of the current target clock constraint in the second action FPGA; according to the second clock driving point and the current target clock constraint, generate a new clock constraint with the clock type as the main clock; according to the positional relationship between the generated clock source and the second clock driving point in the current target clock constraint, calculate the clock delay of the new clock constraint relative to the generated clock source; according to the clock delay, generate a clock delay constraint matching the new clock constraint. By identifying the clock type acting on the cross-FPGA boundary in the design as the clock constraint of the generated clock, and reallocating the clock signal that may be interrupted due to segmentation, the delay value of the generated clock in the original design constraint is compensated and a new clock is generated, the timing constraint file is regenerated, and these constraints are applied to the segmented FPGA to ensure the accurate transmission of the clock signal between different FPGAs, thereby improving the stability and reliability of the cross-FPGA design.

[0078] Optionally, in an embodiment of the present invention, generating a new clock constraint whose clock type is a master clock according to the second clock driving point and the current target clock constraint includes:

[0079] Get the generated clock source in the current target clock constraint and the period relationship between the generated clock and the generated clock source;

[0080] In the clock constraint matching the generated clock source, the source signal period of the generated clock source is obtained, and according to the period relationship between the generated clock and the generated clock source and the source signal period, the target signal period when the generated clock is used as the master clock is determined;

[0081] A new clock constraint whose clock type is the main clock is generated according to the target signal period and the second clock driving point.

[0082] Specifically, according to the generated clock constraint statement<source_clock> and<div_factor> or<mult_factor> The frequency division or multiplication relationship between the source and period of the generated clock can be determined. For example, when the frequency division factor is 2, the period of the generated clock is twice the period of the source signal. When the frequency multiplication factor is 2, the period of the generated clock is half the period of the source signal.<clk_period> The source signal period of the generated clock source can be determined, and based on the period relationship between the generated clock and the generated clock source, the target signal period when the generated clock is used as the main clock can be determined. Therefore, based on the target signal period and the second clock driving point, a new clock constraint with the clock type as the main clock can be determined. The new clock constraint meets the action point, frequency division or multiplication and delay requirements of the cross-FPGA design, and replaces the generated clock in the original design in the form of the main clock, and directly acts on the corresponding FPGA.

[0083] Optionally, in an embodiment of the present invention, calculating a clock delay of a new clock constraint relative to the generated clock source according to a positional relationship between the generated clock source and the second clock driving point in the current target clock constraint includes:

[0084] In the FPGA split design diagram, a second clock propagation path is obtained with a generated clock source as a starting point and a second clock driving point as an end point;

[0085] The clock delay of the new clock constraint relative to the generated clock source is calculated according to the transmission characteristics of the physical devices and / or transmission lines included in the second clock propagation path.

[0086] Specifically, for a timing constraint whose clock type is a generated clock, according to the<source_clock> , the second clock driving point and the FPGA segmentation design diagram, determine the second clock propagation path starting from the generated clock source and ending at the second clock driving point, calculate the clock delay of the new clock constraint relative to the generated clock source according to the transmission characteristics of the physical devices and / or transmission lines contained in the path, for example, for a specific physical device or transmission line, the delay time is generally a fixed value, and the fixed time delay value of each physical device or transmission line can be determined through technical documents, and each delay value is multiplied by the number of each physical device and each transmission line experienced and summed to calculate the clock delay of the new clock constraint relative to the generated clock source. Among them, the physical devices include: FPGA chip (logic unit and clock management unit inside FPGA, etc.) and the connector between FPGA.

[0087] Specific application scenarios

[0088] In existing integrated circuit design, each different stage requires timing check of the design to ensure that the designed circuit can meet the predetermined timing requirements. For the solution of static timing analysis across FPGAs, general static timing analysis software does not consider the increase in the delay of the clock signal transmission path, but directly generates the clock at the clock constraint definition point. Such a design does not pay attention to the delay value of the clock transmitted from the port in the top-level design. When the user design is divided into multiple FPGAs, the constraint action point changes, which will cause the constraint intention output by the user to change, or the constraint does not work. In order to solve the problem that the clock constraints and generated clock constraints are located at the division boundary after division in the cross-FPGA design, resulting in inaccurate clock information, an embodiment of the present invention proposes a timing constraint method to realize that the clock constraints can be combined with the netlist, accurately generate clock delay values ​​and act on the target FPGA. Figure 3 is a constraint segmentation processing flow chart applicable to an embodiment of the present invention. The timing constraint method may specifically be:

[0089] 1. Read the clock constraints entered by the user

[0090] User-entered constraints apply to the unpartitioned FPGA design and are in the top-level timing constraint file with the top level as the constraint application level.

[0091] 2. Categorize and store each clock constraint

[0092] Analyze each clock constraint and apply it line by line. Categorize and store them according to the order and clock constraint type. The clock constraint types include primary clock and generated clock. The corresponding clock constraint statements are create_clock and create_generated_clock.

[0093] 3. Master clock constraints and generated clocks are located after division

[0094] After the design is split into different FPGAs, check whether each clock constraint acts at the boundary. Determine the clock action position and the specific action point in the split FPGA. The clock must act on a specific pin or port in the split FPGA, not a middle-level pin or a logic network. When the clock action position is in the logic network, it is necessary to find the corresponding driving point of the network.

[0095] 4. Calculate the delay value after the generated clock constraint is divided

[0096] Calculate the delay value of the generated clock constraint after segmentation. The generated clock constraint is located at the boundary. After segmentation, it will cross the FPGA. The generated clock constraint cannot pass through the time division multiplexing module or be transmitted across the board, so a new clock needs to be created and the corresponding delay value needs to be calculated.

[0097] 5. Generate clock constraints, mark the delay value, change it to the main clock, and modify its dependencies (the clock does not pass through the time division multiplexing module)

[0098] For the generated clock constraints acting at the split boundary, modify the generated clock to be the main clock, calculate and add the clock delay through the propagation path from the clock source to the specific driving point, update the clock period according to the timing constraint statement, and apply the new clock constraint to the specific driving point.

[0099] 6. After calculating the delay value and dependency, generate the sdc (Synopsys design constraints, static design constraint) file corresponding to the segmented FPGA, which can also be called a timing constraint file.

[0100] In a specific example, for a cross-FPGA design, the specific execution process of the timing constraint method can be:

[0101] 1. Read the clock constraints entered by the user in the timing constraint file entered by the user.

[0102] 2. Categorize and store constraints in order to ensure that the constraints are executed in the order input by the user.

[0103] 3. Process the main clock constraint to determine whether the clock created by create_clock is on the boundary. Figure 4 This is a top-level schematic diagram of a clock splitting model applicable to an embodiment of the present invention. The input clock constraint is create_clock-period10-name clk[get_ports clk]. A main clock clk with a period of 10ns is generated. Then, the clock constraint create_clock-name edge_clk-period 20[get_nets r2] is input. The constraint acts on the splitting boundary net r2.

[0104] 4. Determine whether the constraint acts on the boundary. Figure 5 This is a schematic diagram of a clock division model applicable to an embodiment of the present invention. The clock edge_clk acts between F1 and F2. After the clock is divided, it needs to act on F2, so the clock driving point F2 / P_r2 is found. Then, it is determined whether the clock crosses the FPGA after division. The clock signal acts at F2 / P_r2, and a new clock needs to be generated across the FPGA.

[0105] 5. Generate the main clock constraint create_clock-name edge_clk-period 20[get_ports P_r2].

[0106] 6. Process the generated clock constraint and obtain the generated clock generated by the create_generated_clock constraint in the constraint file. There is a corresponding relationship between the generated clock and the main clock. The input main clock constraint is create_clock-period 10-name clk[get_ports clk], and the main clock clk is generated. The input generated clock constraint is create_generated_clock-name gen-source[get_ports clk]-divide_by 2[get_nets net_r2]. After division, it is necessary to determine the specific action point of the generated clock on FPGA2. Then search forward for the driving point and determine it to be at F2 / P_r2. Then determine the transmission path of the generated clock constraint, and accumulate delays according to the path to calculate the clock delay. The clock is created from port clk and passed to F2 / P_r2 through the clock physical line. According to the description of the physical device characteristics, the accumulated delay of the network net, buffer buf, and the connection between the FPGA is about 5.4ns. Since the generated clock acts on a separate FPGA after segmentation, there is no dependency. The generated clock is modified to the main clock type, that is, a new clock constraint of the form: create_clock-period20[get_ports P_r2] is generated, and a delay of 5.4ns is added, that is, a clock delay constraint of the form: set_clock_latency-source 5.4[get_ports P_r2] is generated.

[0107] 7. The generated timing constraints are written into the corresponding timing constraint files.

[0108] Specifically, after generating a new clock constraint, or a combination of a new clock constraint and a clock delay constraint, the above content is added to the timing constraint file of the affected FPGA for subsequent stable and reliable cross-FPGA design simulation.

[0109] This patent processes the clock constraints at the FPGA split boundary, re-assigns the clocks that may be interrupted due to the split, and compensates the delay value of the generated clock in the original design constraints and generates a new clock, and regenerates the timing constraint file to act on the corresponding FPGA after the split. By identifying the clock constraints acting on the cross-FPGA boundary in the design, and re-assigning the clock signals that may be interrupted due to the split, the delay value compensation and new clock generation of the generated clock in the original design constraints, regenerates the timing constraint file, and applies these constraints to the split FPGA, it ensures the accurate transmission of clock signals between different FPGAs, and improves the stability and reliability of the cross-FPGA design.

[0110] Embodiment 3

[0111] Figure 6 This is a schematic diagram of the structure of a timing constraint device provided in Embodiment 3 of the present invention. Figure 6 As shown, the apparatus includes: a clock constraint extraction module 610 , a target clock constraint identification module 620 and a new clock constraint generation module 630 .

[0112] The clock constraint extraction module 610 is used to obtain a top-level timing constraint file that matches the FPGA design diagram to be segmented, and extract each clock constraint from the top-level timing constraint file;

[0113] The target clock constraint identification module 620 is used to identify the target clock constraints acting on the FPGA segmentation boundary and across the FPGA after the clock segmentation in each clock constraint according to the FPGA segmentation design diagram matching the FPGA design diagram to be segmented;

[0114] The new clock constraint generation module 630 is used to generate new clock constraints for cross-FPGA effects according to the clock types of each target clock constraint, and add the new clock constraints to the timing constraint files of the affected FPGAs respectively.

[0115] The technical solution of the embodiment of the present invention is to obtain the top-level timing constraint file matching the FPGA design drawing to be divided, and extract each clock constraint in the top-level timing constraint file; according to the FPGA division design drawing matching the FPGA design drawing to be divided, identify the target clock constraints acting on the FPGA division boundary and across the FPGA after the clock division in each clock constraint; according to the clock type of each target clock constraint, generate a new clock constraint for acting across the FPGA, and add the new clock constraint to the timing constraint file of the FPGA to be acted on. By identifying the clock constraints acting on the cross-FPGA boundary in the design, and reallocating the clock signal that may be interrupted due to the division, the generated clock in the original design constraint is delayed and a new clock is generated, the timing constraint file is regenerated, and these constraints are applied to the FPGA after the division, to ensure the accurate transmission of the clock signal between different FPGAs, and improve the stability and reliability of the cross-FPGA design.

[0116] Based on the above embodiments, the target clock constraint identification module 620 is specifically used to:

[0117] Get the current clock name and the current clock action position in the current clock constraint;

[0118] Obtain a first positioning result of the current clock action position in the FPGA segmentation design diagram, and detect whether the first positioning result is located at the FPGA segmentation boundary;

[0119] If yes, then obtain the second positioning result of the clock source in the FPGA partition design diagram according to the current clock name;

[0120] Acquire a first clock propagation path according to the first positioning result and the second positioning result, and detect whether the first clock propagation path crosses the FPGA;

[0121] If so, the current clock constraint is determined to be the target clock constraint.

[0122] Based on the above embodiments, the new clock constraint generation module 630 is specifically used for:

[0123] If the clock type of the current target clock constraint is the main clock, determine the first action FPGA that matches the current target clock constraint according to the first clock action position in the current target clock constraint, and locate the first clock driving point of the current target clock constraint in the first action FPGA;

[0124] The first clock driving point is used to replace the first clock action position in the current target clock constraint to obtain a new clock constraint whose clock type is the main clock.

[0125] Further, based on the above embodiments, the new clock constraint generating module 630 may also be specifically used for:

[0126] If the clock type of the current target clock constraint is a generated clock, a second action FPGA matching the current target clock constraint is determined according to the second clock action position in the current target clock constraint, and a second clock driving point of the current target clock constraint is located in the second action FPGA;

[0127] Generate a new clock constraint whose clock type is the main clock according to the second clock driving point and the current target clock constraint;

[0128] Calculate the clock delay of the new clock constraint relative to the generated clock source according to the positional relationship between the generated clock source and the second clock driving point in the current target clock constraint;

[0129] Based on the clock delay, a clock delay constraint is generated that matches the new clock constraint.

[0130] Optionally, based on the above embodiments, the new clock constraint generating module 630 includes: a period relationship acquiring unit, a target signal period determining unit and a new clock constraint generating unit.

[0131] A period relationship acquisition unit, used for acquiring a generated clock source in a current target clock constraint and a period relationship between the generated clock and the generated clock source;

[0132] A target signal period determination unit, used to obtain a source signal period of a generated clock source in a clock constraint matching the generated clock source, and determine a target signal period when the generated clock is used as a master clock according to a period relationship between the generated clock and the generated clock source and the source signal period;

[0133] The new clock constraint generating unit is used to generate a new clock constraint whose clock type is the main clock according to the target signal cycle and the second clock driving point.

[0134] Optionally, based on the above embodiments, the new clock constraint generation module 630 includes: a second clock propagation path acquisition unit and a clock delay calculation unit.

[0135] A second clock propagation path acquisition unit is used to acquire a second clock propagation path starting from a generated clock source and ending at a second clock driving point in the FPGA segmentation design diagram;

[0136] The clock delay calculation unit is used to calculate the clock delay of the new clock constraint relative to the generated clock source according to the transmission characteristics of the physical devices and / or transmission lines included in the second clock propagation path.

[0137] Furthermore, based on the above embodiments, the timing constraint device may further include: an independent clock constraint identification module and a timing constraint file update module.

[0138] An independent clock constraint identification module is used to identify, in each clock constraint, independent clock constraints acting on the FPGA partition boundary and not crossing the FPGA after clock partitioning according to the FPGA partitioning design diagram matching the FPGA design diagram to be partitioned;

[0139] The timing constraint file update module is used to directly add each independent clock constraint to the timing constraint file of the affected FPGA.

[0140] The timing constraint device provided in the embodiment of the present invention can execute the timing constraint method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0141] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0142] Embodiment 4

[0143] Figure 7 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0144] like Figure 7As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0145] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0146] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 11 executes the various methods and processes described above, such as executing a timing constraint method, that is:

[0147] Obtain a top-level timing constraint file that matches the FPGA design diagram to be segmented, and extract each clock constraint from the top-level timing constraint file;

[0148] According to an FPGA split design diagram that matches the FPGA design diagram to be split, identifying in each clock constraint a target clock constraint that acts on an FPGA split boundary and crosses FPGAs after clock splitting; wherein the FPGA split design diagram includes multiple FPGAs;

[0149] According to the clock type of each target clock constraint, a new clock constraint for cross-FPGA effect is generated, and the new clock constraint is added to the timing constraint file of the affected FPGA.

[0150] In some embodiments, the timing constraint method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of a timing constraint method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute a timing constraint method in any other appropriate manner (e.g., by means of firmware).

[0151] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0152] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0153] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0154] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0155] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0156] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0157] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0158] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A timing constraint method, characterized in that: include: Obtain a top-level timing constraint file that matches the FPGA design diagram to be segmented, and extract each clock constraint from the top-level timing constraint file; According to an FPGA split design diagram that matches the FPGA design diagram to be split, identifying in each clock constraint a target clock constraint that acts on an FPGA split boundary and crosses FPGAs after clock splitting; wherein the FPGA split design diagram includes multiple FPGAs; According to the clock type of each target clock constraint, a new clock constraint for cross-FPGA effect is generated, and the new clock constraint is added to the timing constraint file of the affected FPGA.

2. The method according to claim 1, characterized in that: According to the FPGA split design diagram that matches the FPGA design diagram to be split, identify the target clock constraints that act on the FPGA split boundary and cross the FPGA after the clock split in each clock constraint, including: Get the current clock name and the current clock action position in the current clock constraint; Obtain a first positioning result of the current clock action position in the FPGA segmentation design diagram, and detect whether the first positioning result is located at the FPGA segmentation boundary; If yes, then obtain the second positioning result of the clock source in the FPGA partition design diagram according to the current clock name; Acquire a first clock propagation path according to the first positioning result and the second positioning result, and detect whether the first clock propagation path crosses the FPGA; If so, the current clock constraint is determined to be the target clock constraint.

3. The method according to claim 1, characterized in that Generate new clock constraints for cross-FPGA effects based on the clock type of each target clock constraint, including: If the clock type of the current target clock constraint is the main clock, determine the first action FPGA that matches the current target clock constraint according to the first clock action position in the current target clock constraint, and locate the first clock driving point of the current target clock constraint in the first action FPGA; The first clock driving point is used to replace the first clock action position in the current target clock constraint to obtain a new clock constraint whose clock type is the main clock.

4. The method according to claim 1, characterized in that Generate new clock constraints for cross-FPGA effects based on the clock type of each target clock constraint, including: If the clock type of the current target clock constraint is a generated clock, a second action FPGA matching the current target clock constraint is determined according to the second clock action position in the current target clock constraint, and a second clock driving point of the current target clock constraint is located in the second action FPGA; Generate a new clock constraint whose clock type is the main clock according to the second clock driving point and the current target clock constraint; Calculate the clock delay of the new clock constraint relative to the generated clock source according to the positional relationship between the generated clock source and the second clock driving point in the current target clock constraint; Based on the clock delay, a clock delay constraint is generated that matches the new clock constraint.

5. The method according to claim 4, characterized in that Generate a new clock constraint whose clock type is the main clock based on the second clock driving point and the current target clock constraint, including: Get the generated clock source in the current target clock constraint and the period relationship between the generated clock and the generated clock source; In the clock constraint matching the generated clock source, the source signal period of the generated clock source is obtained, and according to the period relationship between the generated clock and the generated clock source and the source signal period, the target signal period when the generated clock is used as the master clock is determined; A new clock constraint whose clock type is the main clock is generated according to the target signal period and the second clock driving point.

6. The method according to claim 4, characterized in that According to the positional relationship between the generated clock source and the second clock driving point in the current target clock constraint, the clock delay of the new clock constraint relative to the generated clock source is calculated, including: In the FPGA split design diagram, a second clock propagation path is obtained with a generated clock source as a starting point and a second clock driving point as an end point; The clock delay of the new clock constraint relative to the generated clock source is calculated according to the transmission characteristics of the physical devices and / or transmission lines included in the second clock propagation path.

7. The method according to any one of claims 1 to 6, characterized in that: After extracting each clock constraint in the top-level timing constraint file, it also includes: According to the FPGA split design diagram that matches the FPGA design diagram to be split, identifying, in each clock constraint, independent clock constraints that act on the FPGA split boundary and do not cross the FPGA after the clock split; Add each independent clock constraint directly to the timing constraint file of the affected FPGA.

8. A timing constraint device, characterized in that: include: A clock constraint extraction module is used to obtain a top-level timing constraint file that matches the FPGA design diagram to be segmented, and extract each clock constraint from the top-level timing constraint file; A target clock constraint identification module is used to identify, in each clock constraint, a target clock constraint that acts on the FPGA segmentation boundary and crosses the FPGA after clock segmentation according to the FPGA segmentation design diagram that matches the FPGA design diagram to be segmented; The new clock constraint generation module is used to generate new clock constraints for cross-FPGA effects according to the clock types of each target clock constraint, and add the new clock constraints to the timing constraint files of the affected FPGAs respectively.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the timing constraint method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the timing constraint method according to any one of claims 1 to 7 when executed.

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