Digital path identification sensitization method in digital-analog hybrid circuit

Abstract

The invention discloses a method for identifying and sensitizing a digital path in a digital-analog hybrid circuit, which comprises the following steps of: firstly, establishing a directed dependency graph of the digital-analog hybrid circuit, dividing all power supplies in the circuit into digital power supplies and analog power supplies, and enabling the voltage values of the digital power supplies to be high or low and the voltage values of the analog power supplies to be default values to obtain value modes of all the power supplies; and performing digital path identification sensitization based on breadth-first search in each power supply value mode to obtain an identification sensitization result, and only considering circuit elements with digital characteristics in the process until node voltage high-low state updating and MOS tube state judgment on all digital paths are completed. Based on the breadth-first search strategy, the transistor-level digital path in the digital-analog hybrid circuit is identified and sensitized in a targeted manner, so that an accurate digital path identification and sensitization result is obtained.

Description

Technical Field

[0001] The invention belongs to the technical field of digital-analog hybrid circuits, and more specifically, relates to a digital path identification sensitization method in a digital-analog hybrid circuit. Background Art

[0002] With the continuous advancement of integrated circuit technology, mixed-analog circuits have attracted more and more attention due to their wide applications in signal processing, communication systems and other fields. This type of circuit integrates two major parts, analog and digital, and can process continuously changing analog signals and discrete digital signals at the same time. However, there are many challenges in the design and analysis of mixed-analog circuits. In particular, it is particularly important to accurately model and quickly simulate circuits at the transistor level, because this is directly related to the effectiveness of circuit performance optimization and fault diagnosis.

[0003] At present, the research on mixed-analog circuits in the industry is mainly focused on high-level abstraction levels, such as the behavioral level or register transfer level (RTL), while relatively little research is done on the underlying transistor level. This situation leads to several key problems: first, it is difficult to accurately evaluate the behavioral characteristics of MOS tubes in different operating modes; second, the traditional automatic test pattern generation (ATPG) method cannot adapt well to the needs of the transistor level; finally, there is a lack of effective means to identify and sensitize digital paths, which limits the possibility of circuit optimization. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method for identifying and sensitizing digital paths in a mixed digital-analog circuit. Based on a breadth-first search strategy, the method specifically identifies and sensitizes transistor-level digital paths in the mixed digital-analog circuit, thereby obtaining accurate digital path identification and sensitization results.

[0005] In order to achieve the above-mentioned object of the invention, the digital path identification sensitization method in the digital-analog hybrid circuit of the present invention comprises the following steps:

[0006] S1: Modeling the digital-analog mixed circuit with a directed dependency graph according to the SPICE netlist of the digital-analog mixed circuit to obtain a directed dependency graph, and extracting a start point and end point dictionary of the voltage node according to the directed dependency graph;

[0007] S2: Divide all power supplies in the digital-analog hybrid circuit into digital power supplies and analog power supplies, and record the number of digital power supplies as K;

[0008] S3: Set the voltage value of the digital power supply to high or low, and the voltage value of the analog power supply to the default value in the SPICE netlist, and obtain M power supply value modes, where M = 2 K ;

[0009] S4: Perform digital path identification sensitization based on breadth-first search in each power supply value mode to obtain identification sensitization results. The specific method is:

[0010] S4.1: Initialize access set Voltage Node Queue Path Queue Then, K digital power supplies are added to the access set A and the voltage node queue B, and then K paths are added to the path queue C, where the starting voltage node of the kth path is the kth digital power supply, k = 1, 2, ..., K;

[0011] S4.2: Take out voltage node i from voltage node queue B and delete it from voltage node queue B, and then obtain neighbor voltage node set N(i) of voltage node i according to the directed dependency graph;

[0012] S4.3: Take out the neighbor voltage node j from the neighbor voltage node set N(i) and delete it from the neighbor voltage node set N(i);

[0013] S4.4: Determine whether the neighbor voltage node j∈A, that is, whether the neighbor voltage node j has been visited. If yes, proceed to step S4.10, otherwise proceed to step S4.5;

[0014] S4.5: Determine whether the neighbor voltage node j corresponds to a MOS gate, if yes, proceed to step S4.6, otherwise proceed to step S4.8;

[0015] S4.6: If the voltage node i is at a high level and the neighboring voltage node j corresponds to the NMOS gate, or the voltage node i is at a low level and the neighboring voltage node j corresponds to the PMOS gate, the MOS gate state is determined to be on, otherwise the MOS gate state is determined to be off;

[0016] S4.7: Determine whether the MOS gate state is on, if yes, go to step S4.8, otherwise go to step S4.10;

[0017] S4.8: Add the neighbor voltage node j to the access set A and the voltage node queue B, and add the neighbor voltage node j to the path queue C behind the path where the voltage node i is located;

[0018] S4.9: traverse the start-end dictionary of the directed dependency graph, if the voltage node i is not the start point and the neighbor voltage node j is the end point, update the voltage of the neighbor voltage node j to the voltage of the corresponding path start point, that is, if the start point is a high voltage, set the neighbor voltage node j to a high voltage, if the start point is a low voltage, set the neighbor voltage node j to a low voltage; if it is other cases, update the voltage of the neighbor voltage node j to the voltage of the voltage node i;

[0019] S4.10: Determine whether the neighbor node set N(i) is empty. If so, proceed to step S4.11, otherwise return to step S4.3;

[0020] S4.11: Determine whether the voltage node queue B is empty. If so, identification sensitization is completed and the process goes to step S4.12. Otherwise, the process returns to step S4.2.

[0021] S4.12: Output the voltage state of each voltage node or the gate state of the MOS tube corresponding to the voltage node to obtain the identification sensitization result.

[0022] The digital path identification and sensitization method in the digital-analog hybrid circuit of the present invention first establishes a directed dependency graph of the digital-analog hybrid circuit, divides all power supplies in the circuit into digital power supplies and analog power supplies, sets the voltage value of the digital power supply to be high or low, and sets the voltage value of the analog power supply to be a default value, obtains all power supply value modes, and performs digital path identification and sensitization based on breadth-first search in each power supply value mode to obtain identification and sensitization results. In this process, only circuit elements with digital characteristics are considered until the node voltage high and low status update and MOS tube status judgment on all digital paths are completed.

[0023] The present invention has the following beneficial effects:

[0024] 1) The present invention can analyze the controlled state of the gate of each MOS tube in the circuit, and accurately determine the voltage distribution of the nodes on the entire digital path based on this, effectively overcoming the limitations of the traditional path sensitization algorithm in the application of digital-analog hybrid circuits and transistor levels;

[0025] 2) The present invention does not require the use of a circuit simulator for simulation, thereby saving time, opening up a new way to deeply understand the working mechanism of mixed analog and digital circuits, improving the understanding of complex circuit structures, and providing strong support for subsequent circuit optimization. It provides a potential exploration method for the design and testability analysis of mixed analog and digital circuits. Potential application scenarios include but are not limited to the testability analysis and design of high-performance mixed analog and digital integrated circuits and the debugging of internal circuits of precision measuring instruments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flowchart of a specific implementation method of the method for identifying and sensitizing a digital path in a mixed digital-analog circuit of the present invention;

[0027] Figure 2 is an example diagram of directed dependency graph modeling in this embodiment;

[0028] Figure 3 It is a flow chart of a digital path identification sensitization method based on breadth-first search in the present invention;

[0029] Figure 4 In this embodiment Figure 2 The signal flow example diagram shown;

[0030] Figure 5 is a bandgap circuit diagram in this embodiment. DETAILED DESCRIPTION

[0031] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0032] Example

[0033] Figure 1 FIG. 1 is a flow chart of a specific implementation method of the method for identifying and sensitizing a digital path in a mixed analog-digital circuit of the present invention. Figure 1 As shown, the specific steps of the digital path identification sensitization method in the digital-analog hybrid circuit of the present invention include:

[0034] S101: Directed Dependency Graph Modeling:

[0035] A directed dependency graph is modeled for the mixed digital-analog circuit according to the SPICE netlist of the mixed digital-analog circuit to obtain a directed dependency graph, and a start point and end point dictionary of voltage nodes is extracted according to the directed dependency graph.

[0036] Figure 2 is an example diagram of directed dependency graph modeling in this embodiment. Figure 2 As shown, Figure 2 Taking the dual inverter in (a) as an example to model the directed dependency graph, we can get Figure 2 (b) shows the directed dependency graph, which effectively reflects the excitation relationship of the components in the circuit.

[0037] S102: Determine the power source type:

[0038] All power supplies in the mixed digital-analog circuit are divided into digital power supplies and analog power supplies, and the number of digital power supplies is denoted as K.

[0039] The division of digital power supply and analog power supply can be realized according to the marking of circuit designers. In this embodiment, a power supply classification method is also provided, and the specific method is: traverse each power supply in the digital-analog hybrid circuit in the directed dependency graph, remove the protection resistor of the power supply in the directed dependency graph, and then check whether the power supply is directly connected to the MOS tube gate. If so, it is determined to be a digital power supply, otherwise it is determined to be an analog power supply. Figure 2 Taking the directed dependency graph shown as an example, it can be seen that power supply S3 is a digital power supply, while power supplies S1 and S2 are analog power supplies.

[0040] S103: Generate different power value modes:

[0041] Let the voltage value of the digital power supply be high or low, and the voltage value of the analog power supply be the default value in the SPICE netlist, and obtain M power supply value patterns, where M = 2 K .by Figure 2 Taking the directed dependency graph shown as an example, there is a digital power supply in the circuit, namely power supply S3, which has two values ​​of high and low, while the analog power supplies S2 and S1 take the default values ​​in the netlist. At this time, S2 is a high voltage and S1 is a low voltage. Therefore, there are two power supply value modes in this example.

[0042] S104: Digital path identification sensitization based on breadth-first search:

[0043] Digital path identification and sensitization are performed based on breadth-first search in each power supply value mode to obtain identification and sensitization results.

[0044] In order to explore the impact of all power supply value modes on the circuit, the present invention proposes a digital path identification sensitization algorithm based on breadth-first search. Compared with the traditional sensitization algorithm in ATPG, the advantage of this algorithm is that it realizes the application of the sensitization algorithm at the transistor level and can be applied to the identification and sensitization of digital paths in mixed analog and digital circuits. Figure 3 FIG. 1 is a flow chart of a digital path identification sensitization method based on breadth-first search in the present invention. Figure 3 As shown, the specific steps of the digital path identification sensitization method based on breadth-first search in the present invention include:

[0045] S301: Initialization data:

[0046] Initialize access collection Voltage Node Queue Path Queue Then, K digital power supplies are added to the access set A and the voltage node queue B, and then K paths are added to the path queue C, where the starting voltage node of the kth path is the kth digital power supply, k=1,2,…,K.

[0047] S302: Get voltage node:

[0048] The voltage node i is taken out from the voltage node queue B and deleted from the voltage node queue B, and then the neighbor voltage node set N(i) of the voltage node i is obtained according to the directed dependency graph.

[0049] S303: Get neighbor voltage nodes:

[0050] The neighbor voltage node j is taken out from the neighbor voltage node set N(i) and deleted from the neighbor voltage node set N(i).

[0051] S304: Determine whether the neighbor voltage node j∈A, that is, whether the neighbor voltage node j has been visited. If yes, proceed to step S310, otherwise proceed to step S305.

[0052] S305: Determine whether the neighbor voltage node j corresponds to a MOS gate, if yes, proceed to step S306, otherwise proceed to step S308.

[0053] S306: Determine the on / off state of the MOS gate:

[0054] If the voltage node i is at a high level and the neighboring voltage node j corresponds to the NMOS gate, or the voltage node i is at a low level and the neighboring voltage node j corresponds to the PMOS gate, the MOS gate state is determined to be on, otherwise the MOS gate state is determined to be off.

[0055] S307: Determine whether the MOS gate state is on, if yes, proceed to step S308, otherwise proceed to step S310.

[0056] S308: Update data:

[0057] Add the neighbor voltage node j to the access set A and the voltage node queue B, and add the neighbor voltage node j to the path queue C behind the path where the voltage node i is located.

[0058] S309: Update neighbor voltage node voltage:

[0059] Traverse the starting point and ending point dictionary of the directed dependency graph. If voltage node i is not the starting point and neighbor voltage node j is the ending point, update the voltage of neighbor voltage node j to the voltage of the starting point of the corresponding path, that is, if the starting point is a high voltage, set the neighbor voltage node j to a high voltage; if the starting point is a low voltage, set the neighbor voltage node j to a low voltage; if it is other cases, update the voltage of neighbor voltage node j to the voltage of voltage node i.

[0060] S310: Determine whether the neighbor node set N(i) is empty. If so, proceed to step S311; otherwise, return to step S303.

[0061] S311: Determine whether the voltage node queue B is empty. If so, identification sensitization is completed and the process goes to step S312; otherwise, the process returns to step S302.

[0062] S312: Output recognition sensitization result:

[0063] The voltage state of each voltage node or the gate state of the MOS tube corresponding to the voltage node is output to obtain the identification sensitization result.

[0064] According to the above description, the present invention propagates each digital power signal along the signal flow direction according to the breadth-first strategy in each power value selection mode. If the signal flow encounters an analog device, a MOS tube source or a drain during active propagation, the signal flow stops propagating on this path, that is, only the circuit devices with digital characteristics are sensitized, and finally the voltage level of each voltage node on the digital path and the gate-controlled on-off status of each MOS tube are obtained.

[0065] Figure 4 In this embodiment Figure 2 The signal flow diagram is shown in Figure 1. Figure 4 As shown, Figure 2 The dual inverter circuit shown performs digital path identification sensitization based on breadth-first search, and the specific process is:

[0066] There is only one digital power supply S3 in this circuit. Here, the voltage of the digital power supply S3 is set to high. Then the high voltage signal of the digital power supply S3 will first try to be transmitted to I1_p (I1_p represents PMOS numbered 1). At this time, the high voltage signal of the digital power supply S3 is transmitted to the gate of I1_p, and the signal is allowed to propagate to I1_p. Then, I1_p is judged to be PMOS, and the high voltage of the digital power supply S3 transmitted to the gate will cut it off, so the signal will no longer continue to propagate to the route connected to I1_p.

[0067] Following the breadth-first principle, after the high voltage signal of digital power supply S3 has completed the on-off judgment and assigned a value to the I1_p node, the high voltage signal of digital power supply S3 will try to be transmitted to I2_n again. At this time, the high voltage signal of digital power supply S3 is transmitted to the gate of I2_n, and the signal is allowed to propagate to I2_n. Then, I2_n is judged to be NMOS, and the high voltage of digital power supply S3 transmitted to the gate will turn it on. After I2_n is turned on, the voltages at both ends of the drain and source of I2_n are equal, that is, the voltage node V1 is assigned to be low.

[0068] After the above process, all adjacent paths of the high voltage signal of the digital power supply S3 have been traversed, and the signal flows to the voltage node V1, then the circuit is sensitized according to the above breadth-first signal flow propagation method starting from the voltage node V1. During the propagation process, the signal flow only goes through the MOS tube gate node and the voltage node, that is, the sensitization result obtained by the present invention is only the digital path sensitization result of the circuit transistor gate. Figure 4 As shown, green represents the MOS that is turned on by the digital power control, red represents the MOS that is turned off by the digital power control, orange represents that the node voltage is high, and yellow represents that the node voltage is low.

[0069] In order to better illustrate the technical effect of the present invention, a specific example is used to experimentally verify the present invention. In this embodiment, a bandgap circuit in a Benchmark reference circuit is used as an example for explanation. Figure 5 : is the bandgap circuit diagram in this embodiment. Figure 5 As shown, the highest voltage available for the bandgap circuit is 2.5V and the lowest voltage is 0V. The method of the present invention is used to perform digital path identification sensitization on the bandgap circuit, and the specific process is as follows:

[0070] First, the bandgap circuit is modeled according to the SPICE netlist of the bandgap circuit to obtain a directed dependency graph. Then the power type is determined. There are three power supplies in the bandgap circuit, among which S3 is connected to the gate of the MOS tube after removing the protection resistor, so it is judged that the power supply S3 is a digital power supply, and the power supplies S2 and S1 are analog power supplies. Therefore, there are two power supply value modes in this embodiment. In power supply value mode 1, power supply S3 is a high voltage, and power supplies S2 and S1 are default values; in power supply mode 2, power supply S3 is a low voltage, and power supplies S2 and S1 are default values. In each power supply value mode, each digital power supply signal is propagated along the signal flow direction based on the breadth-first strategy, and circuit devices with digital characteristics are identified and sensitized. Finally, the voltage level of each node on the digital path of the bandgap circuit and the gate-controlled on-off status of each MOS tube are obtained.

[0071] In this embodiment, the voltage level of each node on the digital path of the Bandgap circuit determined by the present invention is compared with the result obtained by the HSPICE simulator simulation to verify the correctness of the present invention. Table 1 is a comparison table of the node voltage determined by the present invention and the simulated voltage under power value mode 1 in this embodiment.

[0072] Voltage Node Name The voltage obtained by the present invention is high or low Simulated voltage value (V) XI79.net064 low 45.2223u XI79.net011 high 2.5000 XI79.net016 low 1.9040u XI79.net013 low 1.9040u XI79.net068 high 2.5000 XI79.net078 high 2.5000 XI79.net077 high 2.5000 bg low 7.3742u

[0073] Table 1

[0074] As shown in Table 1, the voltage levels of the digital path nodes determined by the present invention are consistent with the voltage values ​​obtained by simulation, which shows that the present invention has high accuracy in determining the voltage levels of the digital path voltage nodes.

[0075] Similarly, the MOS transistors in the present invention whose gates are controlled by a digital power supply to conduct or cut off are compared with the results obtained by simulation using an HSPICE simulator. For PMOS transistors, when Vgs < Vth, the PMOS transistor conducts; otherwise, it cuts off, where Vth is determined by the characteristics of the PMOS transistor (generally a negative number close to 0, and in the circuit used in this example, Vth = -0.4V). For NMOS transistors, when Vgs > Vth, the NMOS transistor conducts; otherwise, it cuts off, where Vth is determined by the characteristics of the NMOS transistor (generally a positive number close to 0, and in the circuit used in this example, Vth = 0.4V). Table 2 is a comparison table of the on / off states of the MOS transistor gates determined by the present invention and the simulation results in Power Supply Value Mode 1 of this embodiment.

[0076]

[0077]

[0078] Table 2

[0079] As shown in Table 2, the on / off states of the MOS transistor gates determined by the present invention are exactly the same as the simulated on / off states of the MOS transistor gates. Therefore, the present invention also has high accuracy in identifying the on / off states of MOS transistors in digital paths.

[0080] In summary, the present invention can accurately implement the sensitization method for identifying digital paths in a digital-analog hybrid circuit, thereby providing strong support for subsequent circuit optimization.

[0081] Although the illustrative specific embodiments of the present invention have been described above for the convenience of those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions created using the concept of the present invention are within the scope of protection.

Claims

1. A method for sensitizing digital paths in a mixed analog-digital circuit, characterized in that: The following steps are involved: S1: Modeling the digital-analog mixed circuit with a directed dependency graph according to the SPICE netlist of the digital-analog mixed circuit to obtain a directed dependency graph, and extracting a start point and end point dictionary of the voltage node according to the directed dependency graph; S2: Divide all power supplies in the digital-analog hybrid circuit into digital power supplies and analog power supplies, and record the number of digital power supplies as K; S3: Set the voltage value of the digital power supply to high or low, and the voltage value of the analog power supply to the default value in the SPICE netlist, and obtain M power supply value modes, where M = 2 K ; S4: Perform digital path identification sensitization based on breadth-first search in each power supply value mode to obtain identification sensitization results. The specific method is: S4.1: Initialize access set Voltage Node Queue Path Queue Then, K digital power supplies are added to the access set A and the voltage node queue B, and then K paths are added to the path queue C, where the starting voltage node of the kth path is the kth digital power supply, k = 1, 2, ..., K; S4.2: Take out voltage node i from voltage node queue B and delete it from voltage node queue B, and then obtain neighbor voltage node set N(i) of voltage node i according to the directed dependency graph; S4.3: Take out the neighbor voltage node j from the neighbor voltage node set N(i) and delete it from the neighbor voltage node set N(i); S4.4: Determine whether the neighbor voltage node j∈A, that is, whether the neighbor voltage node j has been visited. If yes, proceed to step S4.10, otherwise proceed to step S4.5; S4.5: Determine whether the neighbor voltage node j corresponds to a MOS gate, if yes, proceed to step S4.6, otherwise proceed to step S4.8; S4.6: If the voltage node i is at a high level and the neighboring voltage node j corresponds to the NMOS gate, or the voltage node i is at a low level and the neighboring voltage node j corresponds to the PMOS gate, the MOS gate state is determined to be on, otherwise the MOS gate state is determined to be off; S4.7: Determine whether the MOS gate state is on, if yes, go to step S4.8, otherwise go to step S4.10; S4.8: Add the neighbor voltage node j to the access set A and the voltage node queue B, and add the neighbor voltage node j to the path queue C behind the path where the voltage node i is located; S4.9: traverse the start-end dictionary of the directed dependency graph, if the voltage node i is not the start point and the neighbor voltage node j is the end point, update the voltage of the neighbor voltage node j to the voltage of the corresponding path start point, that is, if the start point is a high voltage, set the neighbor voltage node j to a high voltage, if the start point is a low voltage, set the neighbor voltage node j to a low voltage; If it is the other case, the voltage of the neighbor voltage node j is updated to the voltage of the voltage node i; S4.10: Determine whether the neighbor node set N(i) is empty. If so, proceed to step S4.11, otherwise return to step S4.3; S4.11: Determine whether the voltage node queue B is empty. If so, identification sensitization is completed and the process goes to step S4.

12. Otherwise, the process returns to step S4.

2. S4.12: Output the voltage state of each voltage node or the gate state of the MOS tube corresponding to the voltage node to obtain the identification sensitization result.

2. The digital path identification sensitization method according to claim 1, characterized in that: The specific method of power supply classification in step S2 is: traverse each power supply in the digital-analog hybrid circuit in the directed dependency graph, remove the protection resistor of the power supply in the directed dependency graph, and then check whether the power supply is directly connected to the MOS tube gate. If so, it is determined to be a digital power supply, otherwise it is determined to be an analog power supply.

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