Chip layout method and device, electronic equipment and storage medium
Through clustering and replacement technology, unit non-pulse flip-flops in the initial chip layout are merged into multi-bit pulse flip-flops, solving the layout problem of multi-bit flip-flops in high-performance processor design, and improving the merge rate and power consumption optimization effect.
Patent Information
- Application Number
- CN202311167844.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-11
- Publication Date
- 2025-03-11
AI Technical Summary
The prior art is difficult to effectively solve layout problems when multi-bit triggers are applied to high-performance processor designs, resulting in disadvantages in yield and power consumption.
By clustering unit non-pulse flip-flops in the initial chip layout into trigger clusters and finding matching multi-bit flip-flop units in the temporary multi-bit flip-flop library, replacing and optimizing the layout, the multi-bit flip-flop unit is finally restored to pulse generators and pulse flip-flops.
Improve the merge rate of multiple-bit triggers in chip layout, optimize power consumption, and obtain better layout timing results.
Smart Images
Figure CN119598942A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of chip design, and in particular relates to a chip layout method, device, electronic device and storage medium. Background Art
[0002] Multi-bit flip-flops are commonly used sequential logic units in modern high-performance processors. Simply put, a multi-bit flip-flop is a basic unit formed by merging multiple unit flip-flops, where multiple unit flip-flops share a clock port, thereby reducing the number of clock buffers in the chip and reducing the power consumption of the chip.
[0003] In the prior art, the clock ports of multiple triggers are usually connected in parallel to share the same clock source. On this basis, a scan chain embedded in the circuit is designed to form a complete and practical circuit. However, this solution is limited to ordinary trigger circuits. Compared with pulse triggers, this technical solution has disadvantages in yield and power consumption, and cannot solve the layout problem of multi-bit triggers when applied to high-performance processor design. Summary of the invention
[0004] The present application provides a chip layout method, device, electronic device and storage medium.
[0005] Some embodiments of the present application provide a chip layout method, the method comprising:
[0006] When the initial chip layout is obtained, the unit non-pulse triggers in the initial chip layout are clustered to obtain trigger clusters;
[0007] searching a multi-bit flip-flop unit matching the flip-flop cluster in a temporary multi-bit flip-flop library, wherein the temporary multi-bit flip-flop library is generated from a combination of a pulse generator and different numbers of pulse flip-flops;
[0008] replacing the trigger cluster in the initial chip layout with a multi-bit trigger unit;
[0009] Performing layout optimization based on the multi-bit trigger unit to obtain an intermediate chip layout;
[0010] The multi-bit trigger unit in the intermediate chip layout is restored to a pulse generator and a pulse trigger to obtain a target chip layout.
[0011] Optionally, clustering the unit non-pulse triggers in the initial chip layout to obtain trigger clusters includes:
[0012] The unit non-pulse flip-flops with the same clock gating signal in the initial chip layout are clustered to obtain a flip-flop cluster.
[0013] Optionally, clustering unit non-pulse triggers with the same clock gating signal in the initial chip layout to obtain a trigger cluster includes:
[0014] The unit non-pulse flip-flops whose name similarity in the initial chip layout is greater than a similarity threshold and whose clock gating signals are the same are clustered to obtain a flip-flop cluster.
[0015] Optionally, clustering the unit non-pulse triggers in the initial chip layout to obtain trigger clusters includes:
[0016] The unit non-pulse flip-flops in the initial chip layout that are separated by a distance less than a distance threshold and have the same clock gating signal are clustered to obtain a flip-flop cluster.
[0017] Optionally, searching for a multi-bit trigger unit that matches the trigger cluster includes:
[0018] The temporary multi-bit flip-flop library is searched for multi-bit flip-flop units having the same number and layout of flip-flops as those of the multi-bit flip-flop cluster.
[0019] Optionally, the temporary multi-bit trigger library is generated by the following steps:
[0020] Combining a single pulse generator with different numbers of unit pulse flip-flops to obtain multiple different flip-flop layouts;
[0021] Based on the layout mode and the standard cells of the pulse generator and the pulse trigger, a corresponding multi-bit trigger unit is generated.
[0022] Optionally, the restoring the multi-bit trigger unit in the intermediate chip layout into a pulse generator and a pulse trigger to obtain a target chip layout includes:
[0023] Determine the relative positions of the pulse generator and the unit pulse trigger in the multi-bit trigger unit according to the layout of the multi-bit trigger unit;
[0024] The multi-bit trigger unit is restored into a pulse generator and a unit pulse trigger according to the relative position to obtain a target chip layout.
[0025] Optionally, performing layout optimization based on the multi-bit trigger unit includes:
[0026] Calculating the centroid of the trigger cluster in the initial chip layout as the location of the multi-bit trigger unit in the intermediate chip layout;
[0027] The intermediate chip layout is optimized for layout timing based on the position of the multi-bit trigger unit.
[0028] Some embodiments of the present application provide a chip layout device, the device comprising:
[0029] A clustering module, used for clustering unit non-pulse triggers in the initial chip layout to obtain trigger clusters when the initial chip layout is acquired;
[0030] a replacement module, for searching a multi-bit flip-flop unit matching the flip-flop cluster in a temporary multi-bit flip-flop library, wherein the temporary multi-bit flip-flop library is generated from a combination of a pulse generator and a different number of pulse flip-flops;
[0031] replacing the trigger cluster in the initial chip layout with a multi-bit trigger unit;
[0032] Performing layout optimization based on the multi-bit trigger unit to obtain an intermediate chip layout;
[0033] The restoration module is used to restore the multi-bit trigger unit in the intermediate chip layout into a pulse generator and a pulse trigger to obtain a target chip layout.
[0034] Optionally, the clustering module is further used to:
[0035] The unit non-pulse flip-flops with the same clock gating signal in the initial chip layout are clustered to obtain a flip-flop cluster.
[0036] Optionally, the clustering module is further used to:
[0037] The unit non-pulse flip-flops whose name similarity in the initial chip layout is greater than a similarity threshold and whose clock gating signals are the same are clustered to obtain a flip-flop cluster.
[0038] Optionally, the clustering module is further used to:
[0039] The unit non-pulse flip-flops in the initial chip layout that are separated by a distance less than a distance threshold and have the same clock gating signal are clustered to obtain a flip-flop cluster.
[0040] Optionally, the replacement module is further used to:
[0041] The temporary multi-bit flip-flop library is searched for multi-bit flip-flop units having the same number and layout of flip-flops as those of the multi-bit flip-flop cluster.
[0042] Optionally, the replacement module is further used to:
[0043] Combining a single pulse generator with different numbers of unit pulse flip-flops to obtain multiple different flip-flop layouts;
[0044] Based on the layout mode and the standard cells of the pulse generator and the pulse trigger, a corresponding multi-bit trigger unit is generated.
[0045] Optionally, the restoration module is further used to:
[0046] Determine the relative positions of the pulse generator and the unit pulse trigger in the multi-bit trigger unit according to the layout of the multi-bit trigger unit;
[0047] The multi-bit trigger unit is restored into a pulse generator and a unit pulse trigger according to the relative position to obtain a target chip layout.
[0048] Optionally, the replacement module is further used to:
[0049] Calculating the centroid of the trigger cluster in the initial chip layout as the location of the multi-bit trigger unit in the intermediate chip layout;
[0050] The intermediate chip layout is optimized for layout timing based on the position of the multi-bit trigger unit.
[0051] Some embodiments of the present application provide a computing processing device, including:
[0052] a memory having computer readable code stored therein;
[0053] One or more processors, when the computer readable code is executed by the one or more processors, the computing processing device performs the chip layout method as described above.
[0054] Some embodiments of the present application provide a non-transitory computer-readable medium storing a computer-readable code, which, when executed on a computing processing device, causes the computing processing device to execute the above-mentioned chip layout method.
[0055] The present application provides a chip layout method, device, electronic device and storage medium, which clusters unit non-pulse triggers in the initial chip layout into trigger clusters, merges the trigger clusters containing unit non-pulse triggers into multi-bit trigger units, and then replaces the multi-bit trigger units with multi-bit pulse triggers. While the chip layout composed of the obtained pulse triggers and pulse generators has a better layout timing result, the merging rate of multi-bit triggers in the chip layout is improved, thereby obtaining a higher power consumption optimization result.
[0056] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0057] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0058] Figure 1 A schematic diagram of a chip layout method provided in some embodiments of the present application is schematically shown;
[0059] Figure 2 One of the structural diagrams of a multi-bit trigger provided in some embodiments of the present application is schematically shown;
[0060] Figure 3 One of the flowcharts of another chip layout method provided by some embodiments of the present application is schematically shown;
[0061] Figure 4 The second schematic diagram of the structure of a multi-bit trigger provided in some embodiments of the present application is schematically shown;
[0062] Figure 5 The second schematic diagram schematically shows another flow chart of a chip layout method provided in some embodiments of the present application;
[0063] Figure 6 The third flowchart of another chip layout method provided in some embodiments of the present application is schematically shown;
[0064] Figure 7 The structure diagram of a chip layout device provided by some embodiments of the present application is schematically shown;
[0065] Figure 8 A block diagram schematically shows a computing and processing device for executing the method according to some embodiments of the present application;
[0066] Fig. 9 A storage unit for holding or carrying program codes for implementing methods according to some embodiments of the present application is schematically shown. DETAILED DESCRIPTION
[0067] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0068] The introduction of pulse triggers, on the one hand, can optimize the power consumption of the chip and improve the yield of the chip after tape-out production. But on the other hand, the use of pulse triggers must be bound to the pulse generator, otherwise the pulse trigger will lack the necessary clock pulses as clock signal input. For the layout of the pulse trigger, this will add additional physical constraints, resulting in the degradation of the timing of the pulse trigger after layout compared to ordinary triggers.
[0069] Based on this, some embodiments of the present application propose a chip layout method to obtain better layout timing results.
[0070] Figure 1 A schematic diagram of a chip layout method provided by the present application is schematically shown, and the method comprises:
[0071] Step 101 : when an initial chip layout is obtained, the unit non-pulse triggers in the initial chip layout are clustered to obtain trigger clusters.
[0072] It should be noted that the initial chip layout is completed by using a unit non-pulse trigger. The unit non-pulse trigger can be a single edge trigger, a level latch, or other triggers other than a pulse trigger. The specific settings can be based on actual needs and are not limited here. A trigger is a storage component with two stable states that can record binary digital signals "1" and "0". A pulse trigger is a trigger whose output changes at the edge of a clock pulse. Figure 2 , usually the pulse trigger needs to be connected to the pulse generator.
[0073] In an embodiment of the present application, when a user lays out a chip including a multi-bit pulse trigger, a single-bit non-pulse trigger can be used for initial chip layout, or when an initial chip layout composed of single-bit non-pulse triggers already exists, the initial chip layout can be input into a step program system that executes a chip layout method provided in some embodiments of the present application to convert the initial chip layout into a target chip layout composed of multi-bit pulse trigger units.
[0074] Furthermore, when the system obtains the initial chip layout composed of unit non-pulse triggers, in order to replace the unit non-pulse triggers with multi-bit pulse triggers, it is necessary to first aggregate the unit non-pulse triggers into trigger clusters composed of multiple unit non-pulse triggers, and these trigger clusters will be replaced with multi-bit pulse triggers later. Specifically, similar unit non-pulse triggers can be aggregated according to the location, performance parameters, description information and other information of the unit non-pulse triggers, so that the performance of the unit non-pulse triggers in the obtained trigger clusters is similar, which is convenient for subsequent replacement with multi-bit pulse triggers composed of unit pulse triggers.
[0075] Step 102 , searching a temporary multi-bit trigger library for a multi-bit trigger unit that matches the trigger cluster, wherein the temporary multi-bit trigger library is generated from a combination of a pulse generator and different numbers of pulse triggers.
[0076] Step 103: Replace the trigger cluster in the initial chip layout with a multi-bit trigger unit.
[0077] Step 104, perform layout optimization based on the multi-bit trigger unit to obtain an intermediate chip layout. In an embodiment of the present application, the multi-bit trigger unit is a trigger combination composed of multiple unit non-pulse triggers, wherein there are at least two unit non-pulse triggers. The trigger cluster in the initial chip layout can be replaced with a multi-bit trigger unit with the same number of triggers as the trigger cluster. Assuming that the trigger cluster includes n unit non-pulse triggers, the multi-bit trigger unit that replaces it also includes n unit non-pulse triggers, where n is an arbitrary positive integer, but in actual chip design, if n does not exceed 256, the multi-bit trigger has practical significance. It is worth noting that in order to obtain a multi-bit trigger unit with the same chip layout as the multi-bit trigger cluster, multi-bit trigger units with different layouts can be generated in advance based on the number of units included in the initial chip layout to obtain a temporary multi-bit trigger library. The multi-bit trigger units with different layouts in the temporary multi-bit trigger library will not be used as the final output, but will play a transitional role in the intermediate link of the target chip layout generation process. Therefore, the multi-bit trigger units in the temporary multi-bit trigger library do not really exist, but are only chip layout data used temporarily.
[0078] In the specific implementation process, the multi-bit trigger unit only needs to ensure logical equivalence when replacing the trigger cluster. After the trigger cluster in the initial chip layout is replaced with the multi-bit trigger unit, for easy identification, the initial chip layout after replacing the multi-bit trigger unit is called the intermediate chip layout.
[0079] Step 105 , restoring the multi-bit trigger unit in the intermediate chip layout into a pulse generator and a pulse trigger to obtain a target chip layout.
[0080] In the embodiment of the present application, in order to ensure that the logic and spatial layout of the chip layout remain unchanged after the multi-bit trigger unit in the intermediate chip layout is replaced with a pulse generator and a pulse trigger, it is necessary to replace the multi-bit trigger unit with a pulse generator and a pulse trigger having the same trigger layout as the multi-bit trigger unit, so that the layout logic of the target chip layout finally obtained is the same as the initial chip layout. Among them, the trigger arrangement refers to the spatial distribution of each element in the multi-bit trigger unit.
[0081] The embodiment of the present application clusters the unit non-pulse triggers in the initial chip layout into trigger clusters, merges the trigger clusters including the unit non-pulse triggers into multi-bit trigger units, and then replaces the multi-bit trigger units with multi-bit pulse triggers. While the chip layout composed of the pulse triggers and pulse generators obtained has a better layout timing result, the merging rate of the multi-bit triggers in the chip layout is improved, thereby obtaining a higher power consumption optimization result.
[0082] Optionally, the step 101 includes:
[0083] Step 1011 , clustering unit non-pulse flip-flops with the same clock gating signal in the initial chip layout to obtain a flip-flop cluster.
[0084] In the embodiment of the present application, considering that the trigger cluster needs to be merged into a multi-bit trigger in the future, in order to ensure a better timing result of the multi-bit trigger, it is necessary to ensure that the unit non-pulse triggers clustered into the same trigger cluster have the same clock gating signal, so that the multi-bit trigger constituted by the resulting trigger cluster and the unit non-pulse trigger have the same clock gating signal.
[0085] The embodiment of the present application clusters unit non-pulse triggers with the same clock gating signal in the initial chip layout into the same trigger cluster, thereby ensuring that the multi-bit triggers obtained by merging the triggers have better timing results and improving the merging rate of the multi-bit triggers in the chip layout.
[0086] Optionally, the step 1011 includes: clustering unit non-pulse triggers in the initial chip layout whose name similarity is greater than a similarity threshold and whose clock gating signals are the same to obtain a trigger cluster.
[0087] In the embodiment of the present application, name similarity refers to the cosine similarity, sine similarity, etc. of the trigger name of the unit non-pulse trigger, which can be set according to actual needs and is not limited here. Considering that if the names of the triggers are similar, the performance of the triggers is generally similar, so the unit non-pulse triggers with similar name similarities between the triggers can be clustered. Generally, the higher the name similarity, the closer the name, so the unit non-pulse triggers with similar names can be clustered by setting the name similarity. The similarity threshold can be 80%, 70%, etc., which can be set according to actual needs and is not limited here. For example, unit non-pulse triggers such as bus_reg_0, bus_reg_1...bus_reg_n, which only have different last characters, can be clustered.
[0088] The embodiment of the present application clusters unit non-pulse triggers whose trigger name similarity is greater than a similarity threshold, so that unit non-pulse triggers with similar performance can be clustered into a unified trigger cluster, thereby ensuring that the multi-bit triggers obtained by merging the triggers have better timing results and improving the merging rate of multi-bit triggers in chip layout.
[0089] Optionally, the step 1011 includes: clustering unit non-pulse triggers in the initial chip layout that are separated by a distance less than a distance threshold and have the same clock gating signal to obtain a trigger cluster.
[0090] In the embodiment of the present application, considering that the performance of triggers that are closely spaced are usually similar, in order to ensure that the timing results of the obtained multi-bit triggers are high, the unit non-pulse triggers that are spaced less than the distance threshold can be clustered into the same trigger cluster, where it is only necessary to ensure that the distance between two adjacent unit non-pulse triggers is less than the distance threshold, and it is not necessary for the distance between every two unit non-pulse triggers to be less than the distance threshold. For example, if the distance between a0_reg, a1_reg...an_reg is less than m and the clock gating signal is the same, then it can be considered that the above n triggers can be aggregated into a trigger cluster.
[0091] The embodiment of the present application clusters unit non-pulse triggers whose distance from adjacent triggers is less than a distance threshold into the same trigger cluster, thereby ensuring that the multi-bit triggers obtained by merging the triggers have better timing results and improving the merging rate of multi-bit triggers in chip layout.
[0092] Optionally, the step 102 includes searching a temporary multi-bit trigger library for multi-bit trigger units having the same trigger quantity and layout as those of the multi-bit trigger cluster.
[0093] In an embodiment of the present application, a temporary multi-bit trigger library is used to store the correspondence between multi-bit trigger units and multi-bit pulse triggers with the same trigger arrangement, and includes trigger arrangements of different numbers of triggers that may be used, wherein the multi-bit pulse triggers and multi-bit trigger units with the same arrangement have the same number of elements and spatial distribution.
[0094] In order to replace the non-pulse trigger with a pulse trigger, a temporary multi-bit trigger library is required, including a temporary physical LEF library (Library Exchange Format, which describes the library information of the design) and a timing LIB library (static library). Temporary means that the so-called "multi-bit trigger" contained therein is not a real device, but only a concept at the data level. Similarly, there is no device warehouse in the temporary multi-bit trigger library, but a database for storing multi-bit trigger-related data. The temporary multi-bit trigger library and multi-bit trigger units do not come from standard cell providers such as process manufacturers. It is just because we need to use the multi-bit trigger layout optimization feature of EDA (Electronic Design Automation) tools for layout optimization, so such a database and corresponding description files are generated for EDA tool layout optimization. It is a library that only exists in the layout optimization process. Among them, the LEF file of standard cells such as unit pulse triggers contained in the temporary multi-bit trigger library defines two parts of the process technology information and standard cell design information of the integrated circuit. Among them, the standard cell design information is an abstraction of the standard cell and is the application form of the standard cell in the layout and wiring tool.
[0095] Specifically, it is necessary to extract a trigger arrangement with the same number of triggers as the trigger cluster from the temporary multi-bit trigger library, and then replace the trigger cluster with the multi-bit trigger unit corresponding to the trigger arrangement. The multi-bit trigger library can be pre-generated or generated in real time during the process of the system making the target chip layout. It can be set according to actual needs and is not limited here.
[0096] The embodiment of the present application associates and stores multi-bit trigger units of various trigger arrangements with different numbers of triggers in a temporary multi-bit trigger library with multi-bit pulse triggers, thereby ensuring that the trigger cluster can be replaced with a multi-bit trigger with the same number of triggers, ensuring that the multi-bit trigger obtained by merging the triggers has a better timing result, and improving the merging rate of multi-bit triggers in the chip layout.
[0097] Optionally, refer to Figure 3 , the temporary multi-bit trigger library is generated by the following steps:
[0098] Step 201 , combining a single pulse generator and different numbers of unit pulse triggers to obtain a plurality of different trigger layouts.
[0099] Step 202 : Generate corresponding multi-bit trigger units based on the layout mode and the standard units of the pulse generator and the pulse trigger.
[0100] In the embodiment of the present application, a single pulse generator and different numbers of pulse triggers can be combined to obtain multiple different trigger arrangements. Even if the number of pulse generators and pulse triggers is the same, different trigger arrangements can be used to combine, for example, Figure 4 , which includes three trigger arrangements including 1 pulse generator and 4 pulse triggers, namely vertical arrangement, horizontal arrangement and center surround arrangement. Of course, this is only an exemplary description, and the specific trigger arrangement can be set according to actual needs, and is not limited this time.
[0101] Then, we use EDA chip design tools to extract LEF libraries of multi-bit triggers with different bit numbers from different trigger arrangements. Based on the trigger arrangement of the multi-bit trigger, we use chip design tools to extract LIB libraries of multi-bit triggers with different bit numbers. At this point, the temporary physical LEF library and temporary timing LIB library of the multi-bit trigger are generated, that is, the multi-bit pulse trigger and multi-bit trigger unit with the same trigger arrangement are associated and stored.
[0102] The embodiment of the present application obtains a multi-bit trigger library by combining a single pulse generator and different numbers of pulse triggers to obtain multi-bit triggers with various trigger arrangements. The multi-bit trigger library can be used for trigger merging processes with various trigger numbers and arrangements, thereby improving the compatibility of trigger merging in chip layout.
[0103] Optionally, refer to Figure 5 , the step 105 comprises:
[0104] Step 1051, determining the relative positions of the pulse generator and the unit pulse trigger in the multi-bit trigger unit according to the layout of the multi-bit trigger unit.
[0105] Step 1052, restore the multi-bit trigger unit into a pulse generator and a unit pulse trigger according to the relative position to obtain a target chip layout.
[0106] In the embodiment of the present application, a multi-bit trigger library is searched for a multi-bit pulse trigger corresponding to the trigger arrangement with reference to a layout of a multi-bit trigger unit, and then the relative position of the pulse generator and the pulse trigger is determined, and then the multi-bit trigger is split into a pulse generator and a pulse trigger. During the splitting process, the logical equivalence before and after needs to be ensured.
[0107] The embodiment of the present application replaces the non-multi-bit pulse trigger with a multi-bit pulse trigger with the same trigger arrangement, thereby ensuring that the multi-bit trigger obtained by merging the triggers has a better timing result and improving the merging rate of the multi-bit triggers in the chip layout.
[0108] Optionally, refer to Figure 6 , the step 104 comprises:
[0109] Step 1041, calculating the centroid of the trigger cluster in the initial chip layout as the location of the multi-bit trigger unit in the intermediate chip layout;
[0110] Step 1042 , optimizing the layout timing of the intermediate chip layout based on the position of the multi-bit trigger unit.
[0111] In the embodiments of the present application, two optimization strategies can be used to complete the layout timing optimization based on multi-bit triggers. One is to extract the information of replacing the trigger cluster with the multi-bit trigger, and provide it as input to the chip design tool, and then the chip design tool completes the layout optimization. The other is to calculate the center of mass of the trigger cluster and provide it as the coordinates of the replaced multi-bit trigger to the chip design tool. After fixing the position of the multi-bit trigger, the chip design tool completes the incremental layout optimization. Both methods can be used for chip layout optimization. Of course, if the chip design tool can better support the layout of multi-bit triggers, the first optimization strategy can be used. If the effect is poor, the second optimization strategy can be used.
[0112] The embodiment of the present application optimizes the layout timing of the intermediate chip layout after replacing the trigger cluster with a multi-bit trigger unit, thereby ensuring that the multi-bit triggers obtained by merging the triggers have good timing results and improving the merging rate of the multi-bit triggers in the chip layout.
[0113] Optionally, refer to Figure 6 After step 103, the method further includes:
[0114] Step 301 : Optimize the layout timing of the target chip layout based on the centroid position.
[0115] In the embodiment of the present application, when the multi-bit trigger unit is replaced by a multi-bit pulse trigger including a pulse generator and a pulse trigger, the timing information will be offset to a certain extent. Therefore, the post-layout optimization module will call the chip design tool to perform another post-layout incremental timing optimization to obtain better timing results.
[0116] The embodiment of the present application optimizes the layout timing of the chip layout again after obtaining the target chip layout composed of multi-bit pulse triggers, thereby ensuring that the multi-bit triggers obtained by merging the triggers have good timing results and improving the merging rate of the multi-bit triggers in the chip layout.
[0117] Figure 7 The structure diagram of a chip layout device 40 provided by the present application is schematically shown, and the device includes:
[0118] A clustering module 401 is used for clustering unit non-pulse triggers in the initial chip layout to obtain trigger clusters when the initial chip layout is acquired;
[0119] A replacement module 402 is used to search for a multi-bit flip-flop unit matching the flip-flop cluster in a temporary multi-bit flip-flop library, wherein the temporary multi-bit flip-flop library is generated from a combination of a pulse generator and a different number of pulse flip-flops;
[0120] replacing the trigger cluster in the initial chip layout with a multi-bit trigger unit;
[0121] Performing layout optimization based on the multi-bit trigger unit to obtain an intermediate chip layout;
[0122] The restoration module 403 is used to restore the multi-bit trigger unit in the intermediate chip layout to a pulse generator and a pulse trigger to obtain a target chip layout.
[0123] Optionally, the clustering module 401 is further used for:
[0124] The unit non-pulse flip-flops with the same clock gating signal in the initial chip layout are clustered to obtain a flip-flop cluster.
[0125] Optionally, the clustering module 401 is further used for:
[0126] The unit non-pulse flip-flops whose name similarity in the initial chip layout is greater than a similarity threshold and whose clock gating signals are the same are clustered to obtain a flip-flop cluster.
[0127] Optionally, the clustering module 401 is further used for:
[0128] The unit non-pulse flip-flops in the initial chip layout that are separated by a distance less than a distance threshold and have the same clock gating signal are clustered to obtain a flip-flop cluster.
[0129] Optionally, the replacement module 402 is further configured to:
[0130] The temporary multi-bit flip-flop library is searched for multi-bit flip-flop units having the same number and layout of flip-flops as those of the multi-bit flip-flop cluster.
[0131] Optionally, the replacement module 402 is further configured to:
[0132] Combining a single pulse generator with different numbers of unit pulse flip-flops to obtain multiple different flip-flop layouts;
[0133] Based on the layout mode and the standard cells of the pulse generator and the pulse trigger, a corresponding multi-bit trigger unit is generated.
[0134] Optionally, the restoring module 403 is further configured to:
[0135] Determine the relative positions of the pulse generator and the unit pulse trigger in the multi-bit trigger unit according to the layout of the multi-bit trigger unit;
[0136] The multi-bit trigger unit is restored into a pulse generator and a unit pulse trigger according to the relative position to obtain a target chip layout.
[0137] Optionally, the replacement module 402 is further configured to:
[0138] Calculating the centroid of the trigger cluster in the initial chip layout as the location of the multi-bit trigger unit in the intermediate chip layout;
[0139] The intermediate chip layout is optimized for layout timing based on the position of the multi-bit trigger unit.
[0140] The embodiment of the present application clusters the unit non-pulse triggers in the initial chip layout into trigger clusters, merges the trigger clusters including the unit non-pulse triggers into multi-bit trigger units, and then replaces the multi-bit trigger units with multi-bit pulse triggers. While the chip layout composed of the pulse triggers and pulse generators obtained has a better layout timing result, the merging rate of the multi-bit triggers in the chip layout is improved, thereby obtaining a higher power consumption optimization result.
[0141] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.
[0142] The various component embodiments of the present application can be implemented in hardware, or implemented in software modules running on one or more processors, or implemented in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all functions of some or all components in the computing processing device according to the embodiment of the present application. The application can also be implemented as a device or apparatus program (e.g., computer program and computer program product) for performing a part or all of the methods described herein. Such a program implementing the present application can be stored on a non-transient computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.
[0143] For example, Figure 8 A computing processing device that can implement the method according to the present application is shown. The computing processing device traditionally includes a processor 510 and a computer program product or a non-transitory computer-readable medium in the form of a memory 520. The memory 520 can be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk or a ROM. The memory 520 has a storage space 530 for a program code 531 for executing any method step in the above method. For example, the storage space 530 for the program code may include individual program codes 531 for implementing various steps in the above method respectively. These program codes can be read from or written to one or more computer program products. These computer program products include program code carriers such as a hard disk, a compact disk (CD), a memory card or a floppy disk. Such a computer program product is usually as shown in reference Fig. 9 The portable or fixed storage unit. The storage unit may have Figure 8The memory 520 in the computing and processing device of the computer 520 is similarly arranged as a storage segment, a storage space, etc. The program code can be compressed, for example, in an appropriate form. Generally, the storage unit includes a computer readable code 531 ', that is, a code that can be read by a processor such as 510, which, when executed by the computing and processing device, causes the computing and processing device to perform the various steps in the method described above.
[0144] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.
[0145] The term "one embodiment", "embodiment" or "one or more embodiments" herein means that a particular feature, structure or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application. In addition, please note that the examples of the term "in one embodiment" here do not necessarily all refer to the same embodiment.
[0146] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.
[0147] In the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.
[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A chip layout method, characterized in that: The method comprises: When the initial chip layout is obtained, the unit non-pulse triggers in the initial chip layout are clustered to obtain trigger clusters; searching a multi-bit flip-flop unit matching the flip-flop cluster in a temporary multi-bit flip-flop library, wherein the temporary multi-bit flip-flop library is generated from a combination of a pulse generator and different numbers of pulse flip-flops; replacing the trigger cluster in the initial chip layout with a multi-bit trigger unit; Performing layout optimization based on the multi-bit trigger unit to obtain an intermediate chip layout; The multi-bit trigger unit in the intermediate chip layout is restored to a pulse generator and a pulse trigger to obtain a target chip layout.
2. The method according to claim 1, characterized in that The step of clustering the unit non-pulse triggers in the initial chip layout to obtain trigger clusters includes: The unit non-pulse flip-flops with the same clock gating signal in the initial chip layout are clustered to obtain a flip-flop cluster.
3. The method according to claim 2, characterized in that The clustering of unit non-pulse triggers with the same clock gating signal in the initial chip layout to obtain a trigger cluster includes: The unit non-pulse flip-flops whose name similarity in the initial chip layout is greater than a similarity threshold and whose clock gating signals are the same are clustered to obtain a flip-flop cluster.
4. The method according to claim 2, characterized in that: The step of clustering the unit non-pulse triggers in the initial chip layout to obtain trigger clusters includes: The unit non-pulse flip-flops in the initial chip layout that are separated by a distance less than a distance threshold and have the same clock gating signal are clustered to obtain a flip-flop cluster.
5. The method according to claim 1, characterized in that The searching for a multi-bit trigger unit matching a trigger cluster comprises: The temporary multi-bit flip-flop library is searched for multi-bit flip-flop units having the same number and layout of flip-flops as those of the multi-bit flip-flop cluster.
6. The method according to claim 5, characterized in that The temporary multi-bit trigger library is generated by the following steps: Combining a single pulse generator with different numbers of unit pulse flip-flops to obtain multiple different flip-flop layouts; Based on the layout mode and the standard cells of the pulse generator and the pulse trigger, a corresponding multi-bit trigger unit is generated.
7. The method according to claim 5, characterized in that The step of restoring the multi-bit trigger unit in the intermediate chip layout to a pulse generator and a pulse trigger to obtain a target chip layout includes: Determine the relative positions of the pulse generator and the unit pulse trigger in the multi-bit trigger unit according to the layout of the multi-bit trigger unit; The multi-bit trigger unit is restored into a pulse generator and a unit pulse trigger according to the relative position to obtain a target chip layout.
8. The method according to claim 1, characterized in that The performing layout optimization based on the multi-bit trigger unit includes: Calculating the centroid of the trigger cluster in the initial chip layout as the location of the multi-bit trigger unit in the intermediate chip layout; The intermediate chip layout is optimized for layout timing based on the position of the multi-bit trigger unit.
9. A chip layout device, characterized in that: The device comprises: A clustering module, used for clustering unit non-pulse triggers in the initial chip layout to obtain trigger clusters when the initial chip layout is acquired; a replacement module, for searching a multi-bit flip-flop unit matching the flip-flop cluster in a temporary multi-bit flip-flop library, wherein the temporary multi-bit flip-flop library is generated from a combination of a pulse generator and a different number of pulse flip-flops; replacing the trigger cluster in the initial chip layout with a multi-bit trigger unit; Performing layout optimization based on the multi-bit trigger unit to obtain an intermediate chip layout; The restoration module is used to restore the multi-bit trigger unit in the intermediate chip layout into a pulse generator and a pulse trigger to obtain a target chip layout.
10. A computing device, characterized in that: include: a memory having computer readable code stored therein; One or more processors, when the computer readable code is executed by the one or more processors, the computing processing device performs the chip layout method according to any one of claims 1 to 8.
11. A non-transitory computer readable medium, characterized in that A computer readable code is stored, and when the computer readable code is run on a computing processing device, the computing processing device is caused to execute the chip layout method according to any one of claims 1 to 8.