Chip layout processing method, device and equipment, computer storage medium and program product

Abstract

The invention discloses a chip layout processing method and device, equipment, a computer storage medium and a program product, and the method comprises the steps: obtaining a chip layout; the chip layout is divided according to a preset division rule to obtain a plurality of divided area graphs, and the preset division rule is used for enabling graphs in each divided area graph and any graph in the adjacent divided area graph not to have a conflict relation; according to a graph dyeing algorithm, dyeing each graph in each divided area graph to obtain a dyed area graph; obtaining a graphic feature of each graph, and adjusting the dyeing of each dyeing area graph according to the graphic feature of each graph to obtain a plurality of target dyeing area graphs; and performing splitting processing on graphs with different colors in each target dyeing area graph to obtain a chip split graph. According to the method, the graphs involved in the chip layout can be uniformly split.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a chip layout processing method, device, equipment, computer storage medium and program product. Background Art

[0002] With the development of technology, the complexity of modern semiconductor integrated circuit (IC) design has increased significantly. Integrated circuits need to implement complex functions in a very small area, resulting in more and more parameters and factors to be considered in the design process.

[0003] Traditional photolithography technology relies on a single exposure to form circuit patterns, but as the size of integrated circuits continues to shrink, the resolution that can be achieved by a single exposure (i.e., the minimum manufacturable feature size) is facing limitations. Double Patterning Technology (DPT) bypasses the limitations of optical resolution by splitting complex patterns into multiple sub-patterns, each of which is exposed using an independent mask. With the increasing demand for high-precision manufacturing processes, how to effectively split the layout has become the key to improving overall production efficiency and reducing defect rates. Summary of the invention

[0004] The embodiments of the present application provide a chip layout processing method, device, equipment, computer storage medium and program product, which can evenly split the graphics involved in the chip layout.

[0005] In a first aspect, an embodiment of the present application provides a chip layout processing method, the method comprising:

[0006] Obtaining a chip layout, wherein the chip layout includes a plurality of graphics;

[0007] The chip layout is divided according to a preset division rule to obtain a plurality of division area maps, wherein the preset division rule is used to ensure that the graphics in each division area map do not conflict with any graphics in an adjacent division area map;

[0008] Each graph in each partition region graph is dyed according to a graph dyeing algorithm to obtain a dyed region graph. The graph dyeing algorithm is used to make the dyeing colors of the graphs in conflicting relationships in each partition region graph different;

[0009] Get the graphic features of each graphic;

[0010] According to the graphic features of each graphic, the coloring of each coloring region map is adjusted to obtain a plurality of target coloring region maps, so that the ratio of the coloring areas of graphics with different coloring colors in all the target coloring region maps meets the area ratio condition;

[0011] Split the graphics with different colors in the target staining area map into different chip split maps.

[0012] In a second aspect, an embodiment of the present application provides a chip layout processing device, the device comprising:

[0013] An acquisition module is used to acquire a chip layout, wherein the chip layout includes a plurality of graphics;

[0014] A partitioning module is used to partition the chip layout according to a preset partitioning rule to obtain a plurality of partitioning area maps, wherein the preset partitioning rule is used to ensure that the graphics in each partitioning area map do not conflict with any graphics in an adjacent partitioning area map;

[0015] A coloring module is used to color each graph in each partitioned region graph according to a graph coloring algorithm to obtain a colored region graph. The graph coloring algorithm is used to make the graphics in conflicting relationships in each partitioned region graph have different coloring colors.

[0016] The acquisition module is also used to obtain the graphic features of each graphic;

[0017] An adjustment module is used to adjust the coloring of each coloring region map according to the graphic features of each graphic, and obtain multiple target coloring region maps, so that the ratio of the coloring areas of graphics with different coloring colors in all the target coloring region maps meets the area ratio condition;

[0018] The splitting module is used to split the graphics with different colors in the target staining area map into different chip splitting maps.

[0019] In a third aspect, an embodiment of the present application provides a chip layout processing device, the device comprising: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the above-mentioned chip layout processing method is implemented.

[0020] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having computer program instructions stored thereon, and the computer program instructions implement the above-mentioned chip layout processing method when executed by a processor.

[0021] In a fifth aspect, an embodiment of the present application provides a computer program product. When instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the above-mentioned chip layout processing method.

[0022] In an embodiment of the present application, the chip layout is obtained and the chip layout is divided and processed using preset division rules, so that there is no conflict relationship between the graphics in the divided areas, which can avoid the problem of image overlap or image distance being too close; the graphics are colored by a graph coloring algorithm to ensure that the graphics with conflicting relationships have different colors, which can effectively distinguish different graphics; graphics of the same color will be assigned to the same layer in subsequent operations, which is helpful for processing the simultaneous splitting of different areas and reducing interference between adjacent areas; obtaining graphic features is beneficial for analyzing the distribution of each graphic in the layout; the dyeing results are optimized and adjusted according to the graphic features, so that different areas can be processed more evenly during splitting, ensuring the uniformity of the color of the graphics after splitting; finally, the graphics of different colors are actually split in the dyeing area map to ensure that the graphics of the final chip splitting map are evenly distributed. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 It is a schematic flow chart of a chip layout processing method provided in an embodiment of the present application;

[0025] Figure 2 It is a dyeing effect diagram corresponding to dyeing according to the initial dyeing priority provided in an embodiment of the present application;

[0026] Figure 3 It is a dyeing effect diagram corresponding to dyeing according to the target dyeing priority provided in an embodiment of the present application;

[0027] Figure 4 It is a schematic diagram of a layout division provided in an embodiment of the present application;

[0028] Figure 5 is a schematic diagram of the structure of a chip layout processing device provided in an embodiment of the present application;

[0029] Figure 6 It is a schematic diagram of the hardware structure of the chip layout processing device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0030] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0031] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0032] Semiconductor layout design involves placing circuit elements on a chip. In order to optimize chip performance and manufacturing costs, it is often necessary to split the design into multiple regions for processing. This split must be even to balance the wiring requirements, logic complexity, and manufacturing difficulty of each part.

[0033] In the prior art, when splitting, the density of the graph is mainly calculated and the density between different regions is balanced by exchanging part of the graph, for example, exchanging part of the graph in the dense region of P1 to the relatively sparse region of P2.

[0034] The application of existing technologies in double patterning technology has solved the problem of uneven pattern density to a certain extent, but because it relies on the calculation and optimization of local density, it is easy to ignore the uneven density of certain key areas, thus affecting the quality of lithography. In addition, when faced with complex patterns, this method may fall into a local optimal solution and fail to achieve the global optimal solution. This local optimization strategy may result in significant density differences in the global scope, thereby reducing the accuracy and consistency of the final pattern.

[0035] In addition, the existing technology has limited computational accuracy in local optimization algorithms, especially when dealing with some extremely dense or sparse areas, and may not be able to effectively capture and correct potential lithography errors. This lack of accuracy will directly affect the final manufacturing yield and lead to a higher defect rate.

[0036] In order to solve the problems of the prior art, the embodiments of the present application provide a chip layout processing method, device, equipment, computer storage medium and computer program product. The chip layout processing method provided by the embodiments of the present application is first introduced below.

[0037] Figure 1 FIG. 1 is a flow chart of a chip layout processing method provided by an embodiment of the present application. Figure 1 As shown, Figure 1 The process includes the following steps S101 to S106.

[0038] S101. Obtain chip layout.

[0039] The chip layout includes multiple graphics.

[0040] A chip layout is a representation of a circuit design, typically including graphics corresponding to multiple circuit elements (such as resistors, capacitors, transistors, etc.) to show the internal structure and circuit connections of the chip.

[0041] As an example but not a limitation, assume that there are multiple rectangular areas (or other shapes that can represent circuit elements) on the chip layout, which represent different circuit elements, such as one part represents a logic gate and another part represents a power line. It can be understood that different types of chip layouts correspond to different specific graphics, and the graphics in the specific chip layout can be determined according to actual conditions.

[0042] S102: Divide the chip layout according to a preset division rule to obtain a plurality of division area maps.

[0043] The preset division rule is used to ensure that the graphics in each divided area graph do not conflict with any graphics in an adjacent divided area graph.

[0044] The conflict relationship can be understood as the distance between the graphics is too close or there is overlap between the graphics.

[0045] As an example but not a limitation, assuming that parts of two graphics overlap, it is considered that the two rectangular graphics are in a conflicting relationship.

[0046] Correspondingly, the preset division rule can be understood as re-planning the layout in the chip according to some set rules, so that the graphics in the chip layout are not too close or overlapped.

[0047] As an example but not limitation, the preset division rule may be to traverse the distance between the graphics and divide the graphics without conflict relationship into adjacent areas. For example, assuming that there is no conflict relationship between two graphics A and B, then the A graphic is divided into the first area, and the B graphic is divided into the second area. The first area and the second area are adjacent to each other, thereby obtaining multiple divided area graphs.

[0048] As an example but not limitation, the preset division rule may be to use geometric division (such as grid division) to divide the area, and the area may be divided by adjusting the size of the grid so that there is no conflict between the graphics in adjacent grids (which can be considered as adjacent areas).

[0049] As an example but not limitation, the preset division rule can be to divide by density segmentation, for example, to divide according to graphic density. The division can be performed by adjusting the graphic density in each area, and the graphics in the denser areas can be adjusted to other smaller areas, so that there is no conflict between the graphics in adjacent areas after the division.

[0050] As an example but not limitation, the preset division rule may be a logical division method, such as division according to circuit function, where graphics that implement the same circuit function are divided into the same area, while also paying attention to the conflict relationship between graphics within the area, so that there is no conflict relationship between graphics in adjacent areas after division.

[0051] It can be understood that by dividing the chip layout using preset division rules so that there is no conflict between the graphics in adjacent areas after division, it is possible to avoid image overlap or images being too close, which is beneficial to avoid image connection during subsequent exposure.

[0052] S103. Color each graph in each divided region graph according to a graph coloring algorithm to obtain a colored region graph.

[0053] The graph coloring algorithm is used to make each adjacent graph in each partitioned area graph have different coloring colors.

[0054] A graph coloring algorithm is an algorithm used to solve graph theory problems, specifically a strategy for coloring the vertices or edges of a graph to satisfy a certain condition. The goal of the algorithm is to color the vertices of the graph with the fewest colors possible, so that conflicting vertices do not use the same color.

[0055] Suppose there is a graph in which the vertices represent the objects to be colored, and the edges between the vertices represent the conflicts or mutually exclusive relationships between these objects (i.e., adjacent objects cannot have the same color). For example, there are vertices A, B, and C; edges: A is adjacent to B, and B is adjacent to C.

[0056] Start with the uncolored vertex A and color A 1. Next, look at B, which is adjacent to A. Since A's color is 1, B cannot use color 1, so color B 2. Then look at C, which is adjacent to B, so C cannot use color 2 and can be colored 1.

[0057] The final dyeing results can be: A: Color 1. B: Color 2. C: Color 1.

[0058] Combining multiple partitioned region graphs, assuming there are two circuit elements forming an "L" shape, one can be dyed red and the other can be dyed blue, and so on. By traversing all partitioned region graphs and obtaining a dyed region graph, it will be ensured that the regions with connected edges do not use the same color.

[0059] The graph coloring algorithm is used to color the graphs, so that the graphs with conflicting relationships have different colors, which can effectively distinguish different graphs. The graphs of the same color will be assigned to the same layer in subsequent operations, which helps to split different areas at the same time, reduce interference between adjacent areas, and help implement uniform splitting.

[0060] S104: Obtain graphic features of each graphic.

[0061] Graphic features can be understood as parameters that describe the properties of the graphics themselves (such as shape, occupied area, etc.). Graphic features can be used to understand the graphics status on the layer, and thus determine whether the graphics included in any two layers are evenly distributed based on the graphics status.

[0062] The graphic features include at least one of the following: graphic projection overlap length and graphic area.

[0063] The area of ​​a figure can be calculated based on the shape and size of different figures. For example, the area of ​​a rectangular figure can be calculated after the side length is known. The specific calculation method can refer to relevant mathematical principles, which will not be repeated here.

[0064] The overlapping length of graphic projections refers to the length of the overlapping part of the projections of two or more graphics in a specific direction (usually the x-axis or y-axis in two-dimensional space). In other words, when two graphics have overlapping projections in the same direction, the length of the overlapping part is the overlapping part in this direction.

[0065] The specific area data and projection overlap length data can be calculated based on actual conditions and will not be listed here one by one.

[0066] In addition, other graphic features that can be used to determine whether the graphics included in any two layers are evenly distributed can also be included, which will not be listed here one by one.

[0067] It can be understood that graphic features are helpful in analyzing the relative position and occupied area of ​​each graphic in the layout, thereby providing a basis for determining how to evenly split it.

[0068] S105. Adjust the coloring of each coloring region map according to the graphic features of each graphic to obtain multiple target coloring region maps, so that the ratio of the coloring areas of graphics with different coloring colors in all target coloring region maps meets the area ratio condition.

[0069] The purpose of this step is to dynamically adjust the coloring results by analyzing and comparing graphic features to meet the requirements of area division or optimize the overall design.

[0070] The area ratio condition refers to a condition that can reflect whether the sizes of the dyeing areas corresponding to the graphics with different dyeing colors meet the corresponding ratio range.

[0071] As an example but not limitation, the area of ​​the dyed graphics may be directly calculated to determine whether the areas corresponding to graphics of different colors satisfy the corresponding ratio range.

[0072] As an example but not limitation, the size of the colored area of ​​the graphic can also be indirectly determined by calculating other features of the graphic, thereby determining whether the areas corresponding to graphics of different colors meet the corresponding proportional range. For example, the proportional range of the graphic area can be indirectly reflected by calculating the overlapping length of the projection of the graphic.

[0073] For example, by calculating the area of ​​the blue area and the red area, if the calculated result is that the area of ​​the blue area is too small and the area of ​​the red area is too large, the color of a portion of the appropriate red area can be adjusted to blue, so that the areas corresponding to the two colors are evenly distributed. It can be understood that the even distribution can be a 1:1 distribution or a 1.1:1 distribution, etc. The specific ratio can be adjusted according to different process requirements and is not limited here.

[0074] For another example, the coloring result can be adjusted by calculating the overlapping length of the graphic projections of multiple graphics. Assuming that the overlapping length of the graphic projections between any two graphics is calculated and it is found that the overlapping length exceeds a preset range (which can be customized), it can be considered that there is a conflict in the coloring between the two graphics, and the colors of the two graphics are changed to be different from the previous coloring.

[0075] By traversing the graphic areas and / or graphic projection overlap lengths on all the dyeing area maps, it is found whether there are areas with too large a difference in dyeing area or areas where the graphic projection overlap length does not meet the preset range, so as to further adjust the dyeing colors of these areas and finally obtain the target dyeing area map.

[0076] According to the characteristics of the graph, the dyeing region map is updated to reflect a more reasonable region allocation. This step ensures that the dyeing results can be appropriately adjusted while considering the characteristics of the graph, so that different regions can be treated more evenly during splitting, ensuring the uniformity of the features after splitting.

[0077] S106, splitting the graphics with different colors in the target staining area map into different chip splitting maps.

[0078] As an example but not a limitation, the area of ​​the dyed region corresponding to the graphic in the chip splitting diagram meets the preset area condition.

[0079] The preset area condition can be calculated based on the area of ​​all graphics and the number of chip split diagrams. For example, if the graphic area of ​​all graphics is 4 and two chip split diagrams are required, the preset area condition is 4 divided by 2, that is, 2. The specific data can be set according to the actual situation and will not be listed here one by one.

[0080] This step refers to splitting graphics with different colors onto different mask layers. It can also be understood that the colors of graphics on the same mask layer are consistent, and there is no conflict between these graphics.

[0081] Here you can use color thresholds or color ranges to identify different color regions. For example, to identify red regions, you can set the RGB range for red. Traverse the image pixels, if the color of the pixel is within the red range, mark it as graph 1, if it is within the blue range, mark it as graph 2. Create two new graphs and extract all red graphs into the new Figure 1 Extract all blue graphics to another new Figure 2 At the same time, the area of ​​the split red figure and the area of ​​the blue figure meet the preset area conditions.

[0082] Finally, the graphics with different colors are actually split in the dyeing area map to ensure that the graphic area of ​​the final chip splitting map meets the preset area conditions.

[0083] By obtaining the chip layout and using the preset division rules to divide the chip layout, there is no conflict relationship between the graphics in the divided area, which can avoid the problem of image overlap or image distance being too close; the graphics are colored by the graph coloring algorithm to ensure that the graphics with conflicting relationships have different colors, which can effectively distinguish different graphics; graphics of the same color will be assigned to the same layer in subsequent operations, which is helpful for processing the simultaneous splitting of different areas and reducing interference from adjacent areas; by obtaining graphic features, it is helpful to analyze the relative position and occupied area of ​​each graphic in the layout; the dyeing results are optimized and adjusted according to the graphic features, so that different areas can be processed more evenly during splitting, ensuring the uniformity of the color of the graphics after splitting; finally, the graphics of different colors are actually split in the dyeing area map to ensure that the graphics of the final chip splitting map are evenly distributed.

[0084] In one implementation, the graphic features include at least one of the following: the graphic projection overlapping length and the graphic area; adjusting each dyeing area map according to the graphic features of each graphic to obtain multiple target dyeing area maps, including: obtaining the dyeing priority corresponding to each graphic in each divided area map to obtain an initial dyeing priority, the dyeing priority is used to determine the dyeing color corresponding to each graphic, wherein graphics with different dyeing priorities correspond to different dyeing colors; adjusting the initial dyeing priority according to the graphic area corresponding to each graphic, until the ratio between the dyeing areas corresponding to graphics with different dyeing colors meets the area ratio condition, and obtaining the target dyeing priority; or adjusting the initial dyeing priority according to the graphic projection overlapping length, until the projection overlapping length corresponding to graphics with different dyeing colors meets the preset projection overlapping length, and obtaining the target dyeing priority; adjusting the dyeing of each dyeing area map according to the target dyeing priority to obtain multiple target dyeing area maps.

[0085] It will be appreciated that an initial coloring priority may be assigned to each graphic according to a user's custom settings.

[0086] This can be evaluated based on the characteristics, size, shape, position, etc. of the graph, such as area, perimeter, shape complexity, etc. The initial coloring priority is set according to these properties, for example: the larger the area, the higher the priority.

[0087] As an example but not limitation, assume that there are three graphics A, B and C, with areas of 100, 50 and 150 respectively, then the initial coloring priority can be A: 1, B: 2, C: 1 (here it is assumed that the smaller the priority, the higher the coloring priority).

[0088] Combined with the graphic features (graphic area and / or graphic projection overlap length) mentioned above, adjust the priority. For example, if the coloring areas of some graphics differ too much and cause color conflicts, adjust the coloring priority of these graphics. Update the coloring of the graph according to the adjusted target coloring priority to ensure that the final color distribution is evenly distributed.

[0089] As an example but not a limitation, assume that the initial dyeing priority of graphic A is 1, and the corresponding dyeing color is red, the dyeing priority of graphic B is 2, and the corresponding dyeing color is blue, and the initial dyeing priority of graphic C is 1, and the corresponding dyeing color is red. By calculating the areas of these three graphics, it is found that the area of ​​the red area (250) is much larger than the area of ​​the blue area (50). At this time, the dyeing priority of graphic A can be adjusted to 2 (i.e., the target dyeing priority), so that the dyeing color corresponding to graphic A is adjusted to blue. After adjustment, the area of ​​the red area is 150, and the area of ​​the blue area is also 150, so that the final color distribution is evenly distributed.

[0090] Continuing with the above example, assuming that the overlapping length of the projections of Shape A and Shape B exceeds the preset range, resulting in a conflict in the dyeing colors, the dyeing priority of Shape A can be adjusted to 2 (i.e., the target dyeing priority), thereby adjusting the dyeing color corresponding to Shape A to blue, so that the final color distribution is evenly distributed.

[0091] The specific adjustment method can be selected according to the actual situation and is not limited here.

[0092] Combine the following Figure 2 and Figure 3 To compare and introduce the dyeing effects of different dyeing priorities.

[0093] Figure 2 It is a dyeing effect diagram corresponding to dyeing according to the initial dyeing priority provided in an embodiment of the present application.

[0094] like Figure 2 As shown, there is a problem with the dyeing effect after dyeing according to the initial dyeing priority, that is, the area of ​​the pink area is too different from the area of ​​the purple area.

[0095] Figure 3 It is a dyeing effect diagram corresponding to dyeing according to the target dyeing priority provided in an embodiment of the present application.

[0096] like Figure 3 As shown, Figure 2 The dyeing priority corresponding to the pink area in the first row is adjusted so that the dyeing color of the area turns purple.

[0097] Will Figure 2The dyeing priority of the purple area in the first row is adjusted so that the dyeing color of the area becomes pink. After the adjustment, the dyeing areas corresponding to the pink area and the purple area are basically evenly distributed.

[0098] It can be understood that the priority adjustment here is to adjust the color of the dyed area again after dyeing according to the initial dyeing priority by checking whether the area of ​​the dyed graphic is uniform and whether the overlapping length of the dyed graphic projection is within the preset range, so as to avoid color conflicts in some areas after dyeing, so that the final color distribution is evenly distributed.

[0099] In one implementation, after coloring multiple graphics in multiple partition area graphs according to a graph coloring algorithm to obtain a colored area graph, the method further includes: determining edge weights of each edge corresponding to the multiple partition area graphs, the edge weight being positively correlated with the closest distance from an edge of a graphic in one partition area graph to an edge of a graphic in an adjacent partition area graph; obtaining an order of edge weights of each edge corresponding to the multiple partition area graphs; the edge weight order is used to represent the order of the edge weights of each edge of each partition area graph.

[0100] Edge weight refers to the value on the edge connecting two nodes (vertices), which is usually used to represent the distance between the two points.

[0101] As an example and not limitation, edge weights may be determined based on multiple factors, such as the area, shape complexity, location, and neighboring relationships with other regions of a region.

[0102] For example, the edge weight is correlated with the distance between each partition region graph and the adjacent partition region graph. The closer the distance between two partition region graphs, the higher (or lower) weight is assigned to the edge formed by the two partition region graphs.

[0103] As an example but not a limitation, assume that the edge weights of region graphs A, B, C, and D are:

[0104] A:3; B:1; C:4; D:2;

[0105] Then the edge weight order can be B(1) <D(2)<A(3)<C(4)。

[0106] It can be understood that the edge weight is used to determine the relative importance of each area map so that adjacent areas can be processed in a specific order. It is determined whether the ratio between the colored areas corresponding to the graphics with different colored colors in two adjacent divided area maps meets the area ratio condition; when the ratio between the colored areas corresponding to the graphics with different colored colors in two adjacent divided area maps does not meet the area ratio condition, the colored color corresponding to at least one of the two adjacent divided area maps is flipped to obtain a flipped divided area map; the adjacent flipped divided area maps are merged in order from small to large according to the edge weight sequence to obtain a merged divided area map.

[0107] The main goal of this step is to avoid color conflicts between adjacent regions by optimizing the dyeing results again after the dyeing region map is completed (it can also be understood as avoiding uneven dyeing areas of dyeing graphs of adjacent regions).

[0108] According to the edge weight order in the region map, starting from the edge with the smallest distance, the adjacent regions are gradually merged. When merging, the two region maps are flipped as a whole. The purpose of flipping is to make the area ratios of the polygons allocated to the two masks (i.e., the chip splitting map mentioned above) close.

[0109] It can be understood that the purpose of flipping is mainly to make the proportions of the areas of the graphics with different dyeing colors in the two adjacent divided area maps closer. When flipping, you can choose one of the divided area maps to flip, or you can choose to flip both divided area maps at the same time. The specific flipping graphics can be determined based on actual conditions and are not limited here.

[0110] That is to say, if it is found that the area of ​​the graphics split into two masks is too different, the color of the graphics can be flipped. For example, if the area of ​​the red area is much larger than the area of ​​the blue area, the color of the red area of ​​the appropriate area can be changed to blue, so that the areas corresponding to the two colors are basically equal.

[0111] In one implementation, the method further includes: performing a global consistency check on the merged partitioned area map to determine whether there is a graphic conflict area; if there is a graphic conflict area, processing the graphic conflict area using a preset global optimization algorithm to correct the color corresponding to the graphic conflict area.

[0112] This step ensures that the merged partitioned region map has uniform color overall and no areas of coloring conflicts. Even after local optimization or flipping, there may still be invisible conflicts (for example, due to complex region shapes), which can be identified and further processed by this check.

[0113] The preset global optimization algorithm may include an integer linear programming algorithm, a heuristic optimization algorithm, etc. The specific algorithm principle can refer to the relevant technical principle, which will not be described here.

[0114] Assume that after a global consistency check of the merged partitioned region graph, it is found that there are conflicting regions in the merged graph, such as: region X (red) and region Y (red) are adjacent, but region Z (blue) is very close. By using a global optimization algorithm, the above regions can be adjusted, for example, the color of region Z can be adjusted from blue to red.

[0115] It can be understood that the specific color adjustment can be determined according to the actual situation. The dyeing method mentioned above can make the dyeing colors corresponding to the local areas evenly distributed, but there may be conflicts in the overall merge. By optimizing with the preset global optimization algorithm, the existing local conflicts can be resolved, making the overall dyeing result more uniform.

[0116] It can also be understood that after all regions are merged, a global consistency check is performed on the entire layout to ensure that there are no graphic conflicts. If there are still a few conflicts or other design rule issues, a global optimization algorithm (such as integer linear programming or heuristic optimization) can be applied to further optimize the color assignment.

[0117] In one implementation, the chip layout is divided according to a preset division rule to obtain multiple division area maps, including: obtaining the distance between any two adjacent graphics in the chip layout; comparing the distance between any two adjacent graphics with the preset distance, and when the distance between any two adjacent graphics is less than the preset distance, it is determined that there is a conflict relationship between the two graphics; and dividing the two graphics in a conflict relationship into different areas to obtain multiple division area maps.

[0118] It can be understood that in the chip layout, each design element (such as resistors, capacitors, wires, etc.) can be regarded as a graphic. By calculating the distance between these graphics, their spatial relationship with each other can be evaluated.

[0119] For example, a geometric distance formula (such as Euclidean distance) is used to calculate the shortest distance between various graphs.

[0120] It is understood that a minimum safe spacing between graphics is usually specified to ensure reliability and effectiveness during the manufacturing process. For example, a certain safe distance needs to be maintained between circuit components to prevent short circuits or signal interference. For each pair of graphics A and B, the actual distance D between them is checked. If D is less than the preset distance T, they are considered to be in conflict.

[0121] If the distance between the two is detected to be less than the preset distance, it means that their design does not comply with the rules and may cause manufacturing or performance problems. In this case, these graphics need to be considered as conflicting graphics.

[0122] By identifying the conflicting relationships between graphics, designers can proactively avoid potential problems during the design process, ensuring good circuit performance and higher manufacturing quality. Separating different conflicting graphics into different areas can help better adjust and optimize in subsequent processing (such as layout optimization) to avoid interference between them.

[0123] Assume that in the chip design layout, there are the following graphics (A, B, C, D) and the distances between them: the distance between graphic A and graphic B is 3 units; the distance between graphic A and graphic C is 5 units; the distance between graphic B and graphic C is 2 units; the distance between graphic D and other graphics is greater than the preset distance of 5 units; the preset distance T is 4 units.

[0124] It is detected that the distance between A and B (3 units) and the distance between B and C (2 units) are both less than 4 units.

[0125] Conflict relationship identification: A conflicts with B; B conflicts with C; the distance between A and C (5 units) does not touch the preset, so there is no conflict.

[0126] Divide the conflicting areas (A, B, C) into different zones. For example, A may be placed in zone 1, B in zone 2, and C in zone 3. D can exist independently in other zones.

[0127] Through these steps, graphic areas with potential problems can be quickly identified and potential problems can be avoided. In other words, discovering and eliminating conflicting relationships in the early stage of the design phase can save subsequent modification work and reduce costs and risks. Separating conflicting graphics in the early stage can more easily avoid problems and ensure logical rationality in subsequent layout optimization, color filling or other design adjustments. Ultimately, the reliability of the circuit is improved, the failure rate is reduced, and it is easier to meet the technical regulations in the manufacturing process.

[0128] In one implementation, multiple graphics with conflicting relationships are divided into different areas to obtain multiple divided area graphs, including: simplifying different areas into nodes to obtain multiple nodes; connecting multiple nodes with edges to obtain multiple divided area graphs.

[0129] Simplify different regions into nodes. The purpose of this step is to abstract the complex region representation into several key nodes to simplify subsequent processing.

[0130] A node represents a collection of graphics in an area and can be defined by location and attributes (such as color, type, etc.).

[0131] Combine the following Figure 4 To explain in detail.

[0132] Figure 4 It is a schematic diagram of layout division provided in an embodiment of the present application.

[0133] like Figure 4 As shown, suppose there are n regions (region 1, region 2, ..., region n), each containing different graphs. After simplification, we can simplify these regions into nodes N1, N2, ..., Nn, where N1 represents the set of all graphs in region 1, N2 represents the set of all graphs in region 2, ..., Nn represents the set of all graphs in region n.

[0134] Use edges to connect multiple nodes to represent the relationship between regions. For example, a node may be connected to its adjacent nodes (indicating that they are close to each other or have functional connections) through edges.

[0135] As an example and not a limitation, assume that edge E1 connects N1 and N2.

[0136] The simplified node graph can be used for fast calculation, optimization and other algorithms to save processing time and improve processing efficiency.

[0137] In summary, before the map is split, it is first divided into different areas according to the conflict relationship. There is no conflict relationship between polygons in different areas. First, the color is assigned to each area using an algorithm and all conflicts are resolved. Then it is expanded to the entire map.

[0138] When assigning colors to each area, in order to achieve uniform area, not only the different priorities set by the user are taken into consideration, but also the projection overlap length and area factors between conflicting polygons are used to correct the priorities in order to obtain a more uniform area result.

[0139] Based on the principle that the area ratio of the two masks is equal, the staining results on different areas are flipped to further optimize the results.

[0140] Through the above method, the graphic conflict between the two mask layers can be effectively reduced. This reduces short circuits, open circuits or other defects that may occur during the manufacturing process, thereby significantly improving the manufacturing yield. The graphic density on each mask layer is more uniform, which helps to balance the exposure energy distribution during the photolithography process and reduce graphic deformation and errors caused by uneven energy. In subsequent processes (such as etching and polishing), each mask layer can be executed more stably, thereby reducing the impact of process fluctuations and improving production consistency. In addition, this method can reduce the manual corrections required due to rule conflicts on the basis of better meeting design rules. This can speed up the design verification process and reduce the design cycle.

[0141] Based on the chip layout processing method provided in the above embodiment, the present application also provides a specific implementation of a chip layout processing device. Please refer to the following embodiment.

[0142] Figure 5 It is a structural schematic diagram of a chip layout processing device provided in an embodiment of the present application.

[0143] See first Figure 5 The chip layout processing device provided in the embodiment of the present application includes the following modules:

[0144] The acquisition module 1001 is used to acquire a chip layout, where the chip layout includes a plurality of graphics.

[0145] The partitioning module 1002 is used to partition the chip layout according to a preset partitioning rule to obtain a plurality of partitioning area maps. The preset partitioning rule is used to ensure that the graphics in each partitioning area map do not conflict with any graphics in an adjacent partitioning area map.

[0146] The coloring module 1003 is used to color each graph in each divided area graph according to a graph coloring algorithm to obtain a colored area graph. The graph coloring algorithm is used to make the graphics with conflicting relationships have different coloring colors.

[0147] The acquisition module 1001 is also used to acquire the graphic features of each graphic.

[0148] The adjustment module 1004 is used to adjust the coloring of each coloring area map according to the graphic features of each graphic, and obtain multiple target coloring area maps, so that the ratio of the coloring areas of graphics with different coloring colors in all target coloring area maps meets the area ratio condition.

[0149] The splitting module 1005 is used to split the graphics with different colors in each target staining area map into different chip splitting maps.

[0150] As an implementation method of the present application, the graphic features include at least one of the following: the graphic projection overlapping length and the graphic area; the adjustment module 1004 is also used to update each coloring area map according to the graphic features of each graphic to obtain multiple target coloring area maps, including: obtaining the coloring priority corresponding to each graphic in each divided area map to obtain an initial coloring priority, the coloring priority is used to determine the coloring color corresponding to each graphic, wherein graphics with different coloring priorities correspond to different coloring colors; adjusting the initial coloring priority according to the graphic area corresponding to each graphic until the ratio between the coloring areas corresponding to graphics with different coloring colors meets the area ratio condition to obtain the target coloring priority; or adjusting the initial coloring priority according to the graphic projection overlapping length until the projection overlapping length corresponding to graphics with different coloring colors meets the preset projection overlapping length to obtain the target coloring priority; adjusting each coloring area map according to the target coloring priority to obtain multiple target coloring area maps.

[0151] It can be understood that the priority adjustment here is to adjust the color of the dyed area again after dyeing according to the initial dyeing priority by checking whether the area of ​​the dyed graphic is uniform and whether the overlapping length of the dyed graphic projection is within the preset range, so as to avoid color conflicts in some areas after dyeing, so that the final color distribution is evenly distributed.

[0152] As an implementation of the present application, the above-mentioned device may also include: a flipping module, which is used to, after coloring multiple graphics in multiple partition area graphs according to a graph coloring algorithm to obtain a colored area graph, determine the edge weights of each edge corresponding to the multiple partition area graphs, and the edge weight is positively correlated with the closest distance from the edge of a graphic in a partition area graph to the edge of a graphic in an adjacent partition area graph; obtain the edge weight order of each edge corresponding to the multiple partition area graphs, the edge weight order is used to represent the size order of the edge weights of each edge of each partition area graph, and the edge weight is correlated with the distance between each partition area graph and the adjacent partition area graph; determine whether the ratio between the colored areas corresponding to graphics with different colored colors in two adjacent partition area graphs meets the area ratio condition; when the ratio between the colored areas corresponding to graphics with different colored colors in two adjacent partition area graphs does not meet the area ratio condition, flip the colored color of at least one partition area graph in the two adjacent partition area graphs to obtain a flipped partition area graph; merge the adjacent flipped partition area graphs in order from small to large according to the edge weight order to obtain a merged partition area graph.

[0153] The main goal of this step is to avoid color conflicts between adjacent regions by optimizing the dyeing results again after the dyeing region map is completed (it can also be understood as avoiding uneven dyeing areas of dyeing graphs of adjacent regions).

[0154] As an implementation method of the present application, the above-mentioned device may also include: an inspection module, which is used to perform a global consistency check on the merged divided area map to determine whether there is a graphic conflict area; if there is a graphic conflict area, the graphic conflict area is processed using a preset global optimization algorithm to correct the color corresponding to the graphic conflict area.

[0155] This step ensures that the merged partitioned region map has uniform color overall and no areas of coloring conflicts. Even after local optimization or flipping, there may still be invisible conflicts (for example, due to complex region shapes), which can be identified and further processed by this check.

[0156] As an implementation method of the present application, the division module 1002 is also used to divide the chip layout according to a preset division rule to obtain multiple division area maps, including: obtaining the distance between any two adjacent graphics in the chip layout; comparing the distance between any two adjacent graphics with the preset distance, and when the distance between any two adjacent graphics is less than the preset distance, it is determined that there is a conflict relationship between the two graphics; dividing the two graphics with a conflict relationship into different areas to obtain multiple division area maps.

[0157] By identifying the conflicting relationships between graphics, designers can proactively avoid potential problems during the design process, ensuring good circuit performance and higher manufacturing quality. Separating different conflicting graphics into different areas can help better adjust and optimize in subsequent processing (such as layout optimization) to avoid interference between them.

[0158] As an implementation method of the present application, the above-mentioned device may also include: a simplification module, which is used to divide multiple graphics with conflicting relationships into different areas to obtain multiple divided area graphs, including: simplifying different areas to simplify different areas into nodes to obtain multiple nodes; connecting multiple nodes with edges to obtain multiple divided area graphs.

[0159] Simplify different regions into nodes. The purpose of this step is to abstract the complex region representation into several key nodes to simplify subsequent processing.

[0160] Figure 6 It is a schematic diagram of the hardware structure of the chip layout processing device provided in the embodiment of the present application.

[0161] The chip layout processing device may include a processor 2001 and a memory 2002 storing computer program instructions.

[0162] Specifically, the processor 2001 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0163] The memory 2002 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 2002 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 2002 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 2002 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 2002 is a non-volatile solid-state memory.

[0164] In certain embodiments, the memory may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium device, an optical storage medium device, a flash memory device, an electrical, optical or other physical / tangible memory storage device. Thus, typically, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to a method according to an aspect of the present disclosure.

[0165] The processor 2001 implements any one of the chip layout processing methods in the above embodiments by reading and executing computer program instructions stored in the memory 2002 .

[0166] In one example, the chip layout processing device may further include a communication interface 2003 and a bus 2000. Figure 6 As shown, the processor 2001, the memory 2002, and the communication interface 2003 are connected via a bus 2000 and communicate with each other.

[0167] The communication interface 2003 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0168] Bus 2000 includes hardware, software or both, and the parts of online data flow billing equipment are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front-end bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 2000 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the present application considers any suitable bus or interconnection.

[0169] In addition, in combination with the chip layout processing method in the above embodiment, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any chip layout processing method in the above embodiment is implemented.

[0170] An embodiment of the present application also provides a computer program product, including a computer program, which, when executed, implements any one of the chip layout processing methods in the above embodiments.

[0171] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0172] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0173] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0174] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0175] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A chip layout processing method, characterized in that: include: Acquire a chip layout, wherein the chip layout includes a plurality of graphics; The chip layout is divided according to a preset division rule to obtain a plurality of division area maps, wherein the preset division rule is used to ensure that the graphics in each of the division area maps do not conflict with any graphics in the adjacent division area maps; Coloring each graph in each of the divided region graphs according to a graph coloring algorithm to obtain a colored region graph, wherein the graph coloring algorithm is used to make the graphics in conflicting relationships in each of the divided region graphs have different coloring colors; Get the graphic features of each graphic; According to the graphic features of each of the graphics, the coloring of each of the coloring region maps is adjusted to obtain a plurality of target coloring region maps, so that the ratio of the coloring areas of graphics with different coloring colors in all of the target coloring region maps satisfies an area ratio condition; The graphics with different colors in each of the target staining area maps are respectively split into different chip split maps.

2. The method according to claim 1, characterized in that The graphic features include at least one of the following: graphic projection overlap length and graphic area; The step of adjusting each of the dyeing region maps according to the graphic features of each graphic to obtain a plurality of target dyeing region maps includes: Obtaining the coloring priority corresponding to each graphic in each of the divided area graphs to obtain an initial coloring priority, wherein the coloring priority is used to determine the coloring color corresponding to each graphic, wherein graphics with different coloring priorities correspond to different coloring colors; The initial coloring priority is adjusted according to the graphic areas corresponding to the various graphics, until the ratio between the coloring areas corresponding to the graphics with different coloring colors meets the area ratio condition, thereby obtaining the target coloring priority; or, The initial coloring priority is adjusted according to the overlapping length of the graphic projections until the overlapping lengths of the projections corresponding to the graphics of different coloring colors meet the preset overlapping lengths of the projections, thereby obtaining the target coloring priority; The coloring of each of the coloring area maps is adjusted according to the target coloring priority to obtain a plurality of target coloring area maps.

3. The method according to claim 2, characterized in that After coloring the multiple graphs in the multiple divided region graphs according to the graph coloring algorithm to obtain the colored region graphs, the method further includes: Determine the edge weight of each edge corresponding to the plurality of divided area graphs, wherein the edge weight is positively correlated with the shortest distance from an edge of a graph in one of the divided area graphs to an edge of a graph in an adjacent divided area graph; Obtaining an edge weight sequence of each edge corresponding to the plurality of partitioned area graphs, wherein the edge weight sequence is used to represent a size sequence of edge weights of each edge of each of the partitioned area graphs; Determine whether the ratio between the colored areas corresponding to the graphics with different colored colors in two adjacent divided area graphs meets the area ratio condition; When the ratio between the colored areas corresponding to the graphics with different colored colors in the two adjacent divided area maps does not meet the area ratio condition, the colored color corresponding to at least one of the two adjacent divided area maps is flipped to obtain a flipped divided area map; The adjacent flipped partitioned region graphs are merged in order from small to large according to the edge weight sequence to obtain a merged partitioned region graph.

4. The method according to claim 3, characterized in that The method further comprises: Performing a global consistency check on the merged partitioned area graph to determine whether there is a graphic conflict area; In the case where the graphic conflict area exists, the graphic conflict area is processed using a preset global optimization algorithm to correct the color corresponding to the graphic conflict area.

5. The method according to any one of claims 1 to 4, characterized in that The chip layout is divided according to a preset division rule to obtain a plurality of division area maps, including: Obtaining the distance between any two adjacent graphics in the chip layout; Comparing the distance between any two adjacent graphics with a preset distance, and if the distance between any two adjacent graphics is less than the preset distance, determining that there is a conflict relationship between the two graphics; The two graphics having a conflicting relationship are divided into different regions to obtain the multiple divided region graphs.

6. The method according to claim 5, characterized in that The step of dividing the plurality of graphics having conflicting relationships into different regions to obtain the plurality of divided region graphs includes: Simplifying the different regions into nodes to obtain a plurality of nodes; The multiple nodes are connected by edges to obtain the multiple partitioned area graphs.

7. A chip layout processing device, characterized in that: The device comprises: An acquisition module, used for acquiring a chip layout, wherein the chip layout includes a plurality of graphics; A partitioning module, used for partitioning the chip layout according to a preset partitioning rule to obtain a plurality of partitioning area maps, wherein the preset partitioning rule is used to ensure that the graphics in each of the partitioning area maps do not conflict with any graphics in the adjacent partitioning area maps; A coloring module, used for coloring each graph in each of the divided area graphs according to a graph coloring algorithm to obtain a colored area graph, wherein the graph coloring algorithm is used for making the graphics in conflicting relationships in each of the divided area graphs have different coloring colors; The acquisition module is also used to acquire the graphic features of each graphic; An adjustment module, for adjusting the coloring of each of the coloring region maps according to the graphic features of each of the graphics, to obtain a plurality of target coloring region maps, so that the ratio of the coloring areas of graphics with different coloring colors in all of the target coloring region maps satisfies an area ratio condition; The splitting module is used to split the graphics with different colors in each of the target staining area maps into different chip splitting maps.

8. A chip layout processing device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the method according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the method according to any one of claims 1 to 6.

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