Method for constructing multi-module clock tree and clock tree synthesis device
By generating an initial clock tree for each module in a multi-modular chip design and building a formal clock tree according to the clock length classification, the clock signal delay matching problem is solved, and chip performance and design efficiency are improved.
Patent Information
- Application Number
- CN202411546291.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-03-11
AI Technical Summary
In a chip design with a multi-modular structure, due to inconsistent path delays of the clock signal, there is a delay matching problem when the same clock signal spans multiple modules, affecting chip performance.
Each module automatically generates an initial clock tree and classifies the clock lengths of the target module and the secondary module to build a formal clock tree so that the clock signal has the same clock length between the target module and its secondary module, thereby eliminating the delay matching problem.
It realizes the elimination of clock signal delay matching problems in a multi-module structure, improves chip performance, and improves the design efficiency of large-scale integrated circuits.
Smart Images
Figure CN119598953A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of clock tree synthesis, and in particular to a method for constructing a multi-module clock tree and a clock tree synthesis device applicable to EDA tools. Background Art
[0002] Currently, most chips are designed in a modular way, and the design of the chip clock tree is a key link in the design of multi-modular chips. In an ideal circuit, it can be assumed that the clock edges of all registers in the clock domain arrive at the same time, and there is no delay matching problem when the same clock signal crosses many modules.
[0003] Clock tree synthesis (CTS) is an important step in electronic design automation (EDA), which refers to the process of creating a clock distribution network for distributing clock signals to a collection of sequential circuit elements in a circuit design. The quality of the clock tree generated by CTS can have a significant impact on downstream steps in the EDA design flow.
[0004] However, in the actual chip clock tree, due to the clock tree structure, on-chip process errors and other reasons, the path delay of the clock signal to each register will be different, resulting in different arrival times of the clock signal. The registers will naturally not flip at the same time, so there will be a delay matching problem when the same clock signal crosses many modules, which will lead to reduced chip performance. Summary of the invention
[0005] In view of the above problems, the present invention proposes a method for constructing a multi-module clock tree and a clock tree synthesis device.
[0006] An embodiment of the present invention provides a method for constructing a multi-module clock tree, the method comprising:
[0007] Step S1: Each module generates an initial clock tree;
[0008] Step S2: determining the clock length of the target module and the clock length of the secondary module according to the clock tree of the target module and the clock tree of the secondary module of the target module;
[0009] Step S3: classifying the clock port sent from the target module to the secondary module according to the size relationship between the clock length of the target module and the clock length of the secondary module;
[0010] Step S4: constructing a formal clock tree of the target module based on the classified clock ports, and uploading the clock length corresponding to the formal clock tree to the high-level module of the target module;
[0011] Step S5: Taking the high-level module as the new target module, iteratively execute steps S2 to S4 until the formal clock tree of the highest-level module is obtained. The highest-level module is a clock signal generating module, and the formal clock tree of the highest-level module is taken as the final clock tree of the multiple modules.
[0012] Optionally, classifying the clock port sent from the target module to the secondary module according to the size relationship between the clock length of the target module and the clock length of the secondary module includes:
[0013] If the clock length of the target module is greater than the clock length of the secondary module, the clock port sent from the target module to the secondary module is set in the first-level clock tree of the target module;
[0014] If the clock length of the target module is smaller than the clock length of the secondary module, the clock port from the target module to the secondary module is set in the second-level clock tree of the target module.
[0015] Optionally, the secondary module includes: a first secondary module and a second secondary module; and according to the size relationship between the clock length of the target module and the clock length of the secondary module, the clock port sent from the target module to the secondary module is classified, including:
[0016] If the clock length of the target module is greater than the clock length of the first secondary module, the clock port sent from the target module to the first secondary module is set in the first-level clock tree of the target module;
[0017] If the clock length of the target module is smaller than the clock length of the second-level module, the clock port sent from the target module to the second-level module is set in the second-level clock tree of the target module;
[0018] Wherein, the first-level clock tree of the target module connects the internal trigger of the target module and the clock port of the target module sent to the first-level module;
[0019] The first-level clock tree source point of the target module serves as the sinking point of the second-level clock tree of the target module, and the second-level clock tree of the target module connects the clock port of the target module to the second-level module.
[0020] Optionally, the second-level clock tree of the target module is located between a target clock port and an initial clock tree of the target module, and the target port is a clock port sent from the high-level module to the target module.
[0021] Optionally, constructing a formal clock tree of the target module based on the classified clock ports includes:
[0022] Performing timing processing on each type of the classified clock ports so that the clock length of the clock signal reaching the internal trigger of the target module is the same as the clock length of the clock signal reaching the internal trigger of the secondary module, thereby constructing a formal clock tree of the target module;
[0023] Among them, the timing processing includes: setting the relative delay relationship between the clock port sent by the target module to the secondary module and the source point of the first-level clock tree in the multi-level clock tree, or setting a clock buffer unit before and after the source point of the first-level clock tree, or modifying the connection relationship between the clock port sent by the target module to the secondary module and the first clock tree.
[0024] Optionally, constructing a formal clock tree of the target module based on the classified clock ports includes:
[0025] Modify the connection relationship between the clock port sent from the target module to the first secondary module and the first clock tree, so that the clock length of the clock signal reaching the clock port sent from the target module to the first secondary module is longer than the clock length of the clock signal reaching the source point of the first clock tree by a first target length, thereby constructing a formal clock tree of the target module, and the first target length is the clock length of the first secondary module;
[0026] A relative delay relationship is set between the clock port sent from the target module to the second-level module and the source point of the first-level clock tree, or a clock buffer unit is set before and after the source point of the first-level clock tree, so that the clock length of the clock signal reaching the clock port sent from the target module to the second-level module is longer than the clock length of the clock signal reaching the source point of the first clock tree by a second target length, thereby constructing a formal clock tree of the target module, and the second target length is the difference between the clock length of the first-level module and the clock length of the target module.
[0027] Optionally, the secondary module further includes: a third secondary module; classifying the clock port sent from the target module to the secondary module according to the size relationship between the clock length of the target module and the clock length of the secondary module, including:
[0028] If the clock length of the target module is smaller than the clock length of the second-level module and the clock length of the third-level module, and the difference between the clock length of the second-level module and the clock length of the third-level module is smaller than a preset value, the clock port of the target module sent to the second-level module and the third-level module is set in the second-level clock tree of the target module;
[0029] If the clock length of the target module is less than the clock length of the second-level module and the clock length of the third-level module, and the difference between the clock length of the second-level module and the clock length of the third-level module is not less than the preset value, the clock port sent from the target module to the second-level module is set in the second-level clock tree of the target module, and the clock port sent from the target module to the third-level module is set in the third-level clock tree of the target module;
[0030] Among them, the second-level clock tree source point of the target module serves as the sinking point of the third-level clock tree of the target module, and the third-level clock tree of the target module connects the clock port of the target module to the third-level module.
[0031] Optionally, constructing a formal clock tree of the target module based on the classified clock ports includes:
[0032] A relative delay relationship is set between the clock port sent by the target module to the third-level module and the source point of the second-level clock tree, or a clock buffer unit is set before and after the source point of the second-level clock tree, so that the clock length of the clock signal reaching the clock port sent by the target module to the third-level module is longer than the clock length of the clock signal reaching the source point of the first clock tree by a third target length, thereby constructing a formal clock tree of the target module, and the third target length is the difference between the clock length of the third-level module and the clock length of the target module.
[0033] Optionally, constructing a formal clock tree of the target module includes:
[0034] The clock port sent from the high-level module to the target module is constructed by using an H-tree, binary tree or clock grid structure, and combining the first-level clock tree and the second-level clock tree to construct a formal clock tree of the target module.
[0035] An embodiment of the present invention provides a clock tree synthesis device, which is applied to an EDA tool. The device can be configured as follows:
[0036] A receiving circuit design, wherein the circuit design includes a plurality of modules;
[0037] Build an initial clock tree for each module and determine the clock length of the module;
[0038] For all the secondary modules of the target module, the clock ports of the secondary modules with a larger clock length than the target module are set in the first-level clock tree of the circuit design, and the clock ports of the secondary modules with a smaller clock length than the target module are set in the second-level clock tree of the circuit design, so as to construct a formal clock tree of the target module and its secondary modules; wherein the second-level clock tree is a higher-level clock tree of the first-level clock tree in the circuit design; and the clock signal in the circuit design is propagated from the target module to the secondary modules via the clock port.
[0039] An embodiment of the present invention provides a computer program product for EDA, comprising computer executable instructions, which, when executed by a processor, enable the computer to:
[0040] Provides a user interface for clock tree synthesis; and
[0041] In response to the operation of the user interface, the following clock tree synthesis operations are performed:
[0042] A receiving circuit design, wherein the circuit design includes a plurality of modules;
[0043] Build an initial clock tree for each module and determine the clock length for that module; and
[0044] For all the secondary modules of the target module, the clock ports of the secondary modules whose clock lengths are greater than the clock length of the target module are set in the first-level clock tree of the circuit design, and the clock ports of the secondary modules whose clock lengths are less than the clock length of the current module are set in the second-level clock tree of the circuit design, so as to construct a formal clock tree of the target module and its secondary modules;
[0045] The second-level clock tree is a higher-level clock tree of the first-level clock tree in the circuit design; the clock signal in the circuit design is propagated from the target module to the secondary module via the clock port.
[0046] The method for constructing a multi-module clock tree provided by the present invention first generates an initial clock tree for each module; then determines the clock length of the target module and the clock length of the secondary module according to the clock tree of the target module and the clock tree of the secondary module of the target module.
[0047] Then, according to the size relationship between the clock length of the target module and the clock length of the secondary module, the clock port sent from the target module to the secondary module is classified; based on the classified clock port, the formal clock tree of the target module is constructed, and the clock length corresponding to the formal clock tree is uploaded to the high-level module of the target module; finally, the high-level module is used as the new target module, and the steps of comparing the size relationship between the clock lengths, classifying the clock ports, and constructing the formal clock tree are iteratively executed until the formal clock tree of the clock signal generating module is obtained, and the formal clock tree is used as the final clock tree of multiple modules, that is, the final clock tree of the chip.
[0048] The present invention aims at the problem of delay matching between multiple modules when the same clock signal crosses in the above-mentioned traditional clock tree design, and creatively proposes a clock tree construction method. By exchanging clock length data between the target module and its secondary modules, the clock ports are classified and the formal clock tree of the target module is constructed based on this, so that the same clock signal has the same clock length when crossing the target module and its secondary modules, thereby eliminating the delay matching between the target module and its secondary modules.
[0049] After the target module generates a formal clock tree, its clock length is uploaded to the high-level module of the target module, so that the high-level module is used as a new target module to iteratively execute the steps of comparing the size relationship between clock lengths, classifying clock ports, and building a formal clock tree until the formal clock tree of the clock signal generation module is obtained. This eliminates the problem of delay matching between the same clock signal across many modules in the entire chip.
[0050] In addition, since the clock tree is generated and adjusted step by step from the bottom module, it does not rely on top-level regulation. Any module can negotiate with adjacent modules (generally, the adjacent modules may be the target module and its secondary module, or two modules with the same clock length) and simultaneously generate the clock tree. Not only can the overall longest path (that is, the longest clock length) be uploaded from the bottom module to the high-level module step by step, but the modules at all levels can be optimized for the path, which is conducive to reducing the overall clock length and improving the design efficiency of large-scale integrated circuits. And the common clock path between adjacent modules is retained to the maximum extent, which is conducive to overall timing convergence. The method proposed in the present invention has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0052] Figure 1is a flow chart of a method for constructing a multi-module clock tree according to an embodiment of the present invention;
[0053] Figure 2 is a schematic diagram of an exemplary module layout and its clock propagation relationship in an embodiment of the present invention;
[0054] Figure 3 is an exemplary clock length of module B, module D and module F in the embodiment of the present invention;
[0055] Figure 4 It is a schematic diagram of clock length of an exemplary target module B and its secondary modules D and F formal clock trees in an embodiment of the present invention. DETAILED DESCRIPTION
[0056] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, are only part of the embodiments of the present invention, not all of the embodiments, and are not used to limit the present invention.
[0057] The EDA (Electronic Design Automation) process can be used to create a circuit design. Once the circuit design is completed, it can be manufactured, packaged, and assembled to produce an integrated circuit chip. The EDA process can include multiple steps, and each step can involve the use of one or more EDA software tools. Clock tree synthesis (CTS) is an important step in circuit design, and its goal is to create an optimal clock tree. EDA tools usually provide a circuit design user interface, including a clock tree synthesis interface, which can receive or read the circuit design and user operations, and perform clock tree synthesis according to user operations or automatically.
[0058] The inventors found that the traditional chip clock tree design has a delay matching problem when the same clock signal crosses many modules. The so-called clock tree refers to the clock network on the chip, which enables the clock signal to be transmitted to various timing devices, such as registers.
[0059] The inventors further studied and found that the cause of the above problem is the existence of clock deviation. In an ideal synchronous circuit, it can be assumed that the clock edges of all registers in the clock domain arrive at the same time, but in the actual clock tree, due to the different path delays from the clock to each register, the clock signal arrives at different times, and the registers will not flip at the same time.
[0060] In the process of gate-level circuit design, in order to obtain an optimal circuit design, it is necessary to check the maximum delay of the gate-level circuit to ensure that the circuit can meet the requirements of the setup time at the specified frequency, and at the same time check the minimum delay of the gate-level circuit to meet the requirements of the hold time. This test is called static timing analysis (STA), which is a relatively thorough method to analyze, debug and confirm the timing performance of a gate-level system design. In other words, it is a key test indicator for the performance of the chip clock tree.
[0061] In large-scale high-performance integrated circuit design, the quality of the clock tree often directly affects the design performance of the integrated circuit, and the performance of the integrated circuit represents whether the designed circuit can complete more functional goals in less time. Designing a high-quality clock tree can undoubtedly effectively improve the performance of the integrated circuit. On the contrary, a low-quality clock tree will reduce the working efficiency of the overall circuit. Higher performance and better clock trees are always the goals pursued by integrated circuit designers. Clock deviation has always been an important parameter for measuring clock tree performance, which is affected by many factors, such as clock tree structure, on-chip process errors, etc.
[0062] The integrated circuit design of a chip can only be truly completed after passing static timing analysis. As for the problem of clock deviation, for example, when the clock of the emission trigger (one of the registers) arrives earlier than the clock of the sampling trigger (one of the registers), it will make it more difficult to meet the hold time of the corresponding path. Conversely, when the clock of the emission trigger arrives later than the clock of the sampling trigger, it will make it more difficult to meet the setup time of the corresponding path. These situations will lead to the degradation of clock tree performance, and indirectly lead to the degradation of chip performance.
[0063] At present, in order to solve the above problems, the existing solutions can be roughly divided into three categories:
[0064] The first category: obtaining multiple groups of synchronization unit groups with the same target clock source; each group of synchronization unit groups includes at least one synchronization unit; for each synchronization unit group, a virtual clock source is set on the end away from the target clock source on the common path from each synchronization unit in the synchronization unit group to the target clock source; using layout and routing tools to make the clock delay from each synchronization unit in the synchronization unit group to the virtual clock source equal.
[0065] The second category: Use EDA tools to complete the layout of top-level modules, logic units, and components; insert buffer units according to the distance of interconnect lines and create a clock tree between the top-level module and the top-level logic unit based on the clock propagation relationship between the top-level logic unit and the top-level module; use EDA software to replace the buffer units used to create the clock tree between the top-level module and the top-level logic unit with inverter units; first perform local routing on the clock tree between the top-level module and the top-level logic unit, and then use EDA software to complete the global clock tree synthesis and routing.
[0066] The third category: determine the design positions of multiple top-level clock ports and the top-level clock ports associated with each bottom-level module; wherein the top-level clock end is designed at the boundary of the bottom-level module, and the overlapping area of the effective coverage range corresponding to the design position of multiple top-level clock ports meets the preset overlapping conditions; according to the top-level clock ports associated with each bottom-level module, design the bottom-level clock tree in each bottom-level module; wherein the bottom-level clock tree of the bottom-level module is connected to the top-level clock tree of the top-level module through the associated top-level clock port.
[0067] Among the above solutions, the first type of solution only considers the situation of two-level hierarchy, that is, starting from the clock source, only one top-level module is needed to reach each trigger. However, in actual large-scale integrated circuit design, the clock signal often needs to pass through multiple modules after being generated from one module to reach a specific unit group. In this case, the use of the first type of solution will become complicated and will introduce additional workload. In addition, since there are many factors affecting the division of unit groups in large-scale integrated circuit design, such as IO position, voltage domain, area, etc., it is difficult to divide the synchronous unit group according to the designer's wishes, which may cause large deviations in the clock lengths between each unit group, making it difficult to retain the common path of the clock.
[0068] In the second type of solution, buffer units are inserted between the logic unit and the top-level module according to the distance of the interconnection line. This cannot ensure that the clock lengths between the top-level modules are consistent. If there is data interaction between two top-level modules and the clock deviation between the two modules is large, it will lead to difficulties in full chip timing convergence.
[0069] In the third type of solution, clock balancing is performed by determining the effective coverage of the top-level clock port. However, if the coverage of the top-level clock port cannot cover the effective range, the bottom-level clock delay will exceed the bottom-level clock delay required for balancing, thereby affecting timing convergence. In addition, if the effective coverage of the top-level clock port is too large or too small, it may cause problems in the efficiency of the integrated circuit.
[0070] In order to solve the above problems, the inventor has creatively proposed a method for constructing a multi-module clock tree and a clock tree integration device of the present invention after extensive research and testing. The technical solution of the present invention is explained and illustrated in detail below.
[0071] The method for constructing a multi-module clock tree of the present invention refers to Figure 1 The method flow chart shown comprises:
[0072] Step S1: Each module generates an initial clock tree.
[0073] In large-scale integrated circuit design, such as chip circuit design, due to the huge scale, the entire chip is often divided into multiple modules so that multiple designers can carry out the design in parallel, which will cause multiple different modules to be associated with the same clock signal. If each module is allowed to complete the clock tree design by itself, there will be deviations between the internal clock lengths of each module, resulting in the timing path in the clock domain between modules being unable to meet the high frequency requirements, ultimately causing the performance of the entire chip to degrade or even fail. The goal of the method proposed in the present invention is to make the lengths of the clock trees designed in different modules consistent.
[0074] In order to achieve the above objectives, each module needs to generate an initial clock tree. Figure 2 An exemplary module layout and its clock propagation relationship diagram is shown in FIG. The same clock signal propagated to all modules is generated by module A, used in module A and propagated to modules B, C and E, and propagated to modules F and D in module B. Figure 2 As shown, for module B, if it is regarded as the target module, then module D and module F are its subordinate modules, and module A is its superior module. Naturally, it can be understood that module A is the superior module of module C and module E, and modules B, C, and E are all subordinate modules of module A. It should be understood that "subordinate" and "superior" here do not refer to the circuit level, but the upstream or downstream of the clock signal propagation path. For the target module B, the clock signal propagates from module B to module D via the clock port of module D, and module B is the superior module of module D.
[0075] It should be noted that Figure 2The examples are only for the purpose of better understanding the method proposed in the present invention, and do not mean that the same clock signal can only be propagated in this form in multiple modules. For example, module C is an adjacent module of module A, but the clock signal generated by module A may be directly propagated to module C, or it may first pass through module B and then to module D before finally propagating to module C. In the latter propagation path, module C becomes a secondary module of module D, and is no longer a secondary module of module A; module F may be a propagation path from module A to module B and then to module F, or it may be a propagation path from module A to module E and then to module F. In the latter propagation path, module F is a secondary module of module E, and is no longer a secondary module of module B. The specific multi-module structure and its propagation path need to be determined according to the actual design requirements, and the determination of the natural target module and its secondary modules and high-level modules is also determined according to the actual propagation path.
[0076] The best method for each module to generate its own clock tree is to use a clock tree distribution topology such as an H-tree, a binary tree, or a clock grid structure to build its own internal clock tree from the input clock port or the clock generation source point. Figure 2 Taking the structure shown as an example, modules A to F each construct their own clock tree.
[0077] Step S2: Determine the clock length of the target module and the clock length of the secondary module according to the clock tree of the target module and the clock tree of the secondary module of the target module.
[0078] After each module generates its own clock tree, the clock length of the target module and the clock length of the secondary module are determined according to the clock tree of the target module and the clock tree of the secondary module of the target module. The target module is generally selected as the second-to-last module, that is, the penultimate module of the same clock signal propagation path. The secondary module of the target module is the last module of the same clock signal propagation path. Figure 2 Take the structure shown as an example: the target module is module B, and module D and module F are the last sequential modules. The advantage of this is that the clock tree length statistics are always passed from the secondary module to the high-level module, so each module can see the longest clock path in the current module and all its secondary modules, and optimize it in a targeted manner to reduce the overall clock tree length. In addition, each module has no effect on the clock tree generation of other modules except for the interaction of clock length data, so each module can carry out multiple rounds of clock tree generation and subsequent iterative optimization in parallel.
[0079] For a clearer understanding of this step, refer to Figure 3 An exemplary clock length of module B, module D and module F is shown. Figure 3From left to right, the clock lengths of module D, module B, and module F are represented respectively. Since each module is affected by its own design characteristics, such as trigger scale and distribution, layout planning, module shape, etc., the lengths of the clock trees obtained are often different, and their respective clock lengths are also different. It can be seen that the clock lengths of modules D, B, and F increase gradually, the clock length in module D is the shortest, and the clock length in module F is the longest. Assume that the internal clock lengths of modules B, D, and F are delay(B), delay(D), and delay(F) respectively. The time length from the clock source of each module to its internal trigger is the clock length of each module. For example, the time length from the clock source of module D to the internal trigger of module D is delay(D). The rest of the modules are similar and will not be described one by one. At this time, if the clock trees of modules B, D, and F are directly spliced, the clock deviation between modules B, D, and F will be large, making it difficult to meet the timing requirements.
[0080] The method proposed in the present invention does not directly combine the clock trees of modules B, D, and F, but determines the clock length of the target module B and the clock length of the secondary modules D and F according to the clock tree of the target module B and the clock trees of the secondary modules D and F of the target module B.
[0081] Step S3: Classify the clock ports sent from the target module to the secondary module according to the size relationship between the clock length of the target module and the clock length of the secondary module.
[0082] After determining the clock length of the target module B and the clock length of the secondary modules D and F, the clock ports (there are two, one is the clock port sent by the target module B to the secondary module D, and the other is the clock port sent by the target module B to the secondary module F) sent by the target module B to the secondary modules D and F are classified according to the size relationship between the clock length of the target module B and the clock length of the secondary modules D and F. A better classification method includes:
[0083] If the clock length of the target module B is greater than the clock length of the secondary modules D and F, the clock port sent from the target module B to the secondary modules D and F is set in the first-level clock tree of the target module B; if the clock length of the target module B is less than the clock length of the secondary modules D and F, the clock port sent from the target module B to the secondary modules D and F is set in the second-level clock tree of the target module. In the current circuit design, the second-level clock tree is a higher-level clock tree of the first-level clock tree. For example, in an H-type clock tree, the second-level clock tree is closer to the source node of the entire tree.
[0084] It should be noted that the above description is based on the example that the target module B has two secondary modules D and F. In practice, the target module B may have only one secondary module D or secondary module F, or may have multiple secondary modules D, F...N. In either case, as long as the clock length of the target module is greater than the clock length of the secondary module, the clock port sent from the target module to the secondary module is set in the first-level clock tree of the target module; if it is less than, the clock port sent from the target module to the secondary module is set in the second-level clock tree of the target module, thereby completing the classification of all clock ports.
[0085] Take module D as the first secondary module and module F as the second secondary module as an example: if the clock length of the target module B is greater than the clock length of the first secondary module D, the clock port sent from the target module B to the first secondary module D is set in the first-level clock tree of the target module B; if the clock length of the target module B is less than the clock length of the second secondary module F, the clock port sent from the target module B to the second secondary module F is set in the second-level clock tree of the target module B.
[0086] Among them, the first-level clock tree of target module B connects the internal trigger of target module B and the clock port sent by target module B to the first sub-module D; the source point of the first-level clock tree of target module B serves as the sinking point of the second-level clock tree of target module B, and the second-level clock tree of target module B connects the clock port sent by target module B to the second sub-module F. Figure 4 FIG. 1 is a schematic diagram of the clock length of an exemplary target module B and its secondary modules D and F formal clock trees. It can be seen that the first-level clock tree of the target module B connects the internal trigger of the target module B and the clock port of the target module B sent to the first secondary module D ( Figure 4 The source point of the first-level clock tree of the target module B is used as the sinking point of the second-level clock tree of the target module B (represented by the dot-dash line), and the second-level clock tree of the target module B connects the clock port sent by the target module B to the second-level module F ( Figure 4 The second-level clock tree of the target module B is located at the target clock port ( Figure 4 The target port is the clock port sent from the advanced module A to the target module B.
[0087] Step S4: constructing a formal clock tree of the target module based on the classified clock ports, and uploading the clock length corresponding to the formal clock tree to the high-level module of the target module.
[0088] After the clock ports are classified, the formal clock tree of the target module B is constructed based on the classified clock ports, and the clock length of the corresponding formal clock tree is uploaded to the advanced module A of the target module B. The construction of the formal clock tree of the target module B can still be completed using clock tree distribution topology structures such as H tree, binary tree or clock grid structure. The better methods for constructing the formal clock tree of the target module based on the classified clock ports include:
[0089] Performing timing processing on each type of the classified clock ports, so that the clock length of the clock signal reaching the internal trigger of the target module is the same as the clock length of the clock signal reaching the internal trigger of the secondary module, so as to construct a formal clock tree of the target module; wherein the timing processing includes: setting the relative delay relationship between the clock port sent from the target module to the secondary module and the source point of the first-level clock tree in the multi-level clock tree, or setting a clock buffer unit before and after the source point of the first-level clock tree, or modifying the connection relationship between the clock port sent from the target module to the secondary module and the first clock tree.
[0090] Take module D as the first secondary module and module F as the second secondary module as an example: modify the connection relationship between the clock port sent by target module B to the first secondary module D and the first clock tree ( Figure 4 The middle line T is the connection line between the modified module B and D clock ports and the first clock tree), so that the clock length of the clock signal reaching the clock port of the target module B to the first secondary module D is longer than the clock length of the clock signal reaching the source point of the first clock tree by the first target length, thereby constructing the formal clock tree of the target module. The so-called first target length is the clock length of the first secondary module D. That is, in order to achieve a balance between module B and module D in the first-level clock tree, it is necessary to perform special timing processing on the clock ports between modules B and D, that is, it is necessary to make the length of the clock signal reaching the module B and D clock ports longer than the length reaching the source point of the first-level clock tree by delay(D). At this time, since delay(B) is greater than delay(D), this requirement can be achieved by modifying the connection relationship between the module B and D clock ports and the first-level clock tree.
[0091] Set the relative delay relationship between the clock port sent from the target module B to the second-level module F and the source point of the first-level clock tree, or set clock buffer units before and after the source point of the first-level clock tree, so that the clock length of the clock signal reaching the clock port sent from the target module B to the second-level module F is longer than the clock length of the clock signal reaching the source point of the first clock tree by a second target length, thereby constructing the formal clock tree of the target module. The so-called second target length is the difference between the clock length of the first-level module F and the clock length of the target module B. That is: in order to achieve a balance between module B and module F in the second-level clock tree, special timing processing is required for the clock ports of modules B and F, that is, the length of the clock signal reaching the clock ports of modules B and F needs to be longer than the length reaching the source point of the first-level clock tree by delay(F)-delay(B). It can be combined Figure 4 The clock tree formed by such timing processing can achieve the same length of the clock trees of modules B, D, and F after splicing, that is, the clock duration of the clock signal from the clock source of module B to the internal trigger of module B, the internal trigger of module D, and the internal trigger of module F is consistent.
[0092] In addition, there is another case, assuming that there is a third submodule G( Figures 2 to 4 (shown in the figure), if the clock length of the target module B is less than the clock length of the second sub-module F and the clock length of the third sub-module G, and the difference between the clock length of the second sub-module F and the clock length of the third sub-module G is less than the preset value, the clock port of the target module B sent to the second sub-module F and the third sub-module F is set in the second-level clock tree of the target module; if the clock length of the target module B is less than the clock length of the second sub-module F and the clock length of the third sub-module G, and the difference between the clock length of the second sub-module F and the clock length of the third sub-module F is not less than the preset value, the clock port of the target module B sent to the second sub-module F is set in the second-level clock tree of the target module, and the clock port of the target module B sent to the third sub-module G is set in the third-level clock tree of the target module B. The second-level clock tree source point of the target module B is used as the sinking point of the third-level clock tree of the target module B, and the third-level clock tree of the target module B connects the clock port of the target module B sent to the third sub-module G.
[0093] The reason for this design is that if the clock length of the third-level module G is not much different from that of the second-level module F, the second-level clock tree can be used to ensure that the same clock signal is propagated to its respective internal triggers with the same clock length. However, if the two are greatly different, using only the second-level clock tree may not be able to ensure that the same clock signal is propagated to its respective internal triggers with the same clock length. Therefore, a third-level clock tree needs to be added to meet this requirement. On the other hand, if the second-level clock tree is directly made with the clock length of the third-level module G and the clock length of the target module B, and the third-level clock tree is not added, then for the second-level module F and the first-level module D, too many clock buffer units need to be inserted, which is not conducive to layout and routing on the one hand, and also destroys the common clock path between module D and module B, and between module F and coal mine B on the other hand.
[0094] Similarly, since the clock length of module D is shorter than that of module B, it is not advisable to generate the clock port between modules B and D in the second-level clock tree. Otherwise, in order to balance with module F, the second-level clock tree will insert too many clock buffers before the internal trigger of module B and the internal trigger of module D. Similarly, on the one hand, it is not conducive to layout and routing, and on the other hand, it also destroys the common clock path between module D and module B.
[0095] In addition, when the target module has a large number of clock tree levels, for example, in order to meet the requirement of clock length consistency, the target module B needs to have a clock tree structure of four or more levels, which will also make the line structure complex to a certain extent. At this time, you can consider adjusting the propagation relationship of the clock signal, such as changing the clock signal of the third-level module G to the second-level module F or other modules such as module E for transmission. Of course, this modification of the propagation relationship needs to meet the modification requirements of the clock logic. In general, it is to achieve the consistency of the clock length of the same clock signal propagated to the internal triggers of each module on the basis of the target module having as few levels of clock tree structure as possible.
[0096] When the target module B needs to build a third-level clock tree, the relative delay relationship between the clock port sent by the target module B to the third-level module G and the source point of the second-level clock tree is set, or a clock buffer unit is set before and after the source point of the second-level clock tree, so that the clock length of the clock signal reaching the clock port sent by the target module B to the third-level module G is longer than the clock length of the clock signal reaching the source point of the first clock tree by a third target length, thereby building a formal clock tree of the target module. The so-called third target length is the difference between the clock length of the third-level module G (assuming it is delay(G)) and the clock length of the target module B: delay(G)-delay(B).
[0097] Step S5: Take the high-level module as the new target module, iteratively execute steps S2 to S4 until the formal clock tree of the highest-level module is obtained. The highest-level module is the clock signal generating module, and the formal clock tree of the highest-level module is taken as the final clock tree of multiple modules.
[0098] After the clock tree of target module B is constructed, its clock length is uploaded to the high-level module A of the target module. The high-level module A is used as the new target module, and steps S2 to S4 are iteratively executed until the formal clock tree of the highest-level module is obtained. The so-called highest-level module is the clock signal generation module. Figure 2 Taking the structure shown in the figure as an example, the highest level module is module A, and assuming that the clock signal module is module Z ( Figures 2 to 4 (as shown in the figure), the clock signal is propagated from module Z to module A, then the high-level module A is used as the new target module, and steps S2 to S4 are iteratively executed until the formal clock tree of the highest-level module Z is obtained, and the formal clock tree of the highest-level module Z is used as the final clock tree of the multi-module structure of the entire chip.
[0099] In an embodiment of the present invention, based on the above method for constructing a multi-module clock tree, a chip is also proposed, the chip comprising: multiple modules; the multiple modules adopt the method for constructing a multi-module clock tree as described in any one of the above steps S1 to S5 to construct the clock tree of the chip.
[0100] In summary, the method for constructing a multi-module clock tree of the present invention first generates an initial clock tree for each module; then, based on the clock tree of the target module and the clock tree of the secondary module of the target module, the clock length of the target module and the clock length of the secondary module are determined.
[0101] Then, according to the size relationship between the clock length of the target module and the clock length of the secondary module, the clock port sent from the target module to the secondary module is classified; based on the classified clock port, the formal clock tree of the target module is constructed, and the clock length corresponding to the formal clock tree is uploaded to the high-level module of the target module; finally, the high-level module is used as the new target module, and the steps of comparing the size relationship between the clock lengths, classifying the clock ports, and constructing the formal clock tree are iteratively executed until the formal clock tree of the clock signal generating module is obtained, and the formal clock tree is used as the final clock tree of multiple modules, that is, the final clock tree of the chip.
[0102] The present invention aims at the problem of delay matching between multiple modules when the same clock signal crosses in the above-mentioned traditional clock tree design, and creatively proposes a clock tree construction method. By exchanging clock length data between the target module and its secondary modules, the clock ports are classified and the formal clock tree of the target module is constructed based on this, so that the same clock signal has the same clock length when crossing the target module and its secondary modules, thereby eliminating the delay matching between the target module and its secondary modules.
[0103] After the target module generates a formal clock tree, its clock length is uploaded to the high-level module of the target module, so that the high-level module is used as a new target module to iteratively execute the steps of comparing the size relationship between clock lengths, classifying clock ports, and building a formal clock tree until the formal clock tree of the clock signal generation module is obtained. This eliminates the problem of delay matching between the same clock signal across many modules in the entire chip.
[0104] The features of the above different embodiments may be combined and other embodiments may be omitted. For example, the present application also provides a clock tree synthesis device, which is applied to EDA tools and can be configured as follows:
[0105] A receiving circuit design, wherein the circuit design includes a plurality of modules;
[0106] Build an initial clock tree for each module and determine the clock length of the module;
[0107] For all the secondary modules of the target module, the clock ports of the secondary modules whose clock lengths are greater than the clock length of the target module are set in the first-level clock tree of the circuit design, and the clock ports of the secondary modules whose clock lengths are less than the clock length of the current module are set in the second-level clock tree of the circuit design, so as to construct a formal clock tree of the target module and its secondary modules; wherein the second-level clock tree is a higher-level clock tree of the first-level clock tree in the circuit design; and the clock signal in the circuit design is propagated from the target module to the secondary modules via the clock ports.
[0108] The present application also provides a computer program product for EDA, comprising computer executable instructions, which, when executed by a processor, enable a computer to:
[0109] Provides a user interface for clock tree synthesis; and
[0110] In response to the operation of the user interface, the following clock tree synthesis operations are performed:
[0111] A receiving circuit design, wherein the circuit design includes a plurality of modules;
[0112] Build an initial clock tree for each module and determine the clock length for that module; and
[0113] For all the secondary modules of the target module, the clock ports of the secondary modules whose clock lengths are greater than the clock length of the target module are set in the first-level clock tree of the circuit design, and the clock ports of the secondary modules whose clock lengths are less than the clock length of the current module are set in the second-level clock tree of the circuit design, so as to construct a formal clock tree of the target module and its secondary modules;
[0114] The second-level clock tree is a higher-level clock tree of the first-level clock tree in the circuit design; the clock signal in the circuit design is propagated from the target module to the secondary module via the clock port.
[0115] In addition, since the clock tree is generated and adjusted step by step from the bottom module, it does not rely on top-level regulation. Any module can negotiate with adjacent modules (generally, the adjacent modules may be the target module and its secondary module, or two modules with the same clock length) and simultaneously generate the clock tree. Not only can the overall longest path (that is, the longest clock length) be uploaded from the bottom module to the high-level module step by step, but the modules at all levels can be optimized for the path, which is conducive to reducing the overall clock length and improving the design efficiency of large-scale integrated circuits. And the common clock path between adjacent modules is retained to the maximum extent, which is conducive to overall timing convergence. The method proposed in the present invention has high practicality.
[0116] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.
[0117] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.
[0118] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.
Claims
1. A method for constructing a multi-module clock tree, characterized in that: The method comprises: Step S1: Each module generates an initial clock tree; Step S2: determining the clock length of the target module and the clock length of the secondary module according to the clock tree of the target module and the clock tree of the secondary module of the target module; Step S3: classifying the clock port sent from the target module to the secondary module according to the size relationship between the clock length of the target module and the clock length of the secondary module; Step S4: constructing a formal clock tree of the target module based on the classified clock ports, and uploading the clock length corresponding to the formal clock tree to the high-level module of the target module; Step S5: Taking the high-level module as the new target module, iteratively execute steps S2 to S4 until the formal clock tree of the highest-level module is obtained. The highest-level module is a clock signal generating module, and the formal clock tree of the highest-level module is taken as the final clock tree of the multiple modules.
2. The method according to claim 1, characterized in that Classifying the clock port sent from the target module to the secondary module according to the size relationship between the clock length of the target module and the clock length of the secondary module, including: If the clock length of the target module is greater than the clock length of the secondary module, the clock port sent from the target module to the secondary module is set in the first-level clock tree of the target module; If the clock length of the target module is smaller than the clock length of the secondary module, the clock port from the target module to the secondary module is set in the second-level clock tree of the target module.
3. The method according to claim 1, characterized in that The secondary module includes: a first secondary module and a second secondary module; and according to the size relationship between the clock length of the target module and the clock length of the secondary module, the clock port sent from the target module to the secondary module is classified, including: If the clock length of the target module is greater than the clock length of the first secondary module, the clock port sent from the target module to the first secondary module is set in the first-level clock tree of the target module; If the clock length of the target module is smaller than the clock length of the second-level module, the clock port sent from the target module to the second-level module is set in the second-level clock tree of the target module; Wherein, the first-level clock tree of the target module connects the internal trigger of the target module and the clock port of the target module sent to the first-level module; The first-level clock tree source point of the target module serves as the sinking point of the second-level clock tree of the target module, and the second-level clock tree of the target module connects the clock port of the target module to the second-level module.
4. The method according to any one of claims 2 or 3, characterized in that: The second level clock tree of the target module is located between the target clock port and the initial clock tree of the target module. The target clock port is the clock port sent from the high-level module to the target module.
5. The method according to claim 1, characterized in that: Constructing a formal clock tree of the target module based on the classified clock ports, including: Performing timing processing on each type of the classified clock ports so that the clock length of the clock signal reaching the internal trigger of the target module is the same as the clock length of the clock signal reaching the internal trigger of the secondary module, thereby constructing a formal clock tree of the target module; Among them, the timing processing includes: setting the relative delay relationship between the clock port sent by the target module to the secondary module and the source point of the first-level clock tree in the multi-level clock tree, or setting a clock buffer unit before and after the source point of the first-level clock tree, or modifying the connection relationship between the clock port sent by the target module to the secondary module and the first clock tree.
6. The method according to claim 3, characterized in that Constructing a formal clock tree of the target module based on the classified clock ports, including: Modify the connection relationship between the clock port sent from the target module to the first secondary module and the first clock tree, so that the clock length of the clock signal reaching the clock port sent from the target module to the first secondary module is longer than the clock length of the clock signal reaching the source point of the first clock tree by a first target length, thereby constructing a formal clock tree of the target module, and the first target length is the clock length of the first secondary module; A relative delay relationship is set between the clock port sent from the target module to the second-level module and the source point of the first-level clock tree, or a clock buffer unit is set before and after the source point of the first-level clock tree, so that the clock length of the clock signal reaching the clock port sent from the target module to the second-level module is longer than the clock length of the clock signal reaching the source point of the first clock tree by a second target length, thereby constructing a formal clock tree of the target module, and the second target length is the difference between the clock length of the first-level module and the clock length of the target module.
7. The method according to claim 3, characterized in that The secondary module further includes: a third secondary module; and classifying the clock port sent from the target module to the secondary module according to the size relationship between the clock length of the target module and the clock length of the secondary module, including: If the clock length of the target module is smaller than the clock length of the second-level module and the clock length of the third-level module, and the difference between the clock length of the second-level module and the clock length of the third-level module is smaller than a preset value, the clock port of the target module sent to the second-level module and the third-level module is set in the second-level clock tree of the target module; If the clock length of the target module is less than the clock length of the second-level module and the clock length of the third-level module, and the difference between the clock length of the second-level module and the clock length of the third-level module is not less than the preset value, the clock port sent from the target module to the second-level module is set in the second-level clock tree of the target module, and the clock port sent from the target module to the third-level module is set in the third-level clock tree of the target module; Among them, the second-level clock tree source point of the target module serves as the sinking point of the third-level clock tree of the target module, and the third-level clock tree of the target module connects the clock port of the target module to the third-level module.
8. The method according to claim 7, characterized in that Constructing a formal clock tree of the target module based on the classified clock ports, including: A relative delay relationship is set between the clock port sent by the target module to the third-level module and the source point of the second-level clock tree, or a clock buffer unit is set before and after the source point of the second-level clock tree, so that the clock length of the clock signal reaching the clock port sent by the target module to the third-level module is longer than the clock length of the clock signal reaching the source point of the first clock tree by a third target length, thereby constructing a formal clock tree of the target module, and the third target length is the difference between the clock length of the third-level module and the clock length of the target module.
9. The method according to any one of claims 5 or 6, characterized in that: Constructing a formal clock tree of the target module, including: The clock port sent from the high-level module to the target module is constructed by using an H-tree, binary tree or clock grid structure, and combining the first-level clock tree and the second-level clock tree to construct a formal clock tree of the target module.
10. A clock tree synthesis device, applied to an EDA tool, wherein the device can be configured as follows: A receiving circuit design, wherein the circuit design includes a plurality of modules; Build an initial clock tree for each module and determine the clock length of the module; For all the secondary modules of the target module, the clock ports of the secondary modules with a larger clock length than the target module are set in the first-level clock tree of the circuit design, and the clock ports of the secondary modules with a smaller clock length than the target module are set in the second-level clock tree of the circuit design, so as to construct a formal clock tree of the target module and its secondary modules; wherein, The second level clock tree is a higher level clock tree than the first level clock tree in the circuit design; A clock signal in the circuit design is propagated from a target module to a secondary module via the clock port.
11. A computer program product for EDA, comprising computer executable instructions, which, when executed by a processor, enable the computer to: Provides a user interface for clock tree synthesis; and In response to the operation of the user interface, the following clock tree synthesis operations are performed: A receiving circuit design, wherein the circuit design includes a plurality of modules; Build an initial clock tree for each module and determine the clock length of the module; as well as For all the secondary modules of the target module, the clock ports of the secondary modules whose clock lengths are greater than the clock length of the target module are set in the first-level clock tree of the circuit design, and the clock ports of the secondary modules whose clock lengths are less than the clock length of the current module are set in the second-level clock tree of the circuit design, so as to construct a formal clock tree of the target module and its secondary modules; in, The second level clock tree is a higher level clock tree than the first level clock tree in the circuit design; A clock signal in the circuit design is propagated from a target module to a secondary module via the clock port.