Multi-circuit control system and state information reading method thereof

Abstract

The invention provides a multi-circuit control system and a state information reading method thereof. The multi-circuit control system includes a first circuit and N second circuits. The second circuit is, for example, a three-dimensional NAND gate flash memory circuit, and the multi-circuit control system provides a high performance and high capacity storage medium. The first circuit provides a read clock signal. The second circuits are sequentially connected in series and coupled to the first circuit. Each second circuit has at least one first data shifter. The at least one first data shifter is used for loading state information of each second circuit and shifting each state information to each second circuit or first circuit at a preceding stage according to a read clock signal, or the first circuit obtains the state information of each second circuit through a parallel transmission mechanism.

Description

Technical Field

[0001] The present invention relates to a multi-circuit control system and a method for reading state information thereof, and in particular to a multi-circuit control system of a memory circuit and a method for reading state information thereof. Background Art

[0002] In multi-circuit systems (such as memory systems), a master circuit often needs to monitor the operating status of multiple slave circuits and thereby determine whether each slave circuit is busy. In the prior art, when the master circuit needs to read the status information of each slave circuit to determine whether it is busy, it must send a status information read command one by one and then receive the status information from each slave circuit one by one. When the number of slave circuits is too large, sending status information read commands to all the slave circuits consumes a considerable amount of time, resulting in wasted time and reduced system efficiency. Summary of the Invention

[0003] The present invention provides a multi-circuit control system and a method for reading state information thereof, which can improve the reading efficiency of the state information of the second circuit.

[0004] The multi-circuit control system of the present invention includes a first circuit and N second circuits. The first circuit provides a read clock signal. The second circuits are serially connected and coupled to the first circuit. Each second circuit has at least one first data shifter. The at least one first data shifter is configured to load status information of each second circuit and shift the status information to the preceding second circuit or the first circuit in response to the read clock signal. Alternatively, the first circuit obtains the status information of each second circuit through a parallel transmission mechanism.

[0005] The method for reading status information of the present invention includes: causing a first circuit to provide a read clock signal; causing N second circuits to be serially connected to each other in sequence, and causing the second circuits to be coupled to the first circuit; providing at least one first data shifter in each second circuit, causing the at least one first data shifter to load the status information of each second circuit; and causing each second circuit to shift out each status information to the previous second circuit or the first circuit according to the read clock signal, or causing the first circuit to obtain the status information of each second circuit through a parallel transmission mechanism.

[0006] Based on the above, in the multi-circuit control system of the present invention, the first circuit can read the clock signal so that the status information of multiple second circuits is read sequentially according to the clock cycles of the read clock signal. In this way, the first circuit can avoid the time wasted in issuing read commands to each second circuit, thereby improving the operating efficiency of the multi-circuit control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a schematic diagram of a multi-circuit control system according to an embodiment of the present invention.

[0008] Figure 2 FIG. 4 is a schematic diagram of a multi-circuit control system according to another embodiment of the present invention.

[0009] Figure 3 Schematic diagram of implementation of each second circuit in a multi-circuit control system according to an embodiment of the present invention.

[0010] Figure 4 Flowchart of a method for reading status information of a multi-circuit control system according to an embodiment of the present invention.

[0011] Figure 5 2 is an operation waveform diagram of a multi-circuit control system according to an embodiment of the present invention.

[0012] Figure 6A This is an operation waveform diagram of another implementation of a multi-circuit control system according to an embodiment of the present invention.

[0013] Figure 6B FIG. 4 is a schematic diagram of a multi-circuit control system according to another embodiment of the present invention.

[0014] Figure 7 FIG. 4 is a schematic diagram of a multi-circuit control system according to another embodiment of the present invention.

[0015] Figure 8 Flowchart of a method for reading status information of a multi-circuit control system according to an embodiment of the present invention.

[0016] Description of Reference Numerals

[0017] 100, 200, 600, 700: Multi-circuit control system

[0018] 110, 210, 610, 710: First circuit

[0019] 120-1 to 120-N, 220-1 to 220-N, 300, 620-1 to 620-N, 720-1 to 720-A, 730-1 to 730-B: Second circuit

[0020] 310, 320: Data shifter

[0021] 311, 312, 321, 322: Shift register

[0022] ADD: address signal

[0023] CLK: clock signal

[0024] CMD: command signal

[0025] IN[0], IN[1], IN[3], IN[4]: data input terminals

[0026] IO[7:0]: input and output signals

[0027] IOP, IOP1, IOP2: parallel input and output terminals

[0028] LD: Load signal

[0029] OUT[0], OUT[1]: data output terminals

[0030] RE#: Read clock signal

[0031] RP, RP1, RP2: Read signal transmission end

[0032] S410~S430, S810~S840: Steps

[0033] ST0[0], ST0[1], ST1[0], ST1[1], ST0[0]-0, ST0[1]-0, ST1[0]-0, ST1[1]-0, ST0[0]-1, ST0[1]-1, ST1[0]-1, ST1[1]-1, ST0[0]-2, ST0[1]-2, ST1[0]-2, ST1[1]-2: Status information

[0034] T1, T2: time interval

[0035] TP1~TP5: Time points

[0036] WE#: write signal

[0037] WP, WP1, WP2: write signal transmission end DETAILED DESCRIPTION

[0038] Please refer to Figure 1 , Figure 1This is a schematic diagram of a multi-circuit control system according to an embodiment of the present invention. The multi-circuit control system 100 includes a first circuit 110 and a plurality of second circuits 120-1 to 120-N. The second circuits 120-1 to 120-N are coupled in series with each other, and the second circuits 120-1 to 120-N are also coupled to the first circuit 110. The first-stage second circuit 120-1 is coupled between the second-stage second circuit 120-2 and the first circuit 110. The second circuits 120-2 to 120-N of the second to Nth stages are sequentially coupled after the first-stage second circuit 120-1. Each of the second circuits 120-1 to 120-N has a data output terminal OUT[0] and a data input terminal IN[0], and the first circuit 110 has a data input terminal IN[0]. In detail, the data output terminal OUT[0] of the first-stage second circuit 120-1 is coupled to the data input terminal IN[0] of the first circuit 110. The data input terminals IN[0] of the second circuits 120-1 to 120-(N-1) of the first to N-1 stages are respectively coupled to the data output terminals OUT[0] of the second circuits 120-2 to 120-N of the next stage (second to N stages).

[0039] In addition, each of the first circuit 110 and the second circuits 120-1 to 120-N has a write signal transmission terminal WP and a read signal transmission terminal RP. The write signal transmission terminals WP of the first circuit 110 and the second circuits 120-1 to 120-N are coupled to each other and are used to transmit a write signal WE#. The read signal transmission terminals RP of the first circuit 110 and the second circuits 120-1 to 120-N are coupled to each other. The first circuit 110 can transmit a read clock signal RE# to the second circuits 120-1 to 120-N via the read signal transmission terminal RP. Furthermore, each of the first circuit 110 and the second circuits 120-1 to 120-N can further have a parallel input / output terminal IOP. Parallel data transmission can be performed between the first circuit 110 and each of the second circuits 120-1 to 120-N via the parallel input / output terminals IOP.

[0040] In this embodiment, each second circuit 120-1 to 120-N may include a data shifter. The data shifter may be coupled between the data input terminal IN[0] and the data output terminal OUT[0] of the corresponding second circuit 120-1 to 120-N. Each second circuit 120-1 to 120-N may load its state information into the data shifter, and the data shifter may shift out the stored state information based on the clock cycle of the read clock signal RE# received by the corresponding second circuit 120-1 to 120-N.

[0041] In detail, when the first circuit 110 needs to read the status information of the second circuits 120-1 to 120-N, it can transmit the relevant command to the second circuits 120-1 to 120-N via the parallel input / output terminal IOP. In response, the second circuits 120-1 to 120-N can load their status information into the multiple data shifters therein. Then, the first circuit 110 can transmit a read clock signal RE# to the second circuits 120-1 to 120-N, causing the multiple data shifters in the second circuits 120-1 to 120-N to shift the stored status information to their data output terminals OUT[0] according to the clock cycles of the read clock signal RE#.

[0042] According to the coupling structure of the multi-circuit control system 100, as the clock cycle of the read clock signal RE# increases, the state information of the second circuit 120-1 can be first shifted to the first circuit 110. Then, the state information of the subsequent second circuits 120-2 through 120-N can be shifted to the previous second circuits 120-1 through 120-(N-1). Similarly, as the clock cycle of the read clock signal RE# increases, the state information of the second circuits 120-2 through 120-N can be sequentially shifted to the first circuit 110. In this way, the first circuit 110 can smoothly read the state information of all the second circuits 120-1 through 120-N.

[0043] Incidentally, the multi-circuit control system 100 of this embodiment can be a memory system and can be applied, for example, to a solid-state disk (SSD). The first circuit 110 can be a memory controller and can be set as a master circuit. The second circuits 120-1 to 120-N can be memory circuits and can be set as slave circuits. The second circuits 120-1 to 120-N can be, for example, NAND, AND, or NOR flash memory circuits. Furthermore, the first circuit 110 can be set on a first chip, and the second circuits 120-1 to 120-N can be set on multiple different chips, respectively.

[0044] On the other hand, in an embodiment of the present invention, when the first circuit 110 only needs to read the status information of one of the second circuits 120-1 to 120-N, it can transmit a related command to the second circuits 120-1 to 120-N via the parallel input / output terminal IOP. The transmitted data packet notifies the selected second circuit (one of the second circuits 120-1 to 120-N) to transmit its status information to the first circuit 110 via the parallel input / output terminal IOP. Furthermore, while the first circuit 110 is reading the status information of the selected second circuit via its parallel input / output terminal IOP, the status information of the second circuits 120-1 to 120-N can be shifted simultaneously. Under this mechanism, the data input terminal IN[0] of the first circuit 110 can be disconnected from the data output terminal OUT[0] of the second circuit 120-1.

[0045] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a multi-circuit control system according to another embodiment of the present invention. The multi-circuit control system 200 includes a first circuit 210 and a plurality of second circuits 220 - 1 through 220 -N. The second circuits 220 - 1 through 220 -N are coupled in series with each other and are in turn coupled to the first circuit 210.

[0046] and Figure 1 The embodiments are different. In this embodiment, each second circuit 220-1 to 220-N has multiple data input terminals IN[0], IN[1] and multiple data output terminals OUT[0], OUT[1]. The first circuit 210 also has multiple data input terminals IN[0], IN[1]. Among them, the data output terminals OUT[0], OUT[1] of the second circuit 220-1 of the first stage are respectively coupled to the data input terminals IN[0], IN[1] of the first circuit 210. The data input terminals IN[0], IN[1] of the second circuits 220-1 to 220-(N-1) of the first to N-1 stages are respectively coupled to the data output terminals OUT[0], OUT[1] of the second circuits 220-2 to 220-N of the next stage (second to N stages).

[0047] On the other hand, in this embodiment, each of the second circuits 220-1 to 220-N may have a plurality of data shifters. One of the data shifters may be coupled between the data input terminal IN[0] and the data output terminal OUT[0], and another data shifter may be coupled between the data input terminal IN[1] and the data output terminal OUT[1]. The data shifting operation of the second circuits 220-1 to 220-N in this embodiment is similar to Figure 1 The embodiments are similar and will not be described again here.

[0048] In this embodiment, the multi-circuit control system 200 can speed up the reading of the status information of each of the second circuits 220 - 1 to 220 -N by disposing a plurality of data shifters in each of the second circuits 220 - 1 to 220 -N.

[0049] It is worth mentioning that, in the embodiment of the present invention, the number of data input terminals, data output terminals and corresponding data shifters in each of the second circuits 220 - 1 to 220 -N may be more than two. Figure 2 The two data input terminals IN[0] and IN[1] and the two data output terminals OUT[0] and OUT[1] shown are merely examples for illustration purposes and are not intended to limit the scope of implementation of the present invention.

[0050] Please refer to Figure 3 , Figure 3 Schematic diagram of the implementation of each second circuit in the multi-circuit control system of an embodiment of the present invention. The second circuit 300 includes data shifters 310 and 320. The data shifter 310 is coupled between the data input terminal IN[0] and the data output terminal OUT[0], and the data shifter 320 is coupled between the data input terminal IN[1] and the data output terminal OUT[1]. The data shifters 310 and 320 are respectively composed of two shift register groups. The shift register group in the data shifter 310 includes a plurality of shift registers 311 and 312. The shift register group in the data shifter 320 includes a plurality of shift registers 321 and 322. It is worth mentioning that in Figure 3 In the illustration, the single shift register group includes two shift registers. This is just an example for illustration. In the embodiment of the present invention, the single shift register group may include two or more registers without any specific limitation. In addition, the number of data shifters in the second circuit 300 may also be more than two. Figure 3 The illustration is not intended to limit the number of data shifters.

[0051] In this embodiment, the shift registers 311 and 312 are sequentially coupled between the data input terminal IN[0] and the data output terminal OUT[0]. The shift registers 311 and 312 jointly receive the load signal LD, the clock signal CLK, and the first portion of the state information ST0[0] and ST0[1]. When the state information ST0[0] and ST0[1] of the second circuit 300 is to be read, the load signal LD ​​can be enabled, and the state information ST0[0] and ST0[1] are loaded into the shift registers 311 and 312, respectively. Then, the load signal LD ​​can be disabled, and the shift registers 311 and 312 can sequentially shift the state information ST0[0] and ST0[1] to the data output terminal OUT[0] according to the clock cycle of the clock signal CLK.

[0052] In addition, the shift registers 321 and 322 are sequentially coupled between the data input terminal IN[1] and the data output terminal OUT[1]. The shift registers 321 and 322 jointly receive the load signal LD, the clock signal CLK, and the second portion of the state information ST1[0] and ST1[1]. When the load signal LD ​​is enabled, multiple bits of the state information ST1[0] and ST1[1] can be loaded into the shift registers 321 and 322, respectively. Then, after the load signal LD ​​is disabled, the shift registers 321 and 322 can sequentially shift the state information ST1[0] and ST1[1] to the data output terminal OUT[1] according to the clock cycle of the clock signal CLK. The state information ST0[0] and ST0[1] and ST1[0] and ST1[1] are respectively transmitted to the second circuit or the first circuit of the previous stage through the data output terminals OUT[0] and OUT[1].

[0053] In addition, as the clock signal CLK cycles, the shift registers 321 and 322 can receive status information transmitted from the second circuit of the subsequent stage through the data input terminals IN[0] and JN[1], respectively, and then transmit the received status information to the second circuit or the first circuit of the previous stage through the data output terminals OUT[0] and OUT[1].

[0054] It is worth noting that, in this embodiment, the clock signal CLK can be generated based on the read clock signal RE# provided by the first circuit. The load signal LD ​​can be disabled or enabled based on the write signal WE# provided by the first circuit. The relevant implementation details will be described in detail in subsequent embodiments.

[0055] The shift registers 311 , 312 , 321 , and 322 can be implemented using shift register circuits well known to those skilled in the art without any particular limitation.

[0056] Please refer to Figure 4 , Figure 4 The flowchart of a method for reading status information of a multi-circuit control system according to an embodiment of the present invention is shown. The multi-circuit control system includes a first circuit serving as a master circuit and a plurality of second circuits serving as slave circuits. In step S410, the plurality of second circuits serving as slave circuits receive a command to read status information sent by the first circuit serving as the master circuit. Next, in step S420, the second circuits load their status information into a shift register. In step S430, the second circuits shift the status information to the next shift register during each clock cycle of the read clock signal.

[0057] Please refer to it synchronously Figure 3 as well as Figure 5 ,in Figure 5 This is an action waveform diagram of a multi-circuit control system according to an embodiment of the present invention. Figure 5 During the time interval T1, the first circuit of the main circuit sends a read command of the status information to the second circuit 300 by pulling the write signal WE# low. In response to the pulling low action of the write signal WE#, the second circuit 300 can pull the load signal LD ​​high after the time interval T1 to enable the load signal LD, and load the status information ST0[0]-0, status information ST0[1]-0, status information ST1[0]-0, and status information ST1[1]-0 of the second circuit 300 into the shift registers 312, 311, 322, and 321, respectively.

[0058] During time interval T2, the first circuit can pull the write signal WE# low again to send a dummy clock cycle. The second circuit 300 can disable the load signal LD ​​by pulling the load signal LD ​​low according to the dummy clock cycle. It should be noted that the dummy clock cycle is not required. The second circuit 300 can also automatically pull the load signal LD ​​low after the load signal LD ​​remains enabled for a predetermined period of time.

[0059] At time point TP1, the data input terminals IN[0] and IN[1] of the second circuit 300 can respectively receive the status information ST0[0]-1 and ST1[0]-1 of the second circuit of the next level, and the data output terminals OUT[0] and OUT[1] of the second circuit 300 can respectively send the status information ST0[0]-0 and ST1[0]-0.

[0060] Then, after time point TP2, the first circuit may begin providing a continuously transitioning read clock signal RE#. Corresponding to the transition of the read clock signal RE#, the second circuit 300 may generate a corresponding clock signal CLK. In this embodiment, the second circuit 300 may detect the falling edge of the read clock signal RE# and initiate the transition of the clock signal CLK based on the falling edge of the read clock signal RE#. After time point TP1, the clock signal CLK may be in phase with the read clock signal RE#. Of course, in other embodiments of the present invention, the clock signal CLK may also have a phase difference with the read clock signal RE#, and the transition of the clock signal CLK may also be initiated based on the read clock signal RE# through other mechanisms. For example, the second circuit 300 may be initiated based on the rising edge of the read clock signal RE# or by counting a certain number of clock cycles of the read clock signal RE#. The relevant details are at the discretion of the circuit designer and are not limited.

[0061] After time point TP2, as the clock signal CLK cycles, the shift registers 311, 312, 321, and 322 in the second circuit 300 can perform a shift operation of the state information according to the rising edge of the clock signal CLK. Therefore, at time point TP3, the state information ST0[0]-1 and ST1[0]-1 of the subsequent second circuit previously on the data input terminals IN[0] and IN[1] are shifted into the shift registers 311 and 321, respectively, and the state information ST0[1]-0 and ST1[1]-0 previously in the shift registers 311 and 321 are shifted into the shift registers 312 and 322, respectively. The shift registers 312 and 322 then output the stored state information ST0[1]-0 and ST1[1]-0 to the data output terminals OUT[0] and OUT[1]. At this time, the data input terminals IN[0] and IN[1] receive the status information ST0[1]-1 and ST1[1]-1 of the second circuit of the next stage.

[0062] At time point TP4, the state information ST0[1]-1 and ST1[1]-1 of the second circuit of the next stage previously on the data input terminals IN[0] and IN[1] are shifted into the shift registers 311 and 321, respectively. The state information ST0[0]-1 and ST1[0]-1 previously in the shift registers 311 and 321 are shifted into the shift registers 312 and 322, respectively. The shift registers 312 and 322 then output the stored state information ST0[0]-1 and ST1[0]-1 to the data output terminals OUT[0] and OUT[1]. At this time, the data input terminals IN[0] and IN[1] receive the state information ST0[0]-2 and ST1[0]-2 of the second circuit of the next stage.

[0063] At time point TP5, the state information ST0[0]-2 and ST1[0]-2 of the second circuit of the next two stages previously on the data input terminals IN[0] and IN[1] are shifted into the shift registers 311 and 321, respectively. The state information ST0[1]-1 and ST1[1]-1 previously in the shift registers 311 and 321 are shifted into the shift registers 312 and 322, respectively. The shift registers 312 and 322 then output the stored state information ST0[1]-1 and ST1[1]-1 to the data output terminals OUT[0] and OUT[1]. At this time, the data input terminals IN[0] and IN[1] receive the state information ST0[1]-2 and ST1[1]-2 of the second circuit of the next two stages.

[0064] Please refer to it synchronously Figure 2 as well as Figure 6A ,in Figure 6A This is an action waveform diagram of another embodiment of the multi-circuit control system of the present invention. Figure 6ADuring time interval T1, the first circuit 210 of the master circuit pulls the write signal WE# low and transmits the input / output signal IO[7:0], which is the command signal CMD, to the second circuits 220-1 to 220-N via the parallel input / output terminal IOP. Then, during time interval T2, the first circuit 210 pulls the write signal WE# low again and transmits the input / output signal IO[7:0], which is the address signal ADD, to the second circuits 220-1 to 220-N via the parallel input / output terminal IOP. In this embodiment, the command signal CMD is used to indicate that the first circuit 210 intends to read the status information of one of the second circuits 220-1 to 220-N. The address signal ADD indicates the address information of the selected second circuit (one of the second circuits 220-1 to 220-N) to be read.

[0065] Next, the first circuit 210 may provide a read clock signal RE#, and cause the selected second circuit (e.g., the second circuit 220-1) to sequentially transmit the input / output signals IO[7:0], which are state information ST[0]-0 and ST[1]-0, to the first circuit 210 via the parallel input / output terminal IOP in accordance with the clock cycles of the read clock signal RE#. After the state information ST[0]-0 and ST[1]-0 of the second circuit 220-1 are output, the state information ST[0]-1 and ST[1]-1 of the next-level second circuit 220-2 may be transmitted to the first circuit 210 via the input / output signals IO[7:0] in accordance with the clock cycles of the read clock signal RE#.

[0066] In this embodiment, the first circuit 210 can perform a status reading operation on a desired one of the second circuits 220 - 1 ˜ 220 -N through the parallel input and output terminals IOP, and can quickly obtain status information of each of the second circuits 220 - 1 ˜ 220 -N.

[0067] Figure 6B Schematic diagram of a multi-circuit control system according to another embodiment of the present invention. The multi-circuit control system 600 includes a first circuit 610 and a plurality of second circuits 620-1 to 620-N. The second circuits 620-1 to 620-N are coupled in series with each other, and the second circuits 620-1 to 620-N are coupled to the first circuit 610 through the parallel input and output terminals IOP. Please note that in this embodiment, the data output terminals OUT[0] and OUT[1] of the first-stage second circuit 620-1 are isolated from the first circuit 610. In other words, the first circuit 610 of this embodiment can be as follows. Figure 6A As shown in the waveform diagram, the state information of each second circuit 620-1 to 620-N is read through the parallel input and output terminal IOP through the parallel transmission mechanism.

[0068] Please refer to Figure 7 , Figure 7 This is a schematic diagram of a multi-circuit control system according to another embodiment of the present invention. The multi-circuit control system 700 includes a first circuit 710 and a plurality of second circuits 720-1 to 720-A and 730-1 to 730-B. The second circuits 720-1 to 720-A are coupled in series with each other, and the data output terminals OUT[0] and OUT[1] of the first-stage second circuit 720-1 are coupled to the data input terminals IN[0] and IN[1] of the first circuit 710, respectively. In addition, the parallel input and output terminals IOP of each of the second circuits 720-1 to 720-A are coupled to the parallel input and output terminal IOP1 of the first circuit 710.

[0069] Furthermore, the second circuits 730-1 to 730-B are coupled in series with each other, and the data output terminals OUT[0] and OUT[1] of the first-stage second circuit 730-1 are respectively coupled to the data input terminals IN[2] and IN[3] of the first circuit 710. Furthermore, the parallel input / output terminals IOP of each of the second circuits 730-1 to 730-B are commonly coupled to the parallel input / output terminal IOP2 of the first circuit 710.

[0070] In this embodiment, the first circuit 710 can transmit a read clock signal RE1# and a write signal WE1# to the second circuits 720-1 to 720-A via the read signal transmission terminal RP1 and the write signal transmission terminal WP1, respectively, to control the reading of status information. The first circuit 710 can also transmit a read clock signal RE2# and a write signal WE2# to the second circuits 730-1 to 730-B via the read signal transmission terminal RP2 and the write signal transmission terminal WP2, respectively, to control the reading of status information. Furthermore, the first circuit 710 can read the status information of any of the second circuits 720-1 to 720-A via the parallel input / output terminal IOP1, and can also read the status information of any of the second circuits 730-1 to 730-B via the parallel input / output terminal IOP2.

[0071] The details of the reading operation of the status information have been described in detail in the aforementioned embodiments and will not be repeated here.

[0072] It is worth noting that the number of second circuits 720-1 to 720-A in the string formed by the second circuits 720-1 to 720-A and the number of second circuits 730-1 to 730-B in the string formed by the second circuits 730-1 to 730-B can be the same or different. Furthermore, in other embodiments of the present invention, the multi-circuit system 700 may also include other second circuits to form one or more strings. Specifically, the number of strings formed by the second circuits in the multi-circuit system 700 can be one or more, without any specific limitation.

[0073] Please refer to Figure 8 , Figure 8 This is a flow chart of a method for reading status information of a multi-circuit control system according to an embodiment of the present invention. In step S810, the first circuit provides a read clock signal. In step S820, N second circuits are serially connected in sequence and coupled to the first circuit, where N is an integer greater than 1. In step S830, at least one first data shifter is provided in each second circuit, and the at least one first data shifter is loaded with status information of each second circuit. In step S840, each second circuit shifts out the status information to the preceding second circuit or the first circuit according to the read clock signal.

[0074] The implementation details of the above steps have been described in detail in the aforementioned embodiments and will not be repeated here.

[0075] In summary, in the multi-circuit control system of the present invention, by coupling a first circuit to multiple second circuits connected in series and providing a read clock signal, the status information of the multiple second circuits is sequentially read out in accordance with the clock cycles of the read clock signal. This eliminates the need for the first circuit to issue a read command to each second circuit individually to read the status information of each second circuit, effectively saving time.

Claims

1. A multi-circuit control system, comprising: A first circuit provides a read clock signal; as well as N second circuits are serially connected to each other in sequence, and these second circuits are coupled to the first circuit, where N is an integer greater than 1. Each of the second circuits has at least one first data shifter, which is used to load status information of each of the second circuits and shift out each of the status information to the previous second circuit or the first circuit according to the read clock signal, or the first circuit obtains the status information of each of the second circuits through a parallel transmission mechanism.

2. The multi-circuit control system according to claim 1, wherein each of the second circuits has at least one data output terminal and at least one data input terminal, and the at least one data output terminal and the at least one data input terminal are coupled to the at least one first data shifter.

3. A multi-circuit control system according to claim 2, wherein the at least one data output terminal of each of the second circuits of the Nth to 2nd stages is coupled to the at least one data input terminal of each of the second circuits of the previous stage, and the at least one data output terminal of the second circuit of the first stage is coupled to the first circuit or isolated from the first circuit.

4. The multi-circuit control system according to claim 2, wherein each of the at least one first data shifter is a shift register group, and the shift register group is coupled between each of the at least one data input terminal and each of the at least one data output terminal of the corresponding each of the second circuits.

5. The multi-circuit control system according to claim 4, wherein the shift register group comprises: A plurality of shift registers are coupled in series with each other. The shift registers receive a loading signal and the read clock signal together, and receive the corresponding status information respectively. 6 . The multi-circuit control system according to claim 5 , wherein the shift registers store the bits of the status information into the shift registers respectively according to the load signal, and perform data shifting according to the read clock signal.

7. The multi-circuit control system according to claim 1, wherein the second circuits are respectively a plurality of memory circuits, and the first circuit is a memory control circuit.

8. The multi-circuit control system according to claim 1, wherein the first circuit further comprises a first parallel input-output interface, the second circuits respectively comprise a plurality of second parallel input-output interfaces, and the first parallel input-output interface is coupled to the second parallel input-output interfaces. 9 . The multi-circuit control system according to claim 8 , wherein the first circuit reads the status information of one of the second circuits through the first parallel input / output interface.

10. The multi-circuit control system according to claim 1, further comprising: N third circuits are serially connected to each other in sequence, and these third circuits are coupled to the first circuit. Each of the third circuits has at least one second data shifter, and the at least one second data shifter is used to load the state information of each of the third circuits and shift out the state information to the third circuits of the previous stage or the first circuit according to the read clock signal.

11. The multi-circuit control system according to claim 1, wherein the first circuit is disposed on a first chip, and the second circuits are disposed on a plurality of second chips respectively.

12. A method for reading status information, comprising: Enable a first circuit to provide a read clock signal; Connecting N second circuits in series in sequence, and coupling the second circuits to the first circuit, wherein N is an integer greater than 1; Providing at least one first data shifter in each of the second circuits, so that the at least one first data shifter is loaded with state information of each of the second circuits; as well as Each of the second circuits is enabled to shift out each of the state information to each of the second circuits or the first circuit at the previous stage according to the read clock signal, or the first circuit is enabled to obtain the state information of each of the second circuits through a parallel transmission mechanism.

13. The reading method according to claim 12, further comprising: A shift register group is disposed in each of the at least one first data shifter, wherein the shift register group is coupled between each of the at least one data input terminal and each of the at least one data output terminal of the corresponding each of the second circuits.

14. The reading method according to claim 13, wherein the shift register group comprises a plurality of shift registers coupled in series, the reading method further comprising: The shift registers are configured to store the bits of the state information into the shift registers respectively according to a load signal; as well as The shift registers are made to perform data shifting action according to the read clock signal.

15. The reading method according to claim 12, further comprising: Connecting a plurality of third circuits in series in sequence, and coupling the third circuits to the first circuit; Providing at least one second data shifter in each of the third circuits, so that the at least one second data shifter is loaded with state information of each of the third circuits; and Each of the third circuits is enabled to shift out each of the state information to each of the third circuits or the first circuit at the previous stage according to the read clock signal.

16. The reading method according to claim 12, further comprising: A first parallel input-output interface is provided in the first circuit, and a plurality of second parallel input-output interfaces are respectively provided in the second circuits; coupling the first parallel input-output interface and the second parallel input-output interfaces to each other; and The first circuit is enabled to read the state information of one of the second circuits through the first parallel input-output interface.

17. The reading method according to claim 12, further comprising: The first circuit is arranged on a first chip, and the second circuits are arranged on a plurality of second chips respectively. The first circuit is a memory control circuit, and the second circuits are respectively provided with a plurality of memory circuits.

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