Semiconductor structure and manufacturing method thereof

Abstract

A method of fabricating a semiconductor structure includes forming a die including forming a first through-via and a second through-via extending into a semiconductor substrate from a front side of the semiconductor substrate. The first through-via and the second through-via are respectively connected to a first integrated circuit device and a second integrated circuit device in the die. A backside grinding process is performed to expose the first through hole and the second through hole. A backside redistribution line is formed to physically bond to both the first through-vias and the second through-vias. The embodiment of the invention also provides a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of manufacturing the same. Background Art

[0002] Integrated circuit packages are becoming increasingly complex, with more device dies being packaged in the same package to achieve more functionality. For example, packaging structures have been developed to include multiple device dies (such as a processor and a memory cube) in the same package. A packaging structure can include device dies formed using different technologies and having different functions coupled to the same device die, thus forming a system. This can save manufacturing costs and optimize device performance. Summary of the invention

[0003] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, the method comprising: forming a tube core, the forming of the tube core comprising: forming a first through hole and a second through hole extending from the front side of the semiconductor substrate into the semiconductor substrate, wherein the first through hole and the second through hole are respectively connected to a first integrated circuit device and a second integrated circuit device in the tube core; performing a backside grinding process to expose the first through hole and the second through hole; and forming a backside redistribution line, the backside redistribution line being physically coupled to both the first through hole and the second through hole.

[0004] Other embodiments of the present disclosure provide a semiconductor structure, which includes: a tube core, the tube core includes: a semiconductor substrate; a first integrated circuit device and a second integrated circuit device, which are located on the front side of the semiconductor substrate; a first through hole and a second through hole, which penetrate the semiconductor substrate, wherein the first through hole and the second through hole are respectively connected to the first integrated circuit device and the second integrated circuit device; and a first back side redistribution line, which is located on the back side of the semiconductor substrate, wherein the first back side redistribution line physically contacts both the first through hole and the second through hole.

[0005] Another embodiment of the present disclosure provides a semiconductor structure, which includes: a tube core, the tube core includes: a semiconductor substrate; a first integrated circuit and a second integrated circuit located at the front side of the semiconductor substrate; a dielectric isolation layer, contacting the back side of the semiconductor substrate; and a back side redistribution line, contacting the dielectric isolation layer, wherein the back side redistribution line electrically connects the first integrated circuit to the second integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 9 A cross-sectional view is shown of an intermediate stage in forming a package in accordance with some embodiments.

[0008] Fig.10 An enlarged view of a portion of a package is shown in accordance with some embodiments.

[0009] Fig.11 and Fig.12 A bottom view of portions of a package according to some embodiments is shown.

[0010] Fig.13A , Fig. 13B , FIG. 13C to FIG. 22A , Fig. 22B and Fig. 22C Views of portions of packages are shown according to some embodiments.

[0011] Fig.23A and FIG. 23B to FIG. 26A and Fig.26B Views of portions of packages are shown according to some embodiments.

[0012] Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A and Fig.29B Views showing portions of dummy bumps in a package according to some embodiments.

[0013] Fig.30 Portions of a package are shown in accordance with some embodiments.

[0014] FIG. 31A to FIG. 31I A top view of a dummy bump is shown in accordance with some embodiments.

[0015] Figure 32 to Figure 34 Some applications of packages according to some embodiments are shown.

[0016] Fig.35 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] A package and a method for forming the same are provided. According to some embodiments of the present disclosure, the package includes a device die, which includes a through silicon via (TSV) penetrating a semiconductor substrate. The device die is referred to as a TSV die hereinafter. A backside redistribution line (RDL) is formed on the back side of the semiconductor substrate. The backside RDL can be used to integrate signals from different TSVs, and thus the backside RDL can be electrically connected to multiple TSVs, which are connected to different circuits. Accordingly, signals from multiple TSVs can be connected to the same metal bumps in the device die for bonding. The backside RDL can also be connected to the upper RDL (also referred to as the intermediate RDL), which can also integrate signals connected to different metal bumps. By integrating the signals, fewer metal bumps are required for bonding, and fewer intermediate RDLs are required.

[0020] The embodiments discussed herein are intended to provide examples so that the subject matter of the present disclosure can be made or used, and those of ordinary skill in the art will readily appreciate the modifications that may be made while maintaining the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0021] Figures 1 to 91 shows a cross-sectional view of an intermediate stage in forming a package according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Fig.35 The process flow shown.

[0022] Figure 1 A wafer 20 according to some embodiments is shown. The wafer 20 includes identical device dies 20'. In addition, the wafer 20 includes a semiconductor substrate 22, which may be or may include silicon, silicon germanium, carbon-doped silicon, etc. The integrated circuit device (not shown, see Fig.10 Integrated circuits 94 ′ and 94 ″), such as transistors, capacitors, inductors, resistors, etc., may be formed in wafer 20 and may be located in or above semiconductor substrate 22 .

[0023] Through-holes (also referred to as through-silicon vias (TSVs) or through-substrate vias (also referred to as TSVs)) 24 are formed to extend into semiconductor substrate 22. TSVs 24 extend to an intermediate level between the top and bottom surfaces of semiconductor substrate 22. Each TSV 24 is surrounded by a dielectric isolation layer (not shown) and is separated from semiconductor substrate 22. Therefore, device die 20' is alternatively referred to as TSV die 20'.

[0024] An interconnect structure 23 is formed over semiconductor substrate 22. Interconnect structure 23 includes multiple dielectric layers and metal lines and vias in the dielectric layers, which may include low-k dielectric layers. The metal lines and vias electrically interconnect integrated circuit devices into functional circuits. TSVs 24 may extend to any level of interconnect structure 23. Metal bumps 26 are formed over interconnect structure 23 and are electrically connected to metal lines and vias in the interconnect structure, integrated circuits in wafer 20, and TSVs 24.

[0025] According to some embodiments, metal bumps 26 are formed on the top surface of wafer 20. Metal bumps 26 may be formed by plating. Metal bumps 26 may include copper bumps, and may or may not include nickel bumps, solder bumps, etc.

[0026] See also Figure 2 , the wafer 20 is attached to the carrier 30, wherein the front side of the wafer 20 (such as a dielectric bonding film (not shown)) faces the carrier 30 and is attached to the carrier 30. The corresponding process is shown as Fig.35Process 202 in process flow 200 is shown. According to some embodiments, carrier 30 includes a bulk semiconductor carrier (such as a silicon carrier) and a bonding layer located on the bulk semiconductor carrier. The bonding layer may be formed of a silicon-containing dielectric material, and the silicon-containing dielectric material is selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. According to some embodiments, wafer 20 may be attached to carrier 30 by fusion bonding, wherein the surface bonding layer of wafer 20 is bonded to the bonding layer in carrier 30.

[0027] According to an alternative embodiment, the carrier 30 includes a transparent substrate, such as a glass substrate. An adhesive, such as a light-to-heat conversion (LTHC) material (not shown) is applied on the carrier 30, and the wafer 20 is adhered to the carrier 30. The LTHC material can be decomposed under the heat of light (such as a laser beam).

[0028] In the subsequent process, a backside grinding process is performed to thin the semiconductor substrate 22. The backside grinding process is performed until the TSV 24 is exposed. The corresponding process is shown as Fig.35 Process 204 in process flow 200 is shown.

[0029] Next, if Figure 3 As shown, a backside redistribution structure 34 is formed on the backside of the wafer 20. The corresponding process is shown as follows: Fig.35 Process 206 in process flow 200 is shown. According to some embodiments, semiconductor substrate 22 is recessed by an etch-back process. Accordingly, the top of TSV 24 protrudes above the top surface (back surface) of semiconductor substrate 22. The space above the back surface of semiconductor substrate 22 and below the top of TSV 24 is referred to as a recess.

[0030] Next, the groove is filled with a dielectric isolation layer 32. The dielectric isolation layer 32 is formed of or includes an inorganic dielectric material, such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxide, silicon carbide, silicon oxycarbide, etc., or a combination thereof. The formation process may include a conformal deposition process or a non-conformal deposition process, and the formation process may be performed using atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), etc. After deposition, a planarization process is performed to remove the portion of the dielectric isolation layer 32 that is higher than the top of the TSV 24. Accordingly, the top surface of the dielectric isolation layer 32 is coplanar with the top of the TSV 24.

[0031] Next, if Figure 3 As shown, a backside redistribution structure 34 is formed, and the backside redistribution structure 34 includes an RDL 38. There may or may not be a dielectric layer 36, depending on how many layers of RDL 38 are formed. It can be understood that in Figure 3The backside redistribution structure 34 is schematically shown in FIG. 1 , and the details can be seen in the subsequent sections showing the enlarged portion. Fig. 9 and Fig.10 The formation of the backside redistribution structure 34 may also include forming a metal bump 40. According to some embodiments, the metal bump 40 may be a copper bump. The corresponding process is shown as Fig.35 Process 208 of process flow 200 is shown. Solder regions 42 may be formed on metal bumps 40.

[0032] According to some embodiments, the formation of dielectric layer 36 (if any), RDL 38, metal bump 40 and solder 42 may include depositing dielectric layer (if any), patterning dielectric layer to expose underlying conductive features (such as TSV 24 or RDL 38), and forming a metal seed layer. A plating mask (such as a patterned photoresist) is then formed, wherein some portions of the metal seed layer are exposed through openings in the plating mask. Conductive features (such as RDL 38, metal bump 40 and / or solder 42) are then formed by plating in the openings of the plating mask. The plating mask is then removed, thereby exposing some portions of the metal seed layer. The exposed portions of the metal seed layer are then etched. Dielectric layer 36 (if any) may include polyimide, polybenzoxazole (PBO), and the like.

[0033] The wafer 20 and the carrier 30 are collectively referred to as a composite wafer 44 hereinafter. Figure 3 As shown, the composite wafer 40 is placed on a dicing tape 46, which is fixed on a frame 48. A singulation process is then performed to cut the composite wafer 44 into packages 44', each of which includes one TSV die 20'.

[0034] Figure 4 The formation of a package assembly 47 is shown, which will be bonded to Figure 3 The corresponding process is shown as Fig.35 The process 210 in the process flow 200 is shown. Figure 4 , attaching the InFO package 50 to the carrier 52. The carrier 52 may be formed by Figure 2 ) and may include a glass substrate, a silicon substrate, etc. In accordance with some embodiments, the InFO package 50 may include a device die 54 (or a package including multiple device dies), which may represent a single device die or multiple device dies bonded to form a package. Although one device die 54 is shown, multiple device dies 54 may be placed above the carrier 50. In accordance with some embodiments, multiple device dies may also form a system. The device die 54 may include a metal bump 58 and a surface dielectric layer 60.

[0035] According to some embodiments, device die 54 is encapsulated in gap-fill region 56 (also referred to as encapsulant 56). According to some embodiments, gap-fill region 56 includes a dielectric liner and a dielectric region on the dielectric liner. The dielectric liner may be formed of or include silicon nitride, and the dielectric region may include silicon oxide.

[0036] Redistribution structure 62 is formed as a fan-out structure over device die 54. According to some embodiments, redistribution structure 62 includes dielectric layer 64 and RDL 66 in dielectric layer 64. The material, structure, and formation process of dielectric layer 64 and RDL 66 may be substantially the same as the material, structure, and formation process of dielectric layer 36 and RDL 38 in package 44' ( Figure 3 ), and will not be repeated here. The redistribution structure 62 may also include a metal bump 68 (the metal bump 68 may be a copper bump).

[0037] refer to Figure 5 , Figure 3 and Figure 4 The structures shown are bonded to each other, for example by bonding metal bump 68 to metal bump 40 via solder region 74, which includes solder region 42 ( Figure 3 ). The corresponding process is shown as Fig.35 Process 212 of the process flow 200 is shown. An underfill 59 is formed in the gap between the TSV die 20 ′ and the InFO package 50 .

[0038] Next, the carrier 30 is debonded from the underlying structure. The corresponding process is shown as Fig.35 The process 214 in the process flow 200 shown in FIG. In the subsequent process, as shown in FIG. Figure 6 As shown, a sealant 76 (such as a molding compound, a molded underfill, etc.) is formed to seal the TSV die 20' therein. Then, the sealant 76 is planarized, for example, by CMP or mechanical grinding, so that the metal bumps 26 are exposed. Subsequently, a metal bump 78 (which may include a copper bump, a solder area, etc.) is formed on the metal bump 26. The corresponding process is shown as Fig.35 The process 216 in the process flow 200 is shown. A redistribution structure (not shown) may or may not be formed between the metal bump 26 and the metal bump 78. If a redistribution structure is formed, the redistribution structure further includes a dielectric layer and an RDL located in the dielectric layer.

[0039] exist Figure 7 In Figure 6 The structure in FIG. 1 is attached to a carrier 80, which may be a glass carrier according to some embodiments. According to some embodiments, the metal bumps 78 may be attached to an adhesive 82. The corresponding process is shown as Fig.35The process 218 in the process flow 200 is shown. Then, Figure 6 The carrier 52 in the embodiment is separated from the device die 54 and the gap filling area 56. The corresponding process is shown as Fig.35 The process 220 in the process flow 200 is shown. The structure above the carrier 80 is hereinafter referred to as a reconstructed wafer 84, and the reconstructed wafer 84 may include a plurality of identical TSV dies 20'.

[0040] The reconstructed wafer 84 is then debonded from the carrier 80. The corresponding process is shown as Fig.35 Process 222 in process flow 200 is shown. Figure 8 Reconstructed wafer 84 is shown attached to dicing tape 86 , which is secured to frame 88 .

[0041] Next, the reconstructed wafer 84 is singulated in a sawing process to form a plurality of identical packages 84'. The corresponding process is shown as follows: Fig.35 Process 224 in process flow 200 is shown. Fig. 9 The detailed structure of the package 84 ′ is shown according to some embodiments.

[0042] Fig.10 An enlarged portion of a package 84 ′ is shown in accordance with some embodiments. Fig.10 The features shown can be obtained from Figures 1 to 9 It should be noted that one or more dielectric layers 36 may be formed, however, and RDL 38 may be located in dielectric layer 36 (see also Figure 6 and Figure 7 ). The dielectric layer 36 shown in the figure is marked as a dotted line to indicate that the dielectric layer 36 may be formed or not formed, and there may be no, one or more dielectric layers 36. According to some embodiments, Fig. 9 and Fig.10 As shown, the redistribution structure 62 formed on the device die 54 and the gap filling area 56 includes a dielectric layer 64 (including 64A and 64B), and the dielectric layer 64 can be formed of polyimide, PBO, etc. The RDL 66 in the redistribution structure 62 includes a via portion 66V (including portions 66VA and 66VB) located in the dielectric layer 64A and a line portion 66L (including portions 66LA and 66LB) located in the dielectric layer 64B. According to some embodiments, the RDL 66 is also referred to as an intermediate RDL (mRDL). The redistribution structure 62 also includes a metal bump 68 (including metal bumps 68A, 68B, 68C, and 68D), and according to some embodiments, the metal bump 68 can be an under-bump metal (UBM). The UBM 68 also includes a via portion 68V and a line / pad portion 68L.

[0043] Further references Fig.10, the TSV die 20' includes a substrate 22 (the substrate 22 may be a semiconductor substrate) and a TSV 24 penetrating the semiconductor substrate 22. The TSV 24 may include TSVs 24A', 24B', and 24C', which are collectively referred to as TSVs 24'. The TSVs 24 may also include TSVs 24A", 24B", and 24C", which are collectively referred to as TSVs 24". The TSV die 20' includes a backside RDL 38 (including RDLs 38A, 38B, and 38C), which may be in physical contact with the TSV 24. The TSV die 20' also includes metal bumps 40 (including metal bumps 40A, 40B, 40C, and 40D), which are bonded to the UBM 68 via solder regions 74.

[0044] According to some embodiments, TSV die 20' includes integrated circuit 94, which includes circuits 94A', 94B', 94C', 94A", 94B", 94C", 94A"', and 94B"'. Integrated circuit 94 can be formed on the front side (bottom surface as shown) of semiconductor substrate 22. Metal pads 92 including metal pads 92A', 92B', 92C', 92A", 92B", 92C", 92A"', and 92B"' are formed under TSVs 24A', 24B', 24C', 24A", 24B", 24C", 24A"', and 24B"', respectively, and contact TSVs 24A', 24B', 24C', 24A", 24B", 24C", 24A"', and 24B"'. Metal pads 92A', 92B', 92C', 92A", 92B", 92C", 92A"' and 92B"' may be electrically connected to integrated circuits 94A', 94B', 94C', 94A", 94B", 94C", 94A"' and 94B"' respectively through electrical paths (including metal lines and vias) 96A', 96B', 96C', 96A", 96B", 96C", 96A"' and 96B"' respectively.

[0045] According to some embodiments, metal pads 92A′, 92B′, 92C′, 92A″, 92B″, 92C″, 92A′″, and 92B′″ are located in the same metal layer of interconnect structure 23. According to alternative embodiments, metal pads 92A′, 92B′, 92C′, 92A″, 92B″, 92C″, 92A′″, and 92B′″ are located in different metal layers of interconnect structure 23 in any combination.

[0046] According to some embodiments, the backside RDL 38A has the function of integrating signals from (or conducted to) multiple TSVs 24' (including TSVs 24A', 24B', and 24C'). For example, TSVs 24A', 24B', and 24C' may be electrically connected to separate integrated circuits 94' (including integrated circuits 94A', 94B', and 94C') through signal paths 96' (including 96A', 96B', and 96C'). Integrated circuits 94A', 94B', and 94C' may be separate functional circuits including active devices (such as transistors) and / or passive devices (such as resistors, capacitors, etc.). Accordingly, although TSVs 24A', 24B', and 24C' are connected to different circuits, TSVs 24A', 24B', and 24C' share the same backside RDL 38A. This is different from conventional methods, in which each TSV is bonded to a separate upper backside RDL.

[0047] According to some embodiments, the backside RDL 38B has a function of integrating signals from (or conducted to) a plurality of TSVs 24" (including TSVs 24A", 24B", and 24C"). For example, TSVs 24A", 24B", and 24C" are electrically connected to separate integrated circuits 94" (including integrated circuits 94A", 94B", and 94C") through signal paths 96" (including 96A", 96B", and 96C"). Integrated circuits 94A", 94B", and 94C" are separate functional circuits including active devices (such as transistors) and / or passive devices (such as resistors, capacitors, etc.). Accordingly, although TSVs 24A", 24B", and 24C" are connected to different circuits, TSVs 24A", 24B", and 24C" share the same backside RDL 38B.

[0048] According to some embodiments, backside RDL 38C has a function of integrating signals from (or conducted to) a plurality of TSVs 24'" (including TSVs 24A'" and 24B'"). For example, TSVs 24A'" and 24B'" are electrically connected to separate integrated circuits 94'" (including integrated circuits 94A'" and 94B'") through signal paths 96'" (including 96A'" and 96B'"). Integrated circuits 94A'" and 94B'" are separate functional circuits including active devices (such as transistors) and / or passive devices (such as resistors, capacitors, etc.). Accordingly, although TSVs 24A'" and 24B'" are connected to different circuits, TSVs 24A'" and 24B'" share the same backside RDL 38C.

[0049] exist Fig.10In the embodiment, metal bumps 40 (including metal bumps 40A, 40B, 40C, and 40D) are formed and connected to the backside RDL 38 below.

[0050] In addition to integrating the underlying signals through the backside RDL 38, the signals on the backside RDL can be further integrated through the mRDL. For example, UBMs 68A and 68B are connected to the same mRDL 66A, and thus the mRDL 66A has the function of integrating the underlying UBMs 68A and 68B signals. Similarly, the mRDL 66B is connected to the two underlying UBMs 68C and 68D, and thus has the function of integrating their signals. Combining the integration functions of both the backside RDL 38 and the mRDL 66 can significantly reduce the number of metal bumps on the backside of the TSV die 20' and reduce the number of RDLs in the redistribution structure 62.

[0051] According to an alternative embodiment, backside RDL 38C may be split into two parts, rather than being bonded to both TSVs 24A'' and 24B'', wherein region 97 is not a metal region, but a dielectric region. Accordingly, the signals of TSVs 24A'' and 24B'' are not integrated through backside RDL 38C, but rather through

[0052] Fig.11 A bottom view of a feature line portion 66L, line portion 68L (including 68-L, 68L-2, 68L-3, and 68L-4), via portion 68V, via portion 66V, and copper via 83 are shown in accordance with some embodiments. These components have Fig. 9 and Fig.10 The plurality of trace portions 68L of the UBM 68 may be connected to different circuits 94 ( Fig.10 ), and their signals are integrated through the same mRDL 66 (including the via portion 66V and the line / pad portion 66L).

[0053] Fig.12 A bottom view of metal bumps 40, backside RDL 38, and TSV 24 are shown in accordance with some embodiments. These components also have Fig. 9 and Fig.10 The plurality of TSVs 24 may be connected to different circuits 94 ( Fig.10 ), and their signals are integrated through the same backside RDL 38.

[0054] According to some embodiments, the metal bump 40 has a pitch P1 greater than about 4 μm. The width W1 (or diameter) of the metal bump 40 may be in a range between about 2 μm and about 90 μm. The metal bump 40 may have any suitable top view or bottom view shape, including but not limited to circular, rectangular, oval, hexagonal, octagonal, etc.

[0055] Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B and Fig. 22C 24, backside RDL 38, and metal bump 40 according to various embodiments. Some reference numbers are marked to show corresponding components, which can be seen from Fig. 9 and Fig.10 A figure followed by the letter B or C is a bottom view of the corresponding figure with the same number but followed by the letter A. A figure numbered including the letter B and a figure numbered including the letter C illustrate different embodiments.

[0056] As shown in these figures, the backside RDL 38 may include a wide pad portion and an elongated trace portion that is narrower than the pad portion. The metal bump 40 may be located directly above the TSV 24, such as Fig.18A , Fig.18B and Fig.18C The metal bump 40 may be vertically offset from the TSV 24, as shown in the rest of these figures. According to some embodiments, the TSV 24 may be located directly below the pad portion of the backside RDL 38, for example, as shown in FIG. Fig.16A , Fig. 16B and Fig. 16CAccording to an alternative embodiment, TSV 24 may be located directly below the elongated trace portion of backside RDL 38, for example, Fig.13A , Fig. 13B and Fig. 13C And some other pictures shown.

[0057] It should also be understood that although the metal pads below the TSVs 24 are not shown, Fig.13A , Fig. 13B and FIG. 13C to FIG. 22A , Fig. 22B and Fig. 22C Each TSV 24 in the embodiment may have a separate metal pad, with Fig.10 The metal pads 92' and 92" shown in FIG. 1 are identical, and each TSV 24 may be connected to a separate integrated circuit different from the other TSVs 24, which are in FIG. Fig.10 Shown are integrated circuits 94' and 94".

[0058] Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A and Fig.26B According to some embodiments, Fig.10 Bottom views of the components shown in FIG. These figures show exemplary ratios of components connected to the same mRDL 66. Fig.23A and Fig. 23B In FIG. 4 , the ratio of the number of metal bumps 40 to the number of RDL trace portions 68L is 4:4 (ie, 1:1). Fig.24A and Fig. 24B In FIG. 4 , the ratio of the number of metal bumps 40 to the number of RDL trace portions 68L is 2:4 (ie, 1:2). Fig.25A and Fig.25B In FIG. 6 , the ratio of the number of metal bumps to the number of RDL trace portions 68L is 4:2 (i.e., 2:1). Fig.26A and Fig.26B In FIG. 6 , the ratio of the number of metal bumps to the number of RDL trace portions 68L is 8:2 (ie, 4:1). It should be understood that any other suitable ratios may also be considered.

[0059] Fig.27A and Fig.27B1 and 2 show a cross-sectional view and a top view of a package 84' according to some embodiments of the present disclosure, respectively. According to these embodiments, in addition to the signal integration scheme implemented by the backside RDL 38 and the mRDL 66 (as discussed in the previous embodiments), a dummy bump 40D is formed just above the seal ring 102 to improve the robustness of the bonding. It should be understood that although not shown in detail, the following embodiments also implement the Fig. 9 and Fig.10 The signal integration scheme shown is not shown or discussed in detail, but the details can be found in the discussion of the previous embodiments.

[0060] like Fig.27A and Fig.27B As shown, package 84' includes InFO package 50 and TSV die 20' bonded to InFO package 50. According to some embodiments, signal TSV 24 and functional circuits (such as Fig.10 94' and 94" in FIG. 1 ) are formed in an inner region of the TSV die 20' surrounded by the seal ring 102. In the embodiments discussed later, the letter "D" may be added to some components to indicate that these components are dummy components that have no electrical function. For example, the dummy components include a dummy bump 40D, a dummy backside RDL 38D, a dummy UBM 68D, a dummy mRDL 66D, a dummy TSV 24D, etc. The dummy components may be electrically floating.

[0061] Dummy bump 40D is formed on dummy backside RDL 38D. According to some embodiments, seal ring 102 is located directly below dummy bump 40D and backside RDL 38D and overlaps dummy bump 40D and backside RDL 38D. According to some embodiments, features (such as vias) in dashed area 104 may not be formed, so that dummy bump 40D is electrically isolated from device die 54.

[0062] According to some embodiments, dummy TSV 24D may be formed directly below dummy bump 40D and backside RDL 38D and connected to dummy bump 40D and backside RDL 38D. According to an alternative embodiment, dummy TSV 24D is not formed. Accordingly, dummy TSV 24D is shown as a dotted line to indicate that dummy TSV 24D may or may not be formed.

[0063] According to some embodiments, the sealing ring 102 is formed in the interconnect structure 23 of the TSV die 20'. For example, each sealing ring 102 may include a plurality of metal wire rings and a plurality of via rings, and the plurality of via rings are located between and combined with the corresponding upper and lower metal wire rings. Each metal wire ring and via ring may be a solid metal ring, and the corresponding sealing ring 102 is also a solid metal ring. The sealing ring 102 may extend into all low-k dielectric layers in the interconnect structure 23, and may or may not extend into the interlayer dielectric layer of the TSV die 20'. The sealing ring 102 is located at the peripheral area of ​​the TSV die 20' and surrounds the signal TSV 24 and the integrated circuit 94 ( Fig.10 ).

[0064] Fig.27B Shows Fig.27A . The outer edges of the InFO package 50, TSV die 20', and device die 54 are shown. According to some embodiments, the InFO package 50 is larger than the device die 54, which is larger than the TSV die 20'. The sealing ring 102 forms a ring in which a plurality of dummy bumps 40D overlap with the sealing ring 102 (in the cross-sectional view). According to some embodiments, the dummy bumps 40D are located at the corner areas of the TSV die 20' and the sealing ring 102.

[0065] Fig.28A and Fig.28B A cross-sectional view and a top view of a package 84' according to an optional embodiment are shown respectively. These embodiments are similar to Fig.27A and Fig.27B The embodiment shown differs in that the device die 54 and the TSV die 20' have their edges aligned. On the other hand, the InFO package 50 is larger than the TSV die 20' and the device die 54. The dummy bumps 40D are located at the corner areas of the TSV die 20' and the seal ring 102.

[0066] Fig.29A and Fig.29B 1 and 2 show a cross-sectional view and a top view of a package 84' according to some other optional embodiments. Fig.27A and Fig.27B The embodiment shown is different in that the InFO package 50 is larger than the TSV die 20 ′, which in turn is larger than the device die 54 . The dummy bumps 40D are located at the corner regions of the TSV die 20 ′ and the seal ring 102 .

[0067] Fig.30 According to some embodiments Fig.29A, where both the InFO package 50 and the TSV die 20 ′ are larger than the device die 54 . Fig.30 Shows Fig.29A In some embodiments, the dummy bump 40D, dummy UBM 68D, and dummy RDL 66D extend laterally beyond the right edge of the device die 54 and are located directly below the gap fill region 56. The dummy bump 40D overlaps the seal ring 102 in the TSV die 20'. This further improves the robustness of the joint. The dummy TSV 24D is not shown (see Fig.29A ), which may (or may not) exist in Fig.30 In the structure shown.

[0068] Figures 31A to 31E A top view of the dummy bump 40D relative to the size of the InFO package 50, TSV die 20', and device die 54 according to some embodiments is shown. The illustrated example shows that the TSV die 20' has the same size as the device die 54, while both have smaller sizes than the InFO package 50. However, in other embodiments, the size of each of the TSV die 20', the device die 54, and the InFO package 50 can be greater than, equal to, or less than the other size in any combination. Therefore, FIG. 31A to FIG. 31E Each of the embodiments shown in Fig.27B , Fig.28B and Fig.29B Each of the embodiments shown in .

[0069] exist FIG. 31A to FIG. 31E In the embodiment, the sealing rings 102 are not shown, but they are still present and overlap with the dummy bumps 40D. The size and shape of the sealing rings 102 may be similar to Fig.27B , Fig.28B and Fig.29B Same size and shape as shown in .

[0070] like Fig.31A , Fig.31B and Fig.31C As shown, the total number of dummy bumps 40D at each corner of the TSV die 20' may be any number, such as 1, 2, 3, 5, 6, etc. The distribution of the dummy bumps 40D at the corners may be symmetrical, such as Fig.31A , Fig.31B and Fig.31C Optionally, the dummy bumps 40D at different corners may have an asymmetric arrangement relative to each other, such as Fig.31D , Fig.31E and Fig.31F shown.

[0071] Figure 31G , Fig.31H and Fig.31I Embodiments of dummy bumps 40D are shown. According to these embodiments, dummy bumps 40D are aligned in a ring. There may be one ring formed by dummy bumps 40D, two rings formed by dummy bumps 40D, or more rings.

[0072] Fig.32 , Fig.33 and Fig.34 Some applications that may be incorporated with the package 84' according to some embodiments are shown. Fig.32 , the package 84' is bonded to the package substrate 110. Another package 112 including a memory die / package 114 bonded to the package substrate 116 is further located above the package substrate 110 and bonded to the package substrate 110 via solder regions 118. The solder regions 118 and the package 84' are further sealed in an encapsulant 125, which may be a molding compound.

[0073] refer to Fig.33 , the package 84' is bonded to the package substrate 110, on which the multi-chip package 120 including a plurality of stacked device dies is bonded. According to these embodiments, the device die 54 and the corresponding InFO package 50 can be vertically offset from the TSV die 20'. According to some embodiments, a through-hole 122 can be formed to directly connect the InFO package 50 to the package substrate 110.

[0074] refer to Fig.34 , the package 84' is bonded to the package substrate 110. Another package 112 including a memory die / package 114 bonded to the package substrate 116 is further located above the package substrate 110 and bonded to the package substrate 110 through a through hole 124. The through hole 124 and the package 84' are further sealed in an encapsulant 125, which may be a molding compound.

[0075] In the above embodiments, some processes and components for forming three-dimensional (3D) packages are discussed according to some embodiments of the present disclosure. Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of 3D packages or 3DIC devices. For example, the test structure may include a test pad formed in a redistribution layer or on a substrate, the test pad allowing testing of the 3D package or 3DIC, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that combines intermediate verification of known good dies to increase yield and reduce costs.

[0076] Embodiments of the present disclosure have some advantageous features. By using the backside RDL of the TSV die to integrate signals, fewer metal bumps are required because multiple TSVs can share the same backside RDL and / or metal bumps above. Signals can also be integrated through mRDL to further reduce the number of RDLs. In addition, by forming a dummy bump just above the seal ring, the reliability of the bonding is improved.

[0077] According to some embodiments of the present disclosure, a method includes forming a tube core, forming the tube core includes forming a first through hole and a second through hole extending from the front side of the semiconductor substrate into the semiconductor substrate, wherein the first through hole and the second through hole are respectively connected to a first integrated circuit device and a second integrated circuit device in the tube core; performing a backside grinding process to expose the first through hole and the second through hole; and forming a backside redistribution line, the backside redistribution line being physically coupled to both the first through hole and the second through hole.

[0078] In an embodiment, the method further comprises bonding the die to a package assembly, wherein the package assembly comprises intermediate redistribution lines, wherein the intermediate redistribution lines are electrically connected to backside redistribution lines of the die and to a third through via penetrating the semiconductor substrate, and wherein the third through via is electrically connected to a third integrated circuit. In an embodiment, the package assembly comprises an under bump metallization physically contacting the solder region, wherein the metal bump of the die is located between the solder region and the backside redistribution lines and is physically bonded to the solder region and the backside redistribution lines.

[0079] In an embodiment, the first integrated circuit device and the backside redistribution line are located on opposite sides of the semiconductor substrate. In an embodiment, the method further comprises: after the backside grinding process, recessing the first through hole and the second through hole so that the ends of the first through hole and the second through hole protrude from the semiconductor substrate; and forming a dielectric isolation layer, wherein the ends are located in the dielectric isolation layer. In an embodiment, the backside redistribution line physically contacts the dielectric isolation layer. In an embodiment, the backside redistribution line includes a metal pad and an elongated metal line connected to the metal pad, and the metal pad physically contacts both the first through hole and the second through hole.

[0080] In an embodiment, the backside redistribution line includes a metal pad and an elongated metal line connected to the metal pad, and the elongated metal line physically contacts both the first through hole and the second through hole. In an embodiment, the method also includes forming a plurality of metal bumps that physically contact the backside redistribution line. In an embodiment, the method also includes forming a plurality of solder areas that contact the plurality of metal bumps. In an embodiment, the method also includes forming a sealing ring in the die; and forming a dummy bump that overlaps the sealing ring. In an embodiment, the method also includes joining the solder area that contacts the dummy bump.

[0081] According to some embodiments of the present disclosure, a structure includes a tube core, which includes a semiconductor substrate; a first integrated circuit device and a second integrated circuit device located on the front side of the semiconductor substrate; a first through hole and a second through hole penetrating the semiconductor substrate, wherein the first through hole and the second through hole are respectively connected to the first integrated circuit device and the second integrated circuit device; and a first back side redistribution line located on the back side of the semiconductor substrate, wherein the first back side redistribution line physically contacts both the first through hole and the second through hole.

[0082] In an embodiment, the structure further comprises a second backside redistribution line located on the backside of the semiconductor substrate; a first metal bump and a second metal bump respectively contacting the first backside redistribution line and the second backside redistribution line; and a first solder region and a second solder region respectively contacting the first metal bump and the second metal bump. In an embodiment, the structure further comprises a first under bump metal and a second under bump metal respectively contacting the first solder region and the second solder region; and an intermediate redistribution line contacting both the first under bump metal and the second under bump metal.

[0083] In an embodiment, the structure further comprises a first metal pad and a second metal pad located on the front side of the semiconductor substrate and contacting the first through via and the second through via, respectively. In an embodiment, the structure further comprises a first electrical path and a second electrical path electrically connecting the first metal pad and the second metal pad to the first integrated circuit device and the second integrated circuit device, respectively.

[0084] According to some embodiments of the present disclosure, a structure includes a die, the die including a semiconductor substrate; a first integrated circuit and a second integrated circuit located at the front side of the semiconductor substrate; a dielectric isolation layer contacting the back side of the semiconductor substrate; and a backside redistribution line contacting the dielectric isolation layer, wherein the backside redistribution line electrically connects the first integrated circuit to the second integrated circuit. In an embodiment, the structure also includes a first metal pad and a second metal pad located on the front side of the semiconductor substrate and electrically connected to the first integrated circuit and the second integrated circuit, respectively; and a first through-hole and a second through-hole physically bonded to the first metal pad and the second metal pad, respectively, wherein the first through-hole and the second through-hole penetrate the semiconductor substrate and are electrically connected to the first integrated circuit and the second integrated circuit through the first metal pad and the second metal pad, respectively. In an embodiment, the structure also includes a metal bump located on the backside redistribution line; a solder area located on the metal bump; and a package bonded to the solder area.

[0085] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Forming a tube core, forming the tube core includes: forming a first through-hole and a second through-hole extending from a front side of a semiconductor substrate into the semiconductor substrate, wherein the first through-hole and the second through-hole are connected to a first integrated circuit device and a second integrated circuit device in the die, respectively; performing a backside grinding process to expose the first through hole and the second through hole; and A backside redistribution line is formed that is physically coupled to both the first through-via and the second through-via.

2. The method of claim 1 , further comprising bonding the die to a package assembly, wherein The package assembly includes an intermediate redistribution line, wherein the intermediate redistribution line is electrically connected to the backside redistribution line of the die and a third through via penetrating the semiconductor substrate, and wherein the third through via is electrically connected to a third integrated circuit.

3. The method according to claim 2, wherein: The package assembly includes an under bump metallization physically contacting a solder region, wherein metal bumps of the die are located between and physically bonded to the solder region and the backside redistribution lines.

4. The method according to claim 1, wherein: The first integrated circuit device and the backside redistribution line are located on opposite sides of the semiconductor substrate.

5. The method according to claim 1, further comprising, after the backside grinding process, recessing the first through hole and the second through hole so that ends of the first through hole and the second through hole protrude from the semiconductor substrate; and A dielectric isolation layer is formed, wherein The end portion is located in the dielectric isolation layer.

6. The method according to claim 5, wherein: The backside redistribution line physically contacts the dielectric isolation layer.

7. The method according to claim 1, wherein: The backside redistribution line includes a metal pad and an elongated metal line connected to the metal pad, and the metal pad physically contacts both the first through-via and the second through-via.

8. The method according to claim 1, wherein: The backside redistribution line includes a metal pad and an elongated metal line connected to the metal pad, and the elongated metal line physically contacts both the first through-via and the second through-via.

9. A semiconductor structure comprising: A tube core, the tube core comprising: Semiconductor substrate; a first integrated circuit device and a second integrated circuit device located on the front side of the semiconductor substrate; A first through hole and a second through hole penetrate the semiconductor substrate, wherein the first through hole and the second through hole are connected to the first integrated circuit device and the second integrated circuit device, respectively; and A first backside redistribution line is located on a backside of the semiconductor substrate, wherein the first backside redistribution line physically contacts both the first through via and the second through via.

10. A semiconductor structure comprising: A tube core, the tube core comprising: Semiconductor substrate; A first integrated circuit and a second integrated circuit are located at the front side of the semiconductor substrate; a dielectric isolation layer contacting a back side of the semiconductor substrate; and A backside redistribution line contacts the dielectric isolation layer, wherein the backside redistribution line electrically connects the first integrated circuit to the second integrated circuit.

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