High-density rewiring method for chip packaging

Abstract

The invention discloses a high-density rewiring method for chip packaging. The method comprises the following steps: coating a seed layer with a first photoresist layer; performing first exposure and development operation on the first photoresist layer, and forming a first electroplating pattern on the first photoresist layer; performing electroplating operation on the first electroplating pattern, and forming a first electroplating layer on the seed layer; coating a photoresist layer on the first photoresist layer and the first electroplated layer, or removing the remaining first photoresist layer and coating a photoresist layer on the seed layer and the first electroplated layer to form a second photoresist layer; performing second exposure and development operation on the second photoresist layer, and forming a second electroplating pattern on the second photoresist layer; performing electroplating operation on the second electroplating pattern, and forming a second electroplating layer on the seed layer; and removing the residual second photoresist layer and the seed layer which is not covered by the first electroplated layer and the second electroplated layer to obtain a rewiring layer. According to the invention, more lines can be arranged under the condition of the same area.

Description

Technical Field

[0001] The present invention relates to the field of rewiring technology, and in particular to a high-density rewiring method for chip packaging. Background Art

[0002] Traditional rewiring methods are only applicable to low-density rewiring methods. The reason is that in the traditional rewiring method process, if more lines need to be arranged while the total wiring area and the thickness and area of ​​the electroplating layer remain unchanged, then after the electroplating pattern is formed on the photoresist, the more wiring there are, the thinner the photoresist layer around the unplated pattern will be. This will cause the photoresist layer to collapse easily, and ultimately a high-quality rewiring layer cannot be formed.

[0003] In order to solve the above problems, the applicant has developed a high-density redistribution method for chip packaging to solve the above problems. Summary of the invention

[0004] The present invention provides a high-density rewiring method for chip packaging to solve the problem that the existing rewiring method cannot ensure high-density rewiring with high rewiring quality.

[0005] The present invention achieves the above-mentioned purpose through the following technical solutions: A high-density rewiring method for chip packaging, comprising: laying a seed layer on the substrate layer; coating a first photoresist layer on the seed layer; Performing a first exposure and development operation on the first photoresist layer to form a first electroplating pattern on the first photoresist layer; Performing an electroplating operation on the first electroplating pattern to form a first electroplating layer on the seed layer; Coating a photoresist layer on the first photoresist layer and the first electroplating layer to form a second photoresist layer, or removing the remaining first photoresist layer and coating a photoresist layer on the seed layer and the first electroplating layer to form a second photoresist layer; Performing a second exposure and development operation on the second photoresist layer to form a second electroplating pattern on the second photoresist layer, wherein the second electroplating pattern is located in a region of the second photoresist layer surrounded by the first electroplating pattern; performing an electroplating operation on the second electroplating pattern to form a second electroplating layer on the seed layer; The remaining second photoresist layer and the seed layer not covered by the first electroplating layer and the second electroplating layer are removed to obtain a redistribution layer.

[0006] Furthermore, the ratio of the height of the second photoresist layer to the distance between the second electroplating layer and the first electroplating layer is greater than 1:1.

[0007] Furthermore, the ratio of the height of the second photoresist layer to the distance between the second electroplating layer and the first electroplating layer is greater than 3:1.

[0008] Furthermore, the ratio of the height of the second photoresist layer to the distance between the second electroplating layer and the first electroplating layer is greater than 5:1.

[0009] Furthermore, a height of the second electroplating layer is greater than a height of the first electroplating layer.

[0010] The beneficial effects of the present invention are: The high-density rewiring method for chip packaging proposed by the present invention solves the problem that the existing rewiring method cannot ensure high-density rewiring with high rewiring quality. It can arrange more lines under the same area conditions, and photoresist collapse will not occur during the rewiring process. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is one of the method flow charts of a high-density rewiring method for chip packaging in this application; Figure 2 This is the second method flow chart of a high-density redistribution method for chip packaging in the present application. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0013] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0015] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. These directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0016] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0017] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0018] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings.

[0019] Figure 1 and Figure 2 In the figure, PR represents a photoresist layer, seed represents a seed layer, the substrate layer may be made of a glass material or a silicon material, and Metal represents a metal deposition layer formed by electroplating.

[0020] Example 1 like Figure 1 As shown, a high-density redistribution method for chip packaging comprises: laying a seed layer on the substrate layer; coating a first photoresist layer on the seed layer; Performing a first exposure and development operation on the first photoresist layer to form a first electroplating pattern on the first photoresist layer; Performing an electroplating operation on the first electroplating pattern to form a first electroplating layer on the seed layer; Coating a photoresist layer on the first photoresist layer and the first electroplating layer to form a second photoresist layer; Performing a second exposure and development operation on the second photoresist layer to form a second electroplating pattern on the second photoresist layer, wherein the second electroplating pattern is located in a region of the second photoresist layer surrounded by the first electroplating pattern; performing an electroplating operation on the second electroplating pattern to form a second electroplating layer on the seed layer; The remaining second photoresist layer and the seed layer not covered by the first electroplating layer and the second electroplating layer are removed to obtain a redistribution layer.

[0021] Example 2 like Figure 2 As shown, A high-density rewiring method for chip packaging, comprising: laying a seed layer on the substrate layer; coating a first photoresist layer on the seed layer; Performing a first exposure and development operation on the first photoresist layer to form a first electroplating pattern on the first photoresist layer; Performing an electroplating operation on the first electroplating pattern to form a first electroplating layer on the seed layer; Removing the remaining first photoresist layer and coating a photoresist layer on the seed layer and the first electroplating layer to form a second photoresist layer; Performing a second exposure and development operation on the second photoresist layer to form a second electroplating pattern on the second photoresist layer, wherein the second electroplating pattern is located in a region of the second photoresist layer surrounded by the first electroplating pattern; performing an electroplating operation on the second electroplating pattern to form a second electroplating layer on the seed layer; The remaining second photoresist layer and the seed layer not covered by the first electroplating layer and the second electroplating layer are removed to obtain a redistribution layer.

[0022] It can be seen from the above-mentioned Examples 1 and 2 that the high-density rewiring method for chip packaging of the present invention solves the problem that the existing rewiring method cannot guarantee high rewiring quality of high-density rewiring, breaks through the limit of materials, and realizes the arrangement of more lines under the same area conditions, and there will be no photoresist collapse during the rewiring process. The two electroplating operations allow sparse areas to be electroplated for a short time and then dense areas to be electroplated for a long time, thereby achieving equal heights of iso and dense areas, achieving adjustable ISO and Dense current densities of the electroplating process, and achieving better electroplating uniformity.

[0023] In some embodiments, the ratio of the height of the second photoresist layer to the distance between the second electroplating layer and the first electroplating layer is greater than 1: 1. Thus, the material limit under this ratio condition is broken through, and more circuits can be arranged under the same area condition.

[0024] In some embodiments, the ratio of the height of the second photoresist layer to the distance between the second electroplating layer and the first electroplating layer is greater than 3: 1. Thus, the material limit under this ratio condition is broken through, and more circuits can be arranged under the same area condition.

[0025] In some embodiments, the ratio of the height of the second photoresist layer to the distance between the second electroplating layer and the first electroplating layer is greater than 5: 1. Thus, the material limit under this ratio condition is broken through, and more circuits can be arranged under the same area condition.

[0026] In some embodiments, the height of the second electroplating layer is greater than the height of the first electroplating layer, thereby achieving different heights of different circuits.

[0027] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A high-density rewiring method for chip packaging, characterized in that: include: laying a seed layer on the substrate layer; coating a first photoresist layer on the seed layer; Performing a first exposure and development operation on the first photoresist layer to form a first electroplating pattern on the first photoresist layer; Performing an electroplating operation on the first electroplating pattern to form a first electroplating layer on the seed layer; Coating a photoresist layer on the first photoresist layer and the first electroplating layer to form a second photoresist layer, or removing the remaining first photoresist layer and coating a photoresist layer on the seed layer and the first electroplating layer to form a second photoresist layer; Performing a second exposure and development operation on the second photoresist layer to form a second electroplating pattern on the second photoresist layer, wherein the second electroplating pattern is located in a region of the second photoresist layer surrounded by the first electroplating pattern; performing an electroplating operation on the second electroplating pattern to form a second electroplating layer on the seed layer; The remaining second photoresist layer and the seed layer not covered by the first electroplating layer and the second electroplating layer are removed to obtain a redistribution layer.

2. A high-density rewiring method for chip packaging according to claim 1, characterized in that: A ratio of a height of the second photoresist layer to a distance between the second electroplating layer and the first electroplating layer is greater than 1:

1.

3. A high-density rewiring method for chip packaging according to claim 2, characterized in that: A ratio of a height of the second photoresist layer to a distance between the second electroplating layer and the first electroplating layer is greater than 3:

1.

4. A high-density rewiring method for chip packaging according to claim 3, characterized in that: A ratio of a height of the second photoresist layer to a distance between the second electroplating layer and the first electroplating layer is greater than 5:

1.

5. The high-density rewiring method for chip packaging according to claim 1, characterized in that: The height of the second electroplating layer is greater than the height of the first electroplating layer.

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