Semiconductor device and chip flexible packaging method

Abstract

The embodiment of the invention discloses a semiconductor device and a chip flexible packaging method, the semiconductor device comprises a chip, a first flexible thin film layer, a second flexible thin film layer and an interconnection assembly, the chip is packaged through the first flexible thin film layer and the second flexible thin film layer, the chip can be well wrapped, the lead-out of chip I / O can be realized, and the reliability of the chip is improved. The interconnection assembly is connected to the chip to realize communication of the chip, the back-end process of the semiconductor device can support and complete a chip flip-chip bonding process, and the semiconductor device has bending capability, can improve the defects of poor machinability, fragility in a bending process, high interconnection risk and the like of an ultrathin chip, and can improve the reliability of the chip. The finally formed semiconductor device has the advantages of being light, thin, high in reliability, simple in interconnection interface and the like, and the whole process does not involve non-standard processes or equipment and can adopt existing mature systems.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device and a chip flexible packaging method. Background Art

[0002] According to the mechanical properties of Si wafers, when the wafer thickness is less than 50um, the silicon-based material will show flexible and bendable characteristics. Utilizing this property, the chip can be packaged with a certain degree of flexibility. At present, the industrial application of ultra-thin chips, especially in the application scenarios in a bent state, has problems such as fragility, poor processability and reliability, and high difficulty in I / O interconnection. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0004] To this end, a first aspect of the present invention provides a semiconductor device.

[0005] A second aspect of the present invention provides a chip flexible packaging method.

[0006] In view of this, according to a first aspect of an embodiment of the present application, a semiconductor device is provided, comprising:

[0007] chip;

[0008] a first flexible film layer and a second flexible film layer, wherein the chip is arranged between the first flexible film layer and the second flexible film layer;

[0009] An interconnection component, at least a portion of which is connected to the chip through the second flexible film layer.

[0010] In a feasible implementation manner, the chip is embedded in the first flexible film layer, so that the first flexible film layer wraps at least a portion of the peripheral side of the chip.

[0011] In a feasible implementation manner, a ratio of the thickness of the first flexible film layer to the thickness of the chip is greater than or equal to 0.5.

[0012] In a feasible implementation, the interconnection component includes:

[0013] a redistribution layer, a portion of which passes through the second flexible film layer and is connected to the chip;

[0014] A solder ball is connected to the redistribution layer.

[0015] In a feasible implementation manner, the semiconductor device further includes:

[0016] A passivation dielectric layer is disposed on the redistribution layer and / or between adjacent redistribution layers.

[0017] In a feasible implementation manner, the thickness of the chip is less than or equal to 50 um.

[0018] In a feasible implementation manner, the first flexible film layer is made of a photosensitive film; and / or

[0019] The second flexible film layer is made of a photosensitive film.

[0020] In a feasible implementation manner, the distance between the outer edge contour of the first flexible film layer and the chip is 100 um to 500 um.

[0021] In a feasible implementation manner, the first flexible film layer and the second flexible film layer are made of the same material.

[0022] In a feasible implementation manner, the thickness of the second flexible film layer is greater than the thickness of the first flexible film layer.

[0023] According to a second aspect of an embodiment of the present application, a chip flexible packaging method is provided, which is used to prepare a semiconductor device as described in any of the above technical solutions. The chip flexible packaging method includes:

[0024] providing a carrier board on which a first flexible film layer is disposed;

[0025] Pasting a chip onto the first flexible film layer, and embedding at least a portion of the chip into the first flexible film layer;

[0026] connecting a second flexible film layer to the chip and the first flexible film layer;

[0027] preparing the interconnect assembly;

[0028] The carrier is removed to obtain a packaged semiconductor device.

[0029] In a feasible implementation manner, the step of preparing the interconnection assembly comprises:

[0030] Performing photolithography on the second flexible film layer to prepare I / O openings interconnected with the chip, and curing the second flexible film layer;

[0031] Performing metallization deposition on the second flexible film layer to form a first metal seed layer;

[0032] Based on the first metal seed layer, forming a redistribution layer;

[0033] Solder balls are formed on the redistribution layer.

[0034] Compared with the prior art, the present invention has at least the following beneficial effects:

[0035] The semiconductor device provided in the embodiment of the present application includes a chip, a first flexible film layer, a second flexible film layer and an interconnection component. The chip is packaged by the first flexible film layer and the second flexible film layer, which can not only wrap the chip well, but also realize the lead-out of the chip I / O. The chip communication is realized by connecting to the chip through the interconnection component, so that the back-end process of the semiconductor device can support the completion of the chip flip-chip welding process, and has the bendability, which can improve the shortcomings of ultra-thin chips such as poor machinability, fragility during the bending process and high interconnection risk. The finally formed semiconductor device has the advantages of lightness, high reliability and simple interconnection interface, and the whole set of processes does not involve non-standard processes or equipment, and can adopt existing mature systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0037] Figure 1 A schematic structural diagram of a semiconductor device according to an embodiment of the present application;

[0038] Figures 2a to 2j A schematic structural diagram of a semiconductor device manufacturing process according to an embodiment of the present application;

[0039] Figure 3 A schematic flowchart of the steps of a chip flexible packaging method according to an embodiment of the present application.

[0040] The corresponding relationship between the reference numerals and the component names is as follows:

[0041] 110 chip, 120 first flexible film layer, 130 second flexible film layer, 140 interconnection component, 150 passivation dielectric layer, 160 carrier board, 170 temporary adhesive layer, 180 first metal seed layer, 190 second metal seed layer;

[0042] 141 redistribution layer, 142 solder ball. DETAILED DESCRIPTION

[0043] In order to better understand the above-mentioned technical scheme, the technical scheme of the embodiments of the present application is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical scheme of the embodiments of the present application, rather than limitations on the technical scheme of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments may be combined with each other.

[0044] The embodiments of the present application take into account that the ultra-thin chips in traditional technologies have problems such as reliability, I / O lead-out, and subsequent interconnection methods, such as: 1) The surface and side walls of ultra-thin chips (below 50um) are prone to defects such as edge collapse or hidden cracks during the cutting process, which can easily lead to chip breakage or passivation layer cracking and other failures in the subsequent process; 2) Ultra-thin chips (below 50um) have a certain degree of flexibility. In scenarios where flexibility is required, since silicon is a rigid material and does not have flexibility, it is still brittle even after thinning, and the risk of bending is extremely high; 3) The interconnection interface of ultra-thin chips is relatively simple. Due to thickness and excessive fragility, solutions such as bumping or ball planting have greater risks. The wire bonding process is prone to defects such as chip breaking or pad tearing, and the interconnection process has greater risks.

[0045] like Figure 1 As shown, according to a first aspect of an embodiment of the present application, a semiconductor device is proposed, comprising: a chip 110; a first flexible film layer 120 and a second flexible film layer 130, the chip 110 is arranged between the first flexible film layer 120 and the second flexible film layer 130; an interconnection component 140, at least a part of the interconnection component 140 is connected to the chip 110 through the second flexible film layer 130.

[0046] The semiconductor device provided in the embodiment of the present application includes a chip 110, a first flexible film layer 120, a second flexible film layer 130 and an interconnection component 140. The chip 110 is packaged by the first flexible film layer 120 and the second flexible film layer 130, which can not only well wrap the chip 110 and ensure the reliability of the bending of the chip 110, but also realize the lead-out of the chip I / O. The interconnection component 140 is connected to the chip 110 to realize the communication of the chip 110, so that the back-end process of the semiconductor device can support the completion of the flip-chip welding process of the chip 110, and has the bendability, which can improve the shortcomings of the ultra-thin chip 110 such as poor machinability, fragility during the bending process and high interconnection risk. The finally formed semiconductor device has the advantages of being light, thin, highly reliable and having a simple interconnection interface, and the whole set of processes does not involve non-standard processes or equipment, and can adopt existing mature systems.

[0047] like Figure 1As shown, in a feasible implementation manner, the chip 110 is embedded in the first flexible film layer 120 , so that the first flexible film layer 120 wraps at least a portion of the peripheral side of the chip 110 .

[0048] In this technical solution, a configuration method of the chip 110 is further provided. The chip 110 is embedded in the first flexible film layer 120 so that the first flexible film layer 120 wraps at least a portion of the peripheral area of ​​the chip 110. Such a configuration, on the one hand, enables the first flexible film layer 120 to better protect the chip 110; on the other hand, it is convenient to establish a connection relationship between the first flexible film layer 120 and the second flexible film layer 130, which can improve the packaging effect of the semiconductor device.

[0049] like Figure 1 As shown, in a feasible implementation manner, the ratio of the thickness of the first flexible film layer 120 to the thickness of the chip 110 is greater than or equal to 0.5.

[0050] In this technical solution, a relationship between the first flexible film layer 120 and the chip 110 is further provided, and the ratio of the thickness of the first flexible film layer 120 to the chip 110 is greater than or equal to 0.5. Such a setting ensures that the chip 110 can be embedded in the first flexible film layer 120, and the chip 110 will not touch the bottom of the first flexible film layer 120, further ensuring the packaging quality and facilitating the bending of the first flexible film layer 120.

[0051] like Figure 1 As shown, in a feasible implementation, the interconnection component 140 includes: a redistribution layer 141 (RDL line, ReDistribution Layer), a portion of the redistribution layer 141 passes through the second flexible film layer 130 and is connected to the chip 110; a solder ball 142, and the solder ball 142 is connected to the redistribution layer 141.

[0052] In this technical solution, the structural composition of the interconnection component is further provided. The interconnection component 140 may include a redistribution layer 141 and a solder ball 142. Based on this, the semiconductor device provided in the embodiment of the present application adopts a flexible film process to construct a package structure. The first flexible film layer 120 and the second flexible film layer 130 are used to complete the package packaging structure on the front and back sides of the chip 110, and then the Fan-in pad redistribution and solder ball 142 preparation process are performed on the front side to form an interconnection component. Finally, the ultra-thin chip 110 is released after the package through laser bonding and debonding processes to complete the product packaging, thereby ensuring the communication capability of the semiconductor device. After the first flexible film layer 120 and the second flexible film layer 130 are cured, the semiconductor device provided in the embodiment of the present application constructs an RDL wiring layer by adopting a method combining a permanent dry film and a flexible substrate, which can effectively reduce the influence of warping, the complexity of the process, and the requirements for device performance, and can achieve a flat surface on the front side of the chip 110.

[0053] like Figure 1 As shown, in a feasible implementation manner, the semiconductor device further includes: a passivation dielectric layer 150 , and the passivation dielectric layer 150 is disposed on the redistribution layer 141 and / or located between adjacent redistribution layers 141 .

[0054] In this technical solution, the semiconductor device may further include a passivation dielectric layer 150 to facilitate the preparation of the solder ball 142. The materials used to prepare the passivation dielectric layer 150 may include photosensitive polyimide, benzocyclobutene (BCB) and thermosetting polymer (SU8).

[0055] In a feasible implementation manner, the thickness of the chip 110 is less than or equal to 50 um.

[0056] In this technical solution, a style of chip 110 is further provided, and the thickness of chip 110 is less than or equal to 50um. Such a configuration enables chip 110 to exhibit flexible and bendable properties, and is used in combination with the first flexible film layer 120 and the second flexible film layer 130, so that the semiconductor device can be bent.

[0057] In a feasible implementation manner, the first flexible film layer 120 is made of a photosensitive film; and / or the second flexible film layer 130 is made of a photosensitive film.

[0058] In this technical solution, the material of the first flexible film layer 120 and the second flexible film layer 130 is further provided. The first flexible film layer 120 and the second flexible film layer 130 can be made of photosensitive films. Such a configuration can change the shapes of the first flexible film layer 120 and the second flexible film layer 130 by adjusting the curing temperature. On the one hand, it is convenient to embed the chip 110 into the first flexible film layer 120; on the other hand, it is convenient to lead out I / O and to prepare interconnection components; on another hand, after the chip 110 is packaged by the first flexible film layer 120 and the second flexible film layer 130, the semiconductor device has a certain flexibility while taking into account the mechanical strength.

[0059] In a feasible implementation manner, the distance between the outer edge contour of the first flexible film layer 120 and the chip 110 is 100 um to 500 um.

[0060] In this technical solution, a size relationship between the first flexible film layer 120 and the chip 110 is further provided. The size of the first flexible film layer 120 is larger than the chip 110, so as to facilitate the embedding of the chip 110 into the first flexible film layer 120. At the same time, the distance between the outer edge contour of the first flexible film layer 120 and the chip 110 is controlled to be 100um to 500um, which is conducive to controlling the stress distribution while ensuring that the chip 110 can be smoothly embedded, thereby further protecting the chip 110.

[0061] In a feasible implementation, the first flexible film layer 120 and the second flexible film layer 130 are made of the same material. This arrangement can reduce the impact of CTE mismatch, match the previous and next film processes, and avoid defects caused by different process conditions.

[0062] In a feasible implementation, the thickness of the second flexible film layer 130 is greater than the thickness of the first flexible film layer 120. Such an arrangement facilitates I / O lead-out and the preparation of interconnection components.

[0063] like Figure 3 As shown, according to the second aspect of the embodiment of the present application, a chip flexible packaging method is proposed, which is used to prepare a semiconductor device as any of the above technical solutions. The chip flexible packaging method includes:

[0064] Step 101: providing a carrier board, and disposing a first flexible film layer on the carrier board;

[0065] Step 102: attaching the chip to the first flexible film layer, and embedding at least a portion of the chip into the first flexible film layer;

[0066] Step 103: Connecting the second flexible film layer to the chip and the first flexible film layer;

[0067] Step 104: preparing interconnection components;

[0068] Step 105: remove the carrier to obtain a packaged semiconductor device.

[0069] The semiconductor device prepared by the chip flexible packaging method provided in the embodiment of the present application packages the chip through the first flexible film layer and the second flexible film layer, which can not only wrap the chip well, but also realize the lead-out of the chip I / O, and realize the chip communication by connecting to the chip through the interconnection component, so that the back-end process of the semiconductor device can support the completion of the chip flip-chip welding process, and has the bendability, which can improve the shortcomings of ultra-thin chips such as poor machinability, fragility during the bending process, and high interconnection risk. The semiconductor device finally formed has the advantages of lightness, high reliability, and simple interconnection interface, and the full set of processes does not involve non-standard processes or equipment, and can adopt existing mature systems.

[0070] like Figures 2a to 2j As shown, in a feasible implementation manner, a carrier 160 is provided, and the step of disposing the first flexible film layer 120 on the carrier 160 includes: providing the carrier 160 , disposing a temporary adhesive layer 170 on the carrier 160 ; and disposing the first flexible film layer 120 on the temporary adhesive layer 170 .

[0071] In this technical solution, a temporary adhesive layer 170 can be firstly arranged on the carrier 160, and then the first flexible film layer 120 can be arranged on the temporary adhesive layer 170. The carrier 160 can provide a hard support for the first flexible film layer 120. The arrangement of the temporary adhesive layer 170 facilitates the removal of the packaged semiconductor device.

[0072] It is understandable that the carrier 160 should have good thermal stability and load-bearing capacity, and should match the conditions for subsequent release of the temporary bonding adhesive / tape, such as quartz glass, stainless steel or polytetrafluoroethylene.

[0073] In some examples, the temporary adhesive layer 170 can be a temporary bonding adhesive or a temporary bonding tape. The bonding material can be selected from pyrolytic tape, UV release tape, and laser bonding adhesive, for example: SELFA HW-1 series UV double-sided tape, Brewer Science HT series laser tape or WLP TB4130 series temporary bonding adhesive. It is recommended that the film lamination or spin coating be performed in a vacuum film lamination equipment to reduce the generation of bubbles.

[0074] like Figures 2a to 2j As shown, in a feasible implementation manner, the step of removing the carrier to obtain a completed packaged semiconductor device includes: removing the temporary adhesive layer 170 to separate the completed packaged semiconductor device from the carrier 160 .

[0075] In this technical solution, after the semiconductor device is packaged, the temporary adhesive layer 170 can be removed to separate the semiconductor device from the carrier 160, and then the semiconductor device can be removed through the carrier 160 to obtain a finished semiconductor device.

[0076] like Figures 2a to 2j As shown, in a feasible implementation manner, the step of bonding the chip 110 to the first flexible film layer 120 and embedding at least a portion of the chip 110 into the first flexible film layer 120 includes: bonding the chip 110 to the uncured first flexible film layer 120, applying pressure to the chip 110 so that the chip 110 is embedded in the first flexible film layer 120 and does not touch the bottom of the first flexible film layer 120; and curing the first flexible film layer 120.

[0077] In this technical solution, a step of embedding the chip 110 into the first flexible film layer 120 is further provided. The chip 110 can be firstly pasted onto the uncured first flexible film layer 120 at the center of the first flexible film layer 120. The pressure should be adjusted to be able to be embedded in the middle of the first flexible film layer 120 but not touching the bottom of the first flexible film layer 120. The chip 110 pasting temperature is set to the film pasting temperature required by the first flexible film layer 120 to ensure that the first flexible film layer 120 is softened and the chip 110 is embedded. Finally, high-temperature curing is performed according to the temperature required by the first flexible film layer 120 to complete the embedding of the chip 110, so that the chip 110 can be wrapped in a partial area through the first flexible film layer 120, which is convenient for the subsequent bending of the chip 110.

[0078] In a feasible embodiment, the steps of preparing the interconnection component 140 include: performing photolithography on the second flexible film layer 130 to prepare I / O openings interconnected with the chip 110, and curing the second flexible film layer 130; performing metallization deposition on the second flexible film layer 130 to form a first metal seed layer 180; forming a redistribution layer 141 based on the first metal seed layer 180; and forming solder balls 142 on the redistribution layer 141.

[0079] In this technical solution, specific steps for preparing interconnection components are further provided. The second flexible film layer 130 can be first photolithographically processed, and then the redistribution layer 141 and the solder balls 142 can be prepared by metal deposition. Based on this, the chip flexible packaging method provided in the embodiment of the present application adopts a flexible film process to construct the package structure, completes the package structure on the front / back sides of the chip 110, and then performs the Fan-in pad redistribution and solder ball 142 preparation process on the front side. Finally, it is only necessary to release the wrapped ultra-thin chip 110 through laser bonding and debonding processes to complete the product packaging. The chip flexible packaging method can improve the shortcomings of the ultra-thin chip 110, such as poor machinability, fragility during the bending process, and high interconnection risk. The final package has the advantages of being light and thin, highly reliable, and having a simple interconnection interface.

[0080] like Figures 2a to 2j As shown, in a feasible embodiment, the step of forming solder balls 142 on the redistribution layer 141 includes: coating a passivation dielectric layer 150 on the redistribution layer 141 and performing photolithography to open windows; forming a second metal seed layer 190 on the passivation dielectric layer 150; and forming solder balls 142 based on the second metal seed.

[0081] In this technical solution, a method for preparing the solder ball 142 is further provided. The second metal seed layer 190 can be subjected to photolithography, development, electroplating, film stripping and flash etching processes. This is a standard bumping / pillar process to complete the preparation of the corresponding solder ball 142. Here, according to actual design requirements, structures such as CuSnAg, CuSn, CuSnAu, Cu Pillar or Au Pillar can be prepared.

[0082] In summary, through the chip flexible packaging method provided in the embodiment of the present application, on the one hand, the chip 110 is wrapped with a thin film and has side wall protection, which can greatly improve the bendability and reliability of the chip 110; on the other hand, the chip 110 I / O can be led out, and the RDL, pad redistribution and bumping preparation can be completed on the surface of the chip 110; on the other hand, the prepared semiconductor device can support the completion of the chip 110 flip-chip welding process in the back-end process and has bendability.

[0083] In some examples, the chip flexible packaging method may specifically include the following steps:

[0084] like Figure 2aAs shown, step 1: first, a carrier 160 is used as a hard support in the process flow. Here, the carrier 160 should have good thermal stability and load-bearing capacity, and should match the conditions for the subsequent release of the temporary bonding glue / tape, such as quartz glass, stainless steel or polytetrafluoroethylene, etc.; and a temporary adhesive layer 170 is coated on the carrier 160. The temporary adhesive layer 170 may include a temporary bonding glue or a temporary bonding tape. The bonding material may be a pyrolytic tape, an ultraviolet release tape, and a laser bonding glue, such as SELFA HW-1 series UV double-sided tape, Brewer Science HT series laser tape or WLP TB4130 series temporary bonding glue. It is recommended that the film or spin coating be performed in a vacuum film laminating device to reduce the generation of bubbles.

[0085] like Figure 2b As shown, step 2: applying the first flexible film layer 120 on the surface of the temporary adhesive layer 170, the first flexible film layer 120 can be made of a photosensitive film, the thickness of the first flexible film layer 120 here should be greater than 1 / 2 of the thickness of the chip 110 used later, the film material used here should match the CTE and elastic modulus of the subsequent dry film material, for example: Fuji FCPi 2100 series or Shin-Etsu Semiconductor SINR series products, TOK TMMF series, etc.; performing a photolithography process on the first flexible film layer 120 to complete the preparation of an array-type photosensitive film pattern, the size of the first flexible film layer 120 after photolithography should be selected according to the size of the subsequent chip 110, the first flexible film layer 120 should be more than 100um larger than the size of the chip 110 on one side, and should not be greater than 500um.

[0086] like Figure 2c As shown, step three: the thinned chip 110 is mounted on the uncured first flexible film layer 120 through the mounting equipment, the position is the center of the first flexible film layer 120, the pressure should be adjusted to be able to embed into the middle of the first flexible film layer 120, but not touch the bottom of the first flexible film layer 120, the mounting temperature is set to the required film mounting temperature of the first flexible film layer 120, ensure that the first flexible film layer 120 is softened, and the chip 110 is embedded. High temperature curing is performed according to the required temperature of the first flexible film layer 120;

[0087] like Figure 2d As shown, step 4: applying the second flexible film layer 130, where the second flexible film layer 130 should be of the same type as the first flexible film layer 120, to reduce the impact of CTE mismatch, and to match the two film processes before and after, to avoid defects caused by different process conditions;

[0088] like Figure 2eAs shown, step five: perform a photolithography process on the second flexible film layer 130 to expose the I / O openings required for interconnection of the chip 110, and the process is consistent with step three according to the film selection; complete the curing of the second flexible film layer 130;

[0089] like Figure 2f As shown, step six: metallization deposition is performed on the surface of the second flexible film layer 130 to complete the first metal seed layer 180. Various methods such as magnetron sputtering, electron evaporation or chemical deposition can be used here. The metal layer should be but not limited to Ti / Cu, TiW / Cu, Cr / Cu, etc. If the metal bonding force is to be improved, the surface treatment process of the second flexible film layer 130 can be performed before metallization. The treatment method is selected according to the characteristics of the second flexible film layer 130, including but not limited to Plasma, RIE or ozone ultraviolet treatment, etc.;

[0090] like Figure 2g As shown, step seven: performing conventional photolithography, development, electroplating, film stripping and flash etching processes on the first metal seed layer 180, which is a standard semi-additive process, and completing the preparation of the Fan-in redistribution layer 141 (RDL circuit) according to the circuit design plan;

[0091] like Figure 2h As shown, step eight: coating a passivation dielectric layer 150 on the RDL circuit, the passivation dielectric layer 150 is a photosensitive passivation dielectric layer 150, and completing the RDL pad photolithography window opening process, where the materials include but are not limited to photosensitive polyimide, BCB and SU8, etc.; completing the passivation dielectric layer 150 curing;

[0092] like Figure 2i As shown, step nine: metallization deposition is performed on the surface of the passivation dielectric layer 150 to complete the second metal seed layer 190. Various methods such as magnetron sputtering, electron evaporation or chemical deposition can be used here. The metal layer should be but not limited to Ti / Cu, TiW / Cu, Cr / Cu, etc. If the metal bonding force is to be improved, the surface treatment process of the passivation dielectric layer 150 can be performed before metallization. The treatment method is selected according to the characteristics of the passivation dielectric layer 150, including but not limited to Plasma, RIE or ozone ultraviolet treatment, etc.;

[0093] like Figure 2j As shown, step ten: performing conventional photolithography, development, electroplating, film stripping and flash etching processes on the second metal seed layer 190, which is a standard Bumping / Pillar process, to complete the preparation of the corresponding solder ball 142, where CuSnAg, CuSn, CuSnAu, Cu Pillar or Au Pillar structures can be prepared according to actual design requirements;

[0094] like Figure 1As shown, step eleven: debonding the entire structure, removing the packaged chip 110 according to the release condition of the selected temporary adhesive layer 170, and completing all the processes of chip 110 packaging.

[0095] In some examples, the chip flexible packaging method may specifically include the following steps:

[0096] Step 1: Use high-transmittance glass with a thickness of 2mm and a size of 100mm*100mm as the carrier, model is Schott BF33;

[0097] Step 2: Use a temporary bonding film to attach it to the glass. The bonding film here is Sekisui Semiconductor's SELFA HW-1 series UV double-sided tape, and EVG 5 series bonding equipment is used to complete the temporary bonding film attachment on the glass surface.

[0098] Step 3: Use a photosensitive film to attach to the temporary bonding film as the first flexible film layer. Here, TAIYO's FINEFLEX_30SA is used, with a film thickness of 30um. Guangdong Siwo Precision's V-ONE vacuum laminating equipment is used, and the laminating temperature is 80 degrees Celsius to complete the laminating process;

[0099] Step 4: The first flexible film layer is subjected to photolithography. The photolithography pattern is 3.3 mm*4.5 mm square. The photolithography equipment used is SUSS MA6 and the developing system is 1% sodium carbonate.

[0100] Step 5: Place the chip in the center of the first flexible film layer after photolithography. The chip here is a power control chip of a certain company, with a thickness of 30um and a chip size of 3.1mm*4.3mm. The chip is placed using Datacon 2200, the placement temperature is 80 degrees Celsius, and the placement pressure is 10gf. The embedded film depth after chip placement is 20um;

[0101] Step 6: Curing, temperature set to 150 degrees Celsius, 60 minutes, nitrogen atmosphere;

[0102] Step 7: Repeat Step 3 to form a second flexible film layer;

[0103] Step 8: The second flexible film layer is subjected to photolithography. The photolithography pattern is a circular via of the I / O port of the control chip. The photolithography equipment used is SUSS MA6 and the developing system is 1% sodium carbonate.

[0104] Step 9: Repeat Step 6;

[0105] Step 10: The surface of the second flexible film layer is treated with argon plasma, with an argon flow rate of 90 sccm, a power of 1.0 kW, a vacuum degree of 100 mTor, and the equipment used is March ap1000;

[0106] Step 11: Deposit a seed layer metal on the second flexible film layer to form a first metal seed layer. A magnetron sputtering Ti / Cu structure is used here, where Ti is 100nm and Cu is 300nm. The equipment used is Beijing Weikai M600.

[0107] Step 12: Coat photoresist on the surface of the first metal seed layer. AZ4620 is used here. The speed is set to 500rpm for 15s and 2000rpm for 30s. The coating thickness is 10um. The equipment used is KW-4. Soft bake is performed at a temperature of 120 degrees Celsius for 180s.

[0108] Step 13: Perform photolithography on the photoresist. The photolithography pattern is Fan-in RDL pattern. The photolithography equipment used is SUSS MA6 and the development system is MicoChem 400K solution.

[0109] Step 14: Perform a pattern electroplating process on the photolithography pattern. Here, a copper sulfate plating solution system is used to complete the 8um thickness pattern electroplating process;

[0110] Step 15: Use acetone solution to remove the photoresist, and then use 20% ferric chloride solution and 3% hydrofluoric acid solution to flash-etch the seed layer Cu and Ti to complete the RDL layer preparation;

[0111] Step 16: Coat a photosensitive dielectric layer on the RDL layer to form a passivation dielectric layer. HD 4100 is used here, the speed is set to 500rpm for 15s, 2500rpm for 30s, the coating thickness is 7um, the equipment used is KW-4, and soft baking is performed at a temperature of 120 degrees Celsius for 180s;

[0112] Step 13: Perform photolithography on the photoresist, the photolithography pattern is a Bumpinp via pattern, the photolithography equipment used is SUSS MA6, and the developing system is 2.38% TMAH solution;

[0113] Step 14: Curing, temperature set to 220 degrees Celsius, temperature gradient 5 degrees Celsius / min, maximum temperature 120 minutes, natural cooling, nitrogen atmosphere;

[0114] Step 15: The surface of the photofilm is treated with oxygen plasma, with an argon flow rate of 80 sccm, a power of 1.0 kW, a vacuum degree of 100 mTor, and the equipment used is March ap1000;

[0115] Step 16: Repeat Step 11 to form a second metal seed layer;

[0116] Step 17: Coat photoresist on the surface of the second metal seed layer. Futurrex NR5-8000 is used here. The speed is set to 500rpm for 15s and 1000rpm for 30s. The coating thickness is 35um. The equipment used is KW-4. Soft bake is performed at a temperature of 150 degrees Celsius for 180s.

[0117] Step 18: Perform photolithography on the photoresist. The photolithography pattern is a bumping window pattern. The photolithography equipment used is SUSS MA6, and the developing system is PGMEA solution.

[0118] Step 19: Performing electroplating process on the photolithography pattern, copper sulfate, phenol sulfonate electroplating tin and DMH cyanide-free electroplating silver plating solution system are used here to complete the preparation of Cu / Sn / Ag solder balls;

[0119] Step 20: Use acetone solution to remove the photoresist, then use 20% ferric chloride solution and 3% hydrofluoric acid solution to flash-etch the seed layer Cu and Ti to remove the seed layer, and then complete the reflow according to the solder ball metal ratio;

[0120] Step 21: Remove the carrier glass by UV irradiation. Nitto UM810 equipment can be used here to release the packaged semiconductor device.

[0121] In the present invention, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance; the term "plurality" refers to two or more, unless otherwise clearly defined. The terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; "connected" can be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0122] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by terms such as “upper”, “lower”, “left”, “right”, “front” and “back” are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or unit referred to must have a specific direction, be constructed and operated in a specific orientation, and therefore, cannot be understood as a limitation on the present invention.

[0123] In the description of this specification, the description of the terms "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0124] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: chip; a first flexible film layer and a second flexible film layer, wherein the chip is arranged between the first flexible film layer and the second flexible film layer; An interconnection component, at least a portion of which is connected to the chip through the second flexible film layer.

2. The semiconductor device according to claim 1, wherein: The chip is embedded in the first flexible film layer so that the first flexible film layer wraps at least a portion of the peripheral side of the chip.

3. The semiconductor device according to claim 1, wherein: A ratio of a thickness of the first flexible film layer to a thickness of the chip is greater than or equal to 0.

5.

4. The semiconductor device according to claim 1, wherein: The interconnect assembly comprises: a redistribution layer, a portion of which passes through the second flexible film layer and is connected to the chip; A solder ball is connected to the redistribution layer.

5. The semiconductor device according to claim 4, characterized in that Also includes: A passivation dielectric layer is disposed on the redistribution layer and / or between adjacent redistribution layers.

6. The semiconductor device according to claim 1, wherein: The thickness of the chip is less than or equal to 50 um.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that The first flexible film layer is made of a photosensitive film; and / or The second flexible film layer is made of a photosensitive film.

8. The semiconductor device according to any one of claims 1 to 6, characterized in that: The distance between the outer edge contour of the first flexible film layer and the chip is 100um to 500um.

9. The semiconductor device according to any one of claims 1 to 6, characterized in that: The first flexible film layer and the second flexible film layer are made of the same material.

10. The semiconductor device according to any one of claims 1 to 6, characterized in that The thickness of the second flexible film layer is greater than that of the first flexible film layer.

11. A chip flexible packaging method, characterized in that: Applied to the semiconductor device according to any one of claims 1 to 10, the chip flexible packaging method comprises: providing a carrier board on which a first flexible film layer is disposed; Pasting a chip onto the first flexible film layer, and embedding at least a portion of the chip into the first flexible film layer; connecting a second flexible film layer to the chip and the first flexible film layer; preparing interconnect components; The carrier is removed to obtain a packaged semiconductor device.

12. The chip flexible packaging method according to claim 11, characterized in that: The step of preparing the interconnection assembly comprises: Performing photolithography on the second flexible film layer to prepare I / O openings interconnected with the chip, and curing the second flexible film layer; Performing metallization deposition on the second flexible film layer to form a first metal seed layer; Based on the first metal seed layer, forming a redistribution layer; Solder balls are formed on the redistribution layer.

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