Semiconductor package

Abstract

A semiconductor package includes a first semiconductor chip, a dummy die on the first semiconductor chip, a second semiconductor chip stacked on the dummy die, and a dummy plate on the second semiconductor chip. Each of the first semiconductor chip, the dummy die, and the second semiconductor chip includes a through electrode. The dummy die and the second semiconductor chip closest to the dummy die are connected to each other by direct contact of the bond pads. Adjacent second semiconductor chips are connected to each other by direct contact of the bond pads. The first semiconductor chip, the dummy die, the second semiconductor chip, and the dummy plate have a first width, a second width, a third width, and a fourth width, respectively, in a horizontal direction. The fourth width is greater than the second and third widths.

Description

[0001] This patent application claims the priority of Korean Patent Application No. 10-2023-0120612 filed in the Korean Intellectual Property Office on September 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present disclosure relate to a semiconductor package, and more particularly, to a semiconductor package including a plurality of stacked semiconductor chips. Background Art

[0003] With the development of the electronics industry, the demand for high-performance electronic devices is increasing. Therefore, a method for arranging multiple semiconductor chips is needed to achieve high performance of electronic devices. Therefore, a semiconductor package including multiple semiconductor chips having through electrodes and stacked in a vertical direction has been proposed. Summary of the invention

[0004] According to an embodiment of the present disclosure, a semiconductor package is provided, comprising: a core die and a dummy board, wherein the dummy board is adhered to the topmost core die among the core die by a hybrid bonding method, which can increase the bonding strength between the dummy board and the topmost core die while increasing the thickness of the dummy board to improve the reliability of the semiconductor package.

[0005] According to an embodiment of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a first semiconductor chip; a dummy die on the first semiconductor chip; a second semiconductor chip stacked on the dummy die; and a dummy board on the second semiconductor chip, wherein each of the first semiconductor chip, the dummy die, and the second semiconductor chip includes a through electrode, wherein the lowermost second semiconductor chip of the dummy die and the second semiconductor chip closest to the dummy die is connected to each other through direct contact of a first bonding pad, wherein adjacent second semiconductor chips of the second semiconductor chips are connected to each other through direct contact of a second bonding pad, wherein the first semiconductor chip, the dummy die, the second semiconductor chip, and the dummy board have a first width, a second width, a third width, and a fourth width in a horizontal direction, respectively, and wherein the fourth width is greater than the second width and the third width.

[0006] According to an embodiment of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a first semiconductor chip; a dummy die on the first semiconductor chip; a second semiconductor chip stacked on the dummy die; a dummy board on the second semiconductor chip; and a molding structure located between the first semiconductor chip and the dummy board, wherein each of the first semiconductor chip, the dummy die, and the second semiconductor chip includes a through electrode, wherein the dummy die and the first semiconductor chip are connected to each other through direct contact of a first bonding pad, wherein the dummy die and the second semiconductor chip are connected to each other through direct contact of a second bonding pad, wherein the adjacent second semiconductor chips in the second semiconductor chips are connected to each other through direct contact of a third bonding pad, wherein the dummy board and the uppermost second semiconductor chip in the second semiconductor chips are connected to each other through direct contact of an insulating material, and wherein the molding structure is on a top surface of the first semiconductor chip, a side surface of the dummy die, a side surface of the second semiconductor chip, and a bottom surface of the dummy board.

[0007] According to an embodiment of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a package substrate; an interposer on the package substrate; a logic chip on the interposer; and chip stacking structures spaced apart from each other, wherein the logic chip is between the chip stacking structures, each of the chip stacking structures includes: a buffer die; a dummy die on the buffer die; a core die stacked on the dummy die; a dummy board on the core die; and a molding structure located between the buffer die and the dummy board, wherein each of the buffer die, the dummy die, and the core die includes a through electrode, wherein the dummy die and the buffer die are connected to each other by direct contact with a first bonding pad, wherein the dummy die is connected to the bottommost core die of the core die. The cores are connected to each other through direct contact of the second bonding pad, wherein adjacent core dies in the core tube core are connected to each other through direct contact of the third bonding pad, wherein the dummy board and the uppermost core tube core in the core tube core are connected to each other through direct contact of the insulating material, wherein the molding structure is on the top surface of the buffer tube core, the side surface of the dummy tube core, the side surface of the core tube core and the bottom surface of the dummy board, wherein the buffer tube core, the dummy tube core, the core tube core and the dummy board have a first width, a second width, a third width and a fourth width in the horizontal direction respectively, wherein the first width is substantially equal to the fourth width, and wherein the second width is substantially equal to the third width. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure.

[0009] Figure 1B It is conceptually shown Figure 1AA cross-sectional view of the top and bottom surfaces of a die of a semiconductor package.

[0010] Figure 2 yes Figure 1A An enlarged view of area CU1.

[0011] Figure 3 yes Figure 1A An enlarged view of area CU2.

[0012] Figure 4 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure.

[0013] Figure 5A is corresponding to Figure 4 An enlarged view of area CU3.

[0014] Figure 5B is corresponding to Figure 4 An enlarged view of area CU3.

[0015] Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0016] Figure 6B , Figure 7B , Figure 8B and Fig. 9B It is conceptually shown Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A A cross-sectional view of the top and bottom surfaces of a die.

[0017] Figure 6C and Figure 7C They are Fig. 6A Area CU4 and Fig. 7A A magnified view of area CU5.

[0018] Fig.10 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0019] Fig.11 is corresponding to Fig.10 A magnified view of area CU6.

[0020] Fig.12 is corresponding to Fig.10 A magnified view of area CU6.

[0021] Fig.13A is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0022] Fig. 13B It is conceptually shown Fig.13A A cross-sectional view of the top and bottom surfaces of a die.

[0023] Fig.14 is a plan view showing a semiconductor package according to some embodiments of the present disclosure.

[0024] Fig.15 is along Fig.14 A cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0025] Example embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings.

[0026] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or coupled to the other element or layer, or intervening elements or layers may be present. Conversely, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0027] Figure 1A is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure. Figure 1B It is conceptually shown Figure 1A A cross-sectional view of the top and bottom surfaces of a die of a semiconductor package. Figure 2 yes Figure 1A An enlarged view of area CU1. Figure 3 yes Figure 1A An enlarged view of area CU2.

[0028] Reference Figure 1A and Figure 1B For example, the semiconductor package 10 according to the embodiment of the present disclosure may be a high bandwidth memory (HBM). In this specification, the semiconductor package 10 may also be referred to as a chip stack structure. The semiconductor package 10 may include a first semiconductor chip 100, a dummy die 200, second semiconductor chips 300B, 300 and 300U, a dummy board 400 and a molding structure 500.

[0029] In this manual, if Figure 1BAs shown, a direction parallel to the bottom surface 400a of the dummy board 400 may be defined as a first direction D1. The bottom surface 400a of the dummy board 400 may correspond to a surface of a second dummy substrate 410 to be described below. A direction parallel to the bottom surface 400a of the dummy board 400 and intersecting the first direction D1 may be defined as a second direction D2. A direction perpendicular to the bottom surface 400a of the dummy board 400 may be defined as a third direction D3.

[0030] Reference Figure 1A and Figure 2 , the first semiconductor chip 100 may correspond to the lower part of the semiconductor package 10. In this specification, the first semiconductor chip 100 may also be referred to as a logic die, a logic chip, a base die, a buffer chip, a buffer die or a memory controller. The first semiconductor chip 100 may perform the function of a logic chip, which improves the efficiency of data transmission and reduces power consumption. The first semiconductor chip 100 may include a first semiconductor substrate 110, a first upper insulating layer 131, a first upper bonding pad 132, a first through electrode 150, a first integrated circuit 140, a first interconnect layer 120 and a connection terminal 180.

[0031] The first semiconductor substrate 110 may include a semiconductor material such as silicon and / or germanium. The first semiconductor substrate 110 may include a first bottom surface 110a and a first top surface 110b opposite to each other.

[0032] The first interconnection layer 120 may be disposed on the first bottom surface 110a of the first semiconductor substrate 110. The first interconnection layer 120 may include a first lower insulating layer 121, a first lower interconnection pattern 123, and a lower bump pattern 122. For example, the first lower insulating layer 121 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (SiO x N y ) at least one of the following. The first lower insulating layer 121 may include a plurality of insulating layers. The first lower interconnection pattern 123 may include a plurality of interconnection lines and through holes connected thereto. The lower bump pattern 122 may be located at a lower portion of the first interconnection layer 120. One surface of the lower bump pattern 122 may be connected to the first lower interconnection pattern 123, and the other surface of the lower bump pattern 122 may be exposed from the first lower insulating layer 121. The connection terminal 180 may be disposed on the exposed surface of the lower bump pattern 122. For example, the connection terminal 180 may be a solder ball, a bump, or a column.

[0033] The first upper insulating layer 131 and the first upper bonding pad 132 may be disposed on the first top surface 110b. For example, the first upper insulating layer 131 may include silicon oxide (SiO 2), silicon nitride (Si 3 N 4 ) and silicon oxynitride (SiO x N y The first upper bonding pad 132 may be disposed in the first upper insulating layer 131. In some embodiments, the first upper insulating layer 131 may extend between the first upper bonding pad 132 and the first top surface 110b of the first semiconductor substrate 110.

[0034] The first through electrode 150 may penetrate the first semiconductor substrate 110. For example, the first through electrode 150 may include a conductive material such as copper. A diffusion barrier pattern (e.g., tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), and / or tungsten (W)) may be disposed between the first through electrode 150 and the first semiconductor substrate 110. One end of the first through electrode 150 may be connected to the first upper bonding pad 132, and the other end of the first through electrode 150 may be connected to the first lower interconnection pattern 123.

[0035] The dummy die 200 may be disposed on the first semiconductor chip 100. Unlike the first semiconductor chip 100, the dummy die 200 may not include an integrated circuit and an interconnection pattern. The dummy die 200 may include a first dummy substrate 210, a lower connection insulating layer 221, an upper connection insulating layer 231, an upper dummy bonding pad 232, and a dummy through electrode 250.

[0036] The first dummy substrate 210 may have a first surface 210a and a second surface 210b opposite to each other. The second surface 210b may be more curved than the first surface 210a. In other words, the first surface 210a may be flatter than the second surface 210b. The thickness 210H of the first dummy substrate 210 may change toward the first direction D1 and / or the second direction D2. In other words, the first dummy substrate 210 may include a first region and a second region having different thicknesses, and the thickness of the first region may be greater than the thickness of the second region. The thickness difference between the first region and the second region may be 0.3 μm or greater. The amplitude of the height variation of the second surface 210b of the first dummy substrate 210 in the first direction D1 may be greater than the amplitude of the height variation of the first surface 210a in the first direction D1.

[0037] The lower connection insulating layer 221 may be disposed on the first surface 210a, and the upper connection insulating layer 231 may be disposed on the second surface 210b. For example, each of the upper connection insulating layer 231 and the lower connection insulating layer 221 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (SiO x Ny The lower connection insulating layer 221 of the dummy die 200 may be in contact with the first upper insulating layer 131 of the first semiconductor chip 100. In some embodiments, the lower connection insulating layer 221 and the first upper insulating layer 131 may be regarded as a single insulating layer without an interface therebetween.

[0038] The dummy through-electrode 250 may include a first dummy through-electrode 251 and a second dummy through-electrode 252. The first dummy through-electrode 251 and the second dummy through-electrode 252 may penetrate the first dummy substrate 210. The first dummy through-electrode 251 and the second dummy through-electrode 252 may electrically connect the first semiconductor chip 100 to the second semiconductor chip 300. One end of the first dummy through-electrode 251 and one end of the second dummy through-electrode 252 may contact the corresponding upper dummy bonding pad 232. The other end of the first dummy through-electrode 251 and the other end of the second dummy through-electrode 252 may contact the corresponding first upper bonding pad 132 of the first semiconductor chip 100. The first dummy through-electrode 251 may have a first height 251H in the third direction D3, and the second dummy through-electrode 252 may have a second height 252H in the third direction D3. The first height 251H may be greater than the second height 252H. For example, the difference between the first height 251H and the second height 252H may be in the range of 0.3 μm to 5 μm. For example, the difference between the first height 251H and the second height 252H may be 2 μm.

[0039] A top surface of the first dummy through electrode 251 may have a level higher than that of a top surface of the second dummy through electrode 252. A bottom surface of the first dummy through electrode 251 may have a level substantially the same as that of a bottom surface of the second dummy through electrode 252.

[0040] For example, the dummy through electrode 250 may include a conductive material such as copper. A diffusion barrier pattern (e.g., tantalum nitride (TaN), etc.) may be provided between each dummy through electrode 250 and the first dummy substrate 210. A plurality of upper dummy bonding pads 232 may be provided on the second surface 210b of the first dummy substrate 210. A plurality of upper dummy bonding pads 232 may be provided at different levels with a level difference due to the curved shape of the second surface 210b. In some embodiments, the upper connection insulating layer 231 may extend between the upper dummy bonding pad 232 and the second surface 210b of the first dummy substrate 210.

[0041] The bottom second semiconductor chip 300B among the second semiconductor chips 300B, 300 and 300U can be connected to the dummy die 200 by direct contact of the bonding pad. Each of the second semiconductor chips 300B, 300 and 300U can be a memory chip. For example, each of the second semiconductor chips 300B, 300 and 300U can be a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip or a NAND-FLASH chip. The second semiconductor chips 300B, 300 and 300U can be semiconductor chips of the same kind with the same second integrated circuit 340. In this specification, each of the second semiconductor chips 300B, 300 and 300U can be referred to as a core die or a core chip.

[0042] Each of the second semiconductor chips 300B, 300A and 300U may include a second semiconductor substrate 310 , a second upper insulating layer 331 , a second upper bonding pad 332 , a second through electrode 350 , a second integrated circuit 340 , and a second interconnection layer 320 .

[0043] The second semiconductor substrate 310 may include a semiconductor material such as silicon (Si). The second semiconductor substrate 310 may include a second bottom surface 310a and a second top surface 310b opposite to each other. The thickness of the second semiconductor substrate 310 in the third direction D3 may be substantially uniform along the first direction D1 and / or the second direction D2.

[0044] The second bottom surface 310a and the second top surface 310b of the second semiconductor substrate 310 may be curved. The topology of each of the second bottom surface 310a and the second top surface 310b may have a shape that is curved up and down. The topology may represent a connection relationship (e.g., shape, structure, etc.) of a surface, and the height of the surface may be checked through the topology.

[0045] The second interconnection layer 320 may be disposed on the second bottom surface 310a of the second semiconductor substrate 310. The second interconnection layer 320 may include a second lower insulating layer 321, a second lower interconnection pattern 323, and a lower bonding pad 322. For example, the second lower insulating layer 321 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (SiO x N y) at least one of the following. The second lower insulating layer 321 may include a plurality of insulating layers. The second lower interconnect pattern 323 may include a plurality of interconnect lines and through holes connected thereto. The lower bonding pad 322 may be located at the lower portion of the second interconnect layer 320. One surface of the lower bonding pad 322 may be connected to the second lower interconnect pattern 323, and the other surface of the lower bonding pad 322 may be in contact with the upper dummy bonding pad 232 of the dummy die 200.

[0046] The second semiconductor chips 300B, 300A and 300U may be connected to each other through direct contact of bonding pads, similar to the connection through direct contact of bonding pads of the lowermost second semiconductor chip 300B and the dummy die 200 .

[0047] The second upper insulating layer 331 and the second upper bonding pad 332 may be disposed on the second top surface 310b. For example, the second upper insulating layer 331 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (SiO x N y The second upper bonding pad 332 may be disposed in the second upper insulating layer 331. In some embodiments, the second upper insulating layer 331 may extend between the second upper bonding pad 332 and the second top surface 310b of the second semiconductor substrate 310.

[0048] The second through electrode 350 may penetrate the second semiconductor substrate 310. For example, the second through electrode 350 may include a conductive material such as copper. A diffusion barrier pattern (e.g., tantalum nitride (TaN), etc.) may be disposed between the second through electrode 350 and the second semiconductor substrate 310. One end of the second through electrode 350 may be connected to the second upper bonding pad 332, and the other end of the second through electrode 350 may be connected to the second lower interconnection pattern 323. The second through electrode 350 may have a third height 350H. In some embodiments, the third height 350H of the second through electrode 350 may be greater than the first height 251H and the second height 252H of the dummy through electrode 250 of the dummy die 200.

[0049] The molding structure 500 may cover the top surface of the first semiconductor chip 100, and may cover the side surfaces of the dummy die 200 and the side surfaces of the second semiconductor chips 300B, 300 and 300U. The molding structure 500 may include an insulating material such as epoxy molding compound (EMC). The molding structure 500 may be disposed between the top surface of the first semiconductor chip 100 and the bottom surface of the dummy board 400.

[0050] The dummy board 400 may be disposed on the uppermost second semiconductor chip 300U among the second semiconductor chips 300B, 300 and 300U. Figure 1A and Figure 3 , the dummy board 400 may include a second dummy substrate 410 and an adhesive insulating layer 420. The second dummy substrate 410 may include a semiconductor material such as silicon and / or germanium. For example, the second dummy substrate 410 may be a silicon substrate. The second dummy substrate 410 may not include a device (e.g., an integrated circuit), an interconnect pattern, and a through electrode. The adhesive insulating layer 420 may contact the second upper insulating layer 331 and the second upper bonding pad 332 of the uppermost second semiconductor chip 300U. For example, the adhesive insulating layer 420 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (SiO x N y A gap of several micrometers or more may be observed between the adhesive insulating layer 420 and the second upper insulating layer 331 and / or between the adhesive insulating layer 420 and the second upper bonding pad 332, or there may be no such gap of several micrometers or more.

[0051] Refer again Figure 1A , the first semiconductor chip 100 may have a first width 100W in the first direction D1. The first width 100W may refer to the width of the first semiconductor substrate 110 in the first direction D1. The dummy die 200 may have a second width 200W in the first direction D1. The second width 200W may refer to the width of the first dummy substrate 210 in the first direction D1. Each of the second semiconductor chips 300B, 300 and 300U may have a third width 300W in the first direction D1. The third width 300W may refer to the width of the second semiconductor substrate 310 in the first direction D1. The dummy board 400 may have a fourth width 400W in the first direction D1. The fourth width 400W may refer to the width of the second dummy substrate 410 in the first direction D1.

[0052] The first width 100W and the fourth width 400W may be substantially equal to each other. In the present specification, it is understood that when the widths of the components are substantially equal to each other, they may be numerically equal to each other, or the components may be designed to have the same width and may be manufactured by the same cutting process under the same conditions, although the widths of the components are slightly different from each other. For example, when the width difference between components (e.g., die and / or dummy boards) is 10 μm or less, the widths of the components may be substantially equal to each other. The second width 200W and the third width 300W may be substantially equal to each other. The first width 100W and the fourth width 400W may be greater than the second width 200W and the third width 300W.

[0053] The first semiconductor chip 100, the dummy die 200, the second semiconductor chip 300B, 300 or 300U and the dummy board 400 may have a first thickness 100T, a second thickness 200T, a third thickness 300T and a fourth thickness 400T in the third direction D3, respectively. The fourth thickness 400T may be three times or more of each of the first thickness 100T, the second thickness 200T and the third thickness 300T. For example, the fourth thickness 400T may be 250 μm or more. The first thickness 100T may be equal to or greater than the third thickness 300T. The second thickness 200T may be equal to or less than the third thickness 300T. For example, the third thickness 300T may be 38 μm.

[0054] The first thickness 100T may be a distance from the top surface of the first upper insulating layer 131 of the first semiconductor chip 100 to the bottom surface of the first lower insulating layer 121. In addition, the first thickness 100T may be a difference between the level of the top surface of the first upper bonding pad 132 and the level of the bottom surface of the lower bump pattern 122. The second thickness 200T may be the sum of the thickness of the upper dummy bonding pad 232 and the first height 251H of the first dummy through electrode 251, or the sum of the thickness of the upper dummy bonding pad 232 and the second height 252H of the second dummy through electrode 252. The third thickness 300T may represent the difference between the level of the bottom surface of the lower bonding pad 322 and the level of the top surface of the second upper bonding pad 332. The fourth thickness 400T may refer to the sum of the thickness of the second dummy substrate 410 and the thickness of the adhesive insulating layer 420. Alternatively, the fourth thickness 400T may refer to the thickness of the second dummy substrate 410.

[0055] The upper dummy bonding pad 232 of the dummy die 200 and the lower bonding pad 322 of the second semiconductor chip 300B can be bonded to each other without an interface therebetween, thereby being regarded as a single structure. However, the side surfaces of the upper dummy bonding pad 232 and the lower bonding pad 322 can have different tapered shapes, so the levels and thicknesses of the top and bottom surfaces of the upper dummy bonding pad 232 and the lower bonding pad 322 can be inspected using different tapered shapes to determine the second thickness 200T. The first thickness 100T, the second thickness 200T, the third thickness 300T, and the fourth thickness 400T can be measured using non-destructive methods and / or destructive methods used in the art.

[0056] Refer again Figure 1A and Figure 1B , the second semiconductor chips 300U, 300, and 300B may be stacked on the bottom surface 400a of the dummy board 400 by direct contact of the bonding pads, and the height difference of the contact surface may increase sequentially as the distance from the dummy board 400 increases. In other words, the bottom surface 300a8 of the second semiconductor chip 300B closest to the first semiconductor chip 100 may be more curved than the bottom surface 300a1 of the second semiconductor chip 300U closest to the dummy board 400. This may be because in the process of bonding the second semiconductor chips 300U, 300, and 300B having a thin thickness to each other by the hybrid bonding method, the topology of the contact surface may be sequentially transferred and enlarged, and the curvature of the bottom surfaces 300a1 to 300a8 (e.g., the contact surface) may sequentially increase as the number of stacking of the second semiconductor chips 300 increases. According to an embodiment of the present disclosure, the top surface 300b1 of the uppermost second semiconductor chip 300U can be flat, so even if a dummy board 400 with a thicker thickness is used, no gap will be generated. In other words, the gap between the dummy board 400 and the second semiconductor chip 300U can be reduced or no gap occurs. In addition, the dummy die 200 can be arranged between the lowermost second semiconductor chip 300B and the first semiconductor chip 100, and the bottom surface 200a of the dummy die 200 can be flat. The flat bottom surface 200a of the dummy die 200 can be formed by a grinding process as described below, and the curved shape of the surface formed by the accumulation of topology can be removed. As a result, when the first semiconductor chip 100 is in direct contact with the bottom surface 200a of the dummy die 200 through the bonding pad, the misalignment between the dummy die 200 and the first semiconductor chip 100 can be reduced or will not occur.

[0057] Figure 4 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure. Figure 5A is corresponding to Figure 4 An enlarged view of area CU3. Figure 5Bis corresponding to Figure 4 Hereinafter, for the purpose of simplicity and convenience of explanation, the description of the same features as those described above will not be repeated.

[0058] Reference Figure 4 and Figure 5A , the first height 251H of the first dummy through electrode 251 and the second height 252H of the second dummy through electrode 252 may be substantially equal to each other. The first lower dummy bonding pad 2221 opposite to the upper dummy bonding pad 232 may be disposed on the bottom surface of the first dummy through electrode 251. The second lower dummy bonding pad 2222 opposite to the upper dummy bonding pad 232 may be disposed on the bottom surface of the second dummy through electrode 252. The thickness T2 of the second lower dummy bonding pad 2222 may be less than the thickness T1 of the first lower dummy bonding pad 2221. The level of the bottom surface of the second lower dummy bonding pad 2222 may be substantially the same as the level of the bottom surface of the first lower dummy bonding pad 2221. The second lower dummy bonding pad 2222 and the first lower dummy bonding pad 2221 may contact a corresponding one of the first upper bonding pads 132.

[0059] Reference Figure 4 and Figure 5B , the second height 252H of the second dummy through electrode 252 may be equal to or less than the first height 251H of the first dummy through electrode 251. The first lower dummy bonding pad 2221 opposite to the upper dummy bonding pad 232 may be disposed on the bottom surface of the first dummy through electrode 251. The first lower dummy bonding pad 2221 may be in contact with the first upper bonding pad 132. The second lower dummy bonding pad 2222 opposite to the upper dummy bonding pad 232 may not be disposed on the bottom surface of the second dummy through electrode 252. In other words, the second dummy through electrode 252 may be in direct contact with the first upper bonding pad 132 of the first semiconductor chip 100. The horizontal plane of the bottom surface of the first lower dummy bonding pad 2221 may be substantially the same as the level of the bottom surface of the second dummy through electrode 252.

[0060] Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. Figure 6B , Figure 7B , Figure 8B and Fig. 9B It is conceptually shown Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A A cross-sectional view of the top and bottom surfaces of a die. Figure 6C and Figure 7C They are Fig. 6A Area CU4 and Fig. 7A A magnified view of area CU5.

[0061] Reference Fig. 6A , Figure 6B and Figure 6C , a carrier substrate CR1 may be provided. A preliminary dummy board 400P may be disposed on the carrier substrate CR1. The preliminary dummy board 400P may include a second dummy substrate 410 and an adhesive insulating layer 420.

[0062] A plurality of second semiconductor chips 300U, 300 and 300B may be sequentially stacked on the initial dummy board 400P. The second semiconductor chip 300U in contact with the initial dummy board 400P may be bonded to the initial dummy board 400P by a hybrid bonding process. The second semiconductor chips 300 adjacent to each other in the third direction D3 may be bonded to each other by a hybrid bonding process. The hybrid bonding process may mean that the copper pad and the copper pad (or silicon oxide and silicon oxide) are in direct contact with each other at room temperature without connecting terminals (e.g., bumps), and then bonded to each other at high temperatures by an annealing process when the semiconductor chips are bonded to each other. For example, when the second semiconductor chips 300 are bonded to each other, the hybrid bonding process may include: a pretreatment process performed on the top surface of the lower second semiconductor chip among the second semiconductor chips 300; a pretreatment process performed on the lower surface of the upper second semiconductor chip among the second semiconductor chips 300; a process of aligning and compressing the lower second semiconductor chip 300 and the upper second semiconductor chip 300; and a process of bonding the lower second semiconductor chip 300 and the upper second semiconductor chip 300 by using high temperature and high pressure.

[0063] Reference Figure 6B Due to structural features (e.g., metal portions of the second interconnect layer 320, scribe lines, etc.), the top surface (e.g., bottom surface 300a1) of the second semiconductor chip 300U may not be completely flat, and height variations (or height differences) may exist at the top surface (e.g., bottom surface 300a1). The bottom surface (e.g., top surface 300b1) of the second semiconductor chip 300U may be flatter than the top surface (e.g., bottom surface 300a1).

[0064] In the hybrid bonding process, the bottom surface of the second semiconductor chip 300 in contact with the second semiconductor chip 300U may be deformed to contact the top surface (e.g., bottom surface 300a1) of the second semiconductor chip 300U. The top surface (e.g., bottom surface 300a2) of the second semiconductor chip 300 in contact with the second semiconductor chip 300U may be deformed to have a greater height variation than the height variation of the top surface (e.g., bottom surface 300a1) of the second semiconductor chip 300U. The degree of deformation may increase as the number of stacked second semiconductor chips 300 increases.

[0065] The dummy die 200 may be disposed on the second semiconductor chip 300B. The dummy die 200 may be bonded to the second semiconductor chip 300B by a hybrid bonding process. The top surface (or exposed surface) (e.g., bottom surface 200a) of the dummy die 200 may be curved. For example, when the number of the second semiconductor chips 300U, 300, and 300B is 12, the level difference between the highest position and the lowest position of the exposed surface (e.g., bottom surface 200a) may be 0.3 μm or more. For example, the level difference between the highest position and the lowest position may be 2 μm. The level difference may decrease as the number of the second semiconductor chips 300U, 300, and 300B decreases, and the level difference may increase as the number of the second semiconductor chips 300U, 300, and 300B increases.

[0066] Reference Fig. 7A , Figure 7B and Figure 7C , a grinding process may be performed on the exposed surface (e.g., bottom surface 200a) of the dummy die 200. As a result of the grinding process, the pad of the dummy die 200 may be removed, and the dummy through-electrode 250 may be exposed. In this process, the thickness 210H of the first dummy substrate 210 of the dummy die 200 may be reduced. The amount of reduction in the thickness 210H may vary depending on the region. As a result, as Figure 7B As shown, the exposed surface (e.g., bottom surface 200a) of the dummy die 200 may be flatter than the surface 200b opposite thereto. The lower connection insulating layer 221 on the top surface (e.g., first surface 210a) of the first dummy substrate 210 may be removed during the grinding process of the dummy die 200, but the lower connection insulating layer 221 may be generated again by natural oxidation, thereby being formed on the top surface (e.g., first surface 210a) of the flat first dummy substrate 210.

[0067] Reference Fig. 8A and Figure 8B, a release film RF may be provided on the exposed surface (e.g., bottom surface 200a) of the dummy die 200. Thereafter, a molding layer 500P may be formed to cover the top surface of the initial dummy board 400P, the side surfaces of the second semiconductor chips 300U, 300 and 300B, and the side surface of the dummy die 200. The release film RF may protect the exposed surface (e.g., bottom surface 200a) of the dummy die 200, and thus the molding layer 500P may not be formed on the exposed surface (e.g., bottom surface 200a) of the dummy die 200.

[0068] Reference Fig.9A and Fig. 9B , the release film RF may be removed, and the wafer WF may be bonded to the dummy die 200 by a hybrid bonding process. The wafer WF may include a portion on which a plurality of first semiconductor chips 100 are formed. Since the exposed surface (e.g., bottom surface 200a) of the dummy die 200 is flat, the wafer WF in contact with the dummy die 200 in the hybrid bonding process may not be bent but may be flat even if the wafer WF has a thin thickness. In addition, the exposed surface (e.g., bottom surface 200a) of the dummy die 200 may be flat to prevent misalignment between the dummy die 200 and the portion of the wafer WF on which the first semiconductor chip 100 is formed.

[0069] Next, a cutting process may be performed on the wafer WF, the mold layer 500P, and the initial dummy board 400P along the cutting lines SL to form Figure 1A and Figure 1B The first semiconductor chip 100, the molding structure 500 and the dummy board 400 are manufactured. Figure 1A and Figure 1B A semiconductor package 10 is provided.

[0070] Fig.10 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. Fig.11 is corresponding to Fig.10 A magnified view of area CU6. Fig.12 is corresponding to Fig.10 A magnified view of area CU6.

[0071] Reference Fig. 6A , Figure 6B and Fig.10 , a grinding process may be performed on the exposed surface (eg, bottom surface 200a) of the dummy die 200. Fig.10 and Fig.11 In the grinding process, the thickness of the lower dummy bonding pad 222 of the dummy die 200 may be reduced, and at least a portion of the lower dummy bonding pad 222 may be retained. Fig.11As shown, a first lower dummy bonding pad 2221 and a second lower dummy bonding pad 2222 having different thicknesses may be formed. Next, the same method as in reference may be performed. Fig. 8A and Fig.9A The same subsequent process described is used to manufacture Figure 4 and Figure 5A semiconductor packaging.

[0072] Alternatively, Fig.12 As shown, in the grinding process, the second lower dummy bonding pad 2222 of the dummy die 200 may be removed, the thickness of the first lower dummy bonding pad 2221 may be reduced, and a portion of the first lower dummy bonding pad 2221 may be retained. In this process, the thickness of the second dummy through electrode 252 may also be reduced. Next, the same process as in reference may be performed. Fig. 8A and Fig.9A The same subsequent process described is used to manufacture Figure 4 and Figure 5B semiconductor packaging.

[0073] Fig.13A is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. Fig. 13B It is conceptually shown Fig.13A A cross-sectional view of the top and bottom surfaces of a die.

[0074] Reference Fig. 6A , Fig.13A and Fig. 13B , the mold layer 500P may be formed to cover the top surface (e.g., bottom surface) 200a of the dummy die 200, the side surfaces of the dummy die 200, the side surfaces of the second semiconductor chips 300B, 300 and 300U, and the top surface (e.g., bottom surface 400a) of the initial dummy board 400P. A grinding process may be performed to expose the top surface (e.g., bottom surface 200a) of the dummy die 200 from the mold layer 500P. As a result of the grinding process, the top surface (e.g., bottom surface 200a) of the dummy die 200 may be flat, and the top surface (e.g., bottom surface 200a) of the dummy die 200 may be coplanar with the top surface 500a of the mold layer 500P. As a result of the grinding process, the dummy through-electrode 250 (see FIG. 2 ) of at least a portion of the dummy die 200 may be exposed. Figure 7C ). Alternatively, the thickness of the lower dummy bonding pad 222 of at least a portion of the dummy die 200 may be reduced, and a portion of the lower dummy bonding pad 222 may be retained (see Fig.11 and Fig.12 ). Can be executed and referenced Fig.9A The same subsequent process described is used to manufacture Figure 1A or Figure 4 semiconductor packaging.

[0075] Fig.14 is a plan view showing a semiconductor package according to some embodiments of the present disclosure. Fig.15 is along Fig.14 In order to clearly illustrate the components, Fig.14 Omitted Fig.15 Hereinafter, for the purpose of simplicity and convenience of explanation, the description of the features identical to the above-mentioned features will not be repeated.

[0076] Reference Fig.14 and Fig.15 According to some embodiments of the present disclosure, the semiconductor package 1000 may include a package substrate 40, an interposer 30, a third semiconductor chip 20, a plurality of semiconductor packages 10 (e.g., a chip stacking structure), and a bottom fill pattern (e.g., a first bottom fill pattern UF1, a second bottom fill pattern UF2, and a third bottom fill pattern UF3). Fig.14 and Fig.15 The semiconductor packages 10 may each correspond to the semiconductor packages 10 according to the above reference Figure 1A and Figure 4 A corresponding semiconductor package 10 of the described embodiment is shown.

[0077] For example, the package substrate 40 may be a printed circuit board (PCB). The package substrate 40 may include a lower metal pad 42, a first upper metal pad 43, a second upper metal pad 44, a metal line, and an external connection terminal 48. The first upper metal pad 43 and the second upper metal pad 44 may be disposed in the upper portion of the package substrate 40, and the lower metal pad 42 may be disposed in the lower portion of the package substrate 40. The first upper metal pad 43 may overlap with the semiconductor package 10 in the third direction D3. The second upper metal pad 44 may overlap with the third semiconductor chip 20 in the third direction D3. The first upper metal pad 43 and the second upper metal pad 44 may contact the first connection terminal 38 described below, respectively. The metal line may connect the first upper metal pad 43 and the second upper metal pad 44 to the lower metal pad 42. The external connection terminal 48 may be disposed on the lower metal pad 42, respectively. The external connection terminal 48 may include a conductive material such as solder.

[0078] The interposer 30 may be disposed on the package substrate 40. The interposer 30 may include a fourth semiconductor substrate 31, a fourth through electrode 35, an interconnection layer 32, and a first connection terminal 38. The fourth semiconductor substrate 31 may include a semiconductor material such as silicon and / or germanium, and may be, for example, a silicon substrate. The interconnection layer 32 may be disposed on the fourth semiconductor substrate 31. The interconnection layer 32 may include an insulating layer 324 and an interconnection structure 326 in the insulating layer 324. The insulating layer 324 may be an insulating layer such as a silicon oxide layer. The insulating layer 324 is shown as a single layer, but may include multiple insulating layers in some embodiments. The interconnection structure 326 may electrically connect the third semiconductor chip 20 to at least one semiconductor package 10. Each fourth through electrode 35 may penetrate the fourth semiconductor substrate 31, thereby being connected to the first connection terminal 38 through, for example, a pad.

[0079] The first underfill pattern UF1 may be disposed between the interposer 30 and the package substrate 40 . For example, the first underfill pattern UF1 may include an epoxy resin composite material. The first underfill pattern UF1 may fill the space between the first connection terminals 38 .

[0080] The third semiconductor chip 20 and the plurality of semiconductor packages 10 may be disposed on the interposer 30. For example, the third semiconductor chip 20 may be located on a central portion of the interposer 30. The semiconductor packages 10 may be spaced apart from each other in the first direction D1, with the third semiconductor chip 20 interposed between the semiconductor packages 10. Fig.14 As shown, two semiconductor packages 10 may be disposed adjacent to one side surface of the third semiconductor chip 20, and two semiconductor packages 10 may be disposed adjacent to the other side surface of the third semiconductor chip 20. Adjacent semiconductor packages 10 may be spaced apart from each other in the second direction D2.

[0081] In some embodiments, three semiconductor packages 10 may be disposed adjacent to one side surface of the third semiconductor chip 20, and three semiconductor packages 10 may be disposed adjacent to the other side surface of the third semiconductor chip 20. In some embodiments, the semiconductor packages 10 may be disposed differently.

[0082] The third semiconductor chip 20 may be a logic chip. For example, the third semiconductor chip 20 may be a central processing unit (CPU), a graphics processing unit (GPU), or an application-specific integrated circuit (ASIC). The third semiconductor chip 20 may be configured to send signals to and / or receive signals from the semiconductor package 10. The third semiconductor chip 20 may include a chip pad 22 disposed at a lower portion thereof. The second connection terminals 28 may be respectively disposed on the chip pads 22. The second connection terminals 28 may include a conductive material such as solder.

[0083] The second connection terminals 28 of the third semiconductor chip 20 and the connection terminals 180 of the semiconductor package 10 may contact the pads of the top surface of the interposer 30. The second underfill pattern UF2 may be disposed between the third semiconductor chip 20 and the interposer 30. The second underfill pattern UF2 may fill the space between the second connection terminals 28. The third underfill pattern UF3 may be disposed between the semiconductor package 10 and the interposer 30. The third underfill pattern UF3 may fill the space between the connection terminals 180. For example, the second underfill pattern UF2 and the third underfill pattern UF3 may include an epoxy resin composite material.

[0084] According to an embodiment of the present disclosure, the core die can be stacked sequentially on the dummy board. As a result, even if the thickness of the dummy board increases, when the dummy board is bonded to the core die, the appearance of the gap between the dummy board and the core die can be reduced, thereby improving the bonding strength between the dummy board and the core die. In addition, the thickness of the dummy board can be increased to improve the heat dissipation effect. The dummy die can be arranged between the buffer die and the core die, and the surface of the dummy die in contact with the buffer die can be flat. As a result, the misalignment between the buffer die and the dummy die can be reduced, and thus the dummy die can smoothly electrically connect the buffer die to the core die. The reliability of the semiconductor package can be improved by the above features.

[0085] While non-limiting example embodiments of the present disclosure have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: a first semiconductor chip; a dummy die on the first semiconductor chip; a second semiconductor chip stacked on the dummy die; as well as a dummy board, on the second semiconductor chip, wherein each of the first semiconductor chip, the dummy die and the second semiconductor chip comprises a through electrode, wherein the dummy die and a lowermost second semiconductor chip of the second semiconductor chips closest to the dummy die are connected to each other through direct contact of the first bonding pad, wherein adjacent ones of the second semiconductor chips are connected to each other through direct contact of the second bonding pads, The first semiconductor chip, the dummy die, the second semiconductor chip and the dummy board have a first width, a second width, a third width and a fourth width in a horizontal direction, respectively, and The fourth width is greater than the second width and the third width. 2 . The semiconductor package according to claim 1 , wherein the first width is equal to the fourth width. The semiconductor package according to claim 1 , wherein the second width is equal to the third width. 4 . The semiconductor package of claim 1 , wherein the dummy die does not include an integrated circuit and an interconnection pattern.

5. The semiconductor package of claim 1 , wherein the dummy die comprises a semiconductor substrate, in, A direction parallel to the top surface of the semiconductor substrate is defined as a first direction, Wherein, a direction perpendicular to the top surface of the semiconductor substrate is defined as a second direction, wherein a height variation amplitude of the top surface of the semiconductor substrate in the second direction toward the first direction is greater than a height variation amplitude of the bottom surface of the semiconductor substrate in the second direction toward the first direction, and The top surface is farther from the first semiconductor chip than the bottom surface.

6. The semiconductor package of claim 1 , wherein the dummy die comprises a semiconductor substrate, in, The semiconductor substrate includes a first region and a second region, and The thickness of the first region and the thickness of the second region differ from each other by 0.3 μm or more.

7. The semiconductor package according to claim 1, wherein the first semiconductor chip has a first thickness, in, The dummy die has a second thickness, wherein each of the second semiconductor chips has a third thickness, wherein the dummy plate has a fourth thickness, and Wherein, the fourth thickness is three times or greater than each of the first thickness, the second thickness, and the third thickness.

8. The semiconductor package according to claim 7, wherein: The first thickness is greater than the second thickness and the third thickness.

9. The semiconductor package according to claim 7, wherein: The second thickness is smaller than the third thickness.

10. The semiconductor package according to claim 1, wherein the through-electrode of the dummy die comprises: A first dummy through electrode has a first height; as well as a second dummy through electrode laterally spaced apart from the first dummy through electrode and having a second height, and Wherein, the first height is greater than the second height.

11. The semiconductor package according to claim 1, wherein the through-electrode of the dummy die comprises: a first dummy through-electrode; as well as a second dummy through-electrode, which is laterally spaced apart from the first dummy through-electrode; wherein a top surface of the first dummy through-electrode has a level higher than a top surface of the second dummy through-electrode, and The level of the bottom surface of the first dummy through-electrode is the same as the level of the bottom surface of the second dummy through-electrode.

12. The semiconductor package according to claim 1, wherein The dummy die comprises: a first dummy through-electrode; a second dummy through-electrode, which is laterally spaced apart from the first dummy through-electrode; a first bonding pad on a bottom surface of the first dummy through-electrode; and a second bonding pad on a bottom surface of the second dummy through-electrode, Wherein a first thickness of the first bonding pad is greater than a second thickness of the second bonding pad.

13. The semiconductor package according to claim 12, wherein: A first height of the first dummy through electrode is equal to a second height of the second dummy through electrode.

14. The semiconductor package according to claim 1, wherein: The dummy die comprises: a first dummy through-electrode; a second dummy through-electrode laterally spaced apart from the first dummy through-electrode; and a first bonding pad on a bottom surface of the first dummy through-electrode, The bottom surface of the first bonding pad is at the same level as the bottom surface of the second dummy through-electrode.

15. A semiconductor package, comprising: a first semiconductor chip; a dummy die, on the first semiconductor chip, a second semiconductor chip stacked on the dummy die; a dummy board on the second semiconductor chip; as well as A molding structure is located between the first semiconductor chip and the dummy board, wherein each of the first semiconductor chip, the dummy die and the second semiconductor chip comprises a through electrode, wherein the dummy die and the first semiconductor chip are connected to each other through direct contact of a first bonding pad, wherein the dummy die and the lowermost second semiconductor chip of the second semiconductor chips are connected to each other through direct contact of the second bonding pads, wherein adjacent ones of the second semiconductor chips are connected to each other through direct contact of the third bonding pads, wherein the dummy board and the uppermost second semiconductor chip among the second semiconductor chips are connected to each other through direct contact of an insulating material, and The molding structure is on a top surface of the first semiconductor chip, a side surface of the dummy die, a side surface of the second semiconductor chip, and a bottom surface of the dummy board.

16. The semiconductor package according to claim 15, wherein: The dummy board includes silicon, and Wherein, the insulating material includes silicon oxide.

17. The semiconductor package of claim 15, wherein the dummy die comprises a semiconductor substrate, in, A direction parallel to the top surface of the semiconductor substrate is defined as a first direction, Wherein, a direction perpendicular to the top surface of the semiconductor substrate is defined as a second direction, wherein a height variation amplitude of the top surface of the semiconductor substrate in the second direction toward the first direction is greater than a height variation amplitude of the bottom surface of the semiconductor substrate in the second direction toward the first direction, and The top surface of the semiconductor substrate is farther from the first semiconductor chip than the bottom surface of the semiconductor substrate. 18 . The semiconductor package according to claim 15 , wherein a thickness of the dummy board is 250 μm or more.

19. The semiconductor package according to claim 15, wherein the through-electrode of the dummy die comprises: A first dummy through electrode has a first height; as well as a second dummy through electrode laterally spaced apart from the first dummy through electrode and having a second height, and Wherein, the first height is greater than the second height.

20. A semiconductor package, comprising: Package substrate; an interposer, on the packaging substrate; A logic chip on the interposer; as well as A chip stacking structure spaced apart from each other, wherein the logic chip is interposed between the chip stacking structures, Wherein, each of the chip stacking structures comprises: Buffer core; a dummy die on the buffer die; A core die stacked on the dummy die; a dummy board on the core die; and A molded structure located between the buffer die and the dummy board, wherein each of the buffer die, the dummy die and the core die comprises a through electrode, wherein the dummy die and the buffer die are connected to each other through direct contact of the first bonding pad, wherein the dummy die and the lowermost core die among the core dies are connected to each other through direct contact of the second bonding pads, Wherein, adjacent core dies in the core dies are connected to each other through direct contact of the third bonding pads, The dummy board and the uppermost core tube core of the core tube cores are connected to each other through direct contact of insulating material. The molding structure is formed on the top surface of the buffer die, the side surface of the dummy die, the side surface of the core die, and the bottom surface of the dummy board. The buffer die, the dummy die, the core die and the dummy board have a first width, a second width, a third width and a fourth width in the horizontal direction, respectively. wherein the first width is equal to the fourth width, and The second width is equal to the third width.

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