Insert structure and package structure

Abstract

An interposer structure and a package structure are provided. The interposer structure includes a conductive portion, a dielectric layer, a plurality of first lines, and a plurality of second lines. The conductive portion has a first surface and a second surface opposite the first surface. The dielectric layer encapsulates the conductive portion and exposes the first surface and the second surface. The first line is formed on the first surface. The second wire is disposed over the second surface.

Description

Technical Field

[0001] The present disclosure generally relates to an interposer structure and a package structure. Background Art

[0002] Devices or semiconductor wafers can be bonded to each other via various hybrid bonding techniques. Currently, the devices and / or semiconductor wafers are bonded after a chemical mechanical polishing (CMP) process is performed on the devices and / or semiconductor wafers. The CMP process may cause the bonding surface on the devices and / or semiconductor wafers to be uneven, thereby reducing the bonding strength and thus degrading the device reliability. Summary of the invention

[0003] In one or more configurations, an interposer structure includes a conductive portion, a dielectric layer, a plurality of first wires, and a plurality of second wires. The conductive portion has a first surface and a second surface opposite to the first surface. The dielectric layer encapsulates the conductive portion and exposes the first surface and the second surface. The first wires are formed on the first surface. The second wires are disposed above the second surface.

[0004] In one or more configurations, a packaging structure includes a first substrate, a second substrate, and an insert. The second substrate is above the first substrate. The insert is between the first substrate and the second substrate. The insert includes a mesh portion and a dielectric layer. The mesh portion electrically connects the first substrate and the second substrate. The dielectric layer at least partially encapsulates the mesh portion and combines the first substrate and the second substrate.

[0005] In one or more configurations, a package structure includes a first substrate, a second substrate, and an interposer. The second substrate is above the first substrate. The interposer is between the first substrate and the second substrate. The interposer includes a conductive structure electrically connecting the first substrate and the second substrate. The conductive structure includes an upper portion, a lower portion, and a seed layer between the upper portion and the lower portion, a first void is formed in the upper portion, and a second void is formed in the lower portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are better understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that various features may not be drawn to scale and that the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a cross-section of an insert structure according to some configurations of the present disclosure.

[0008] Figure 1A is a cross-section of a package structure according to some configurations of the present disclosure.

[0009] Figure 1Bis a cross-section of a portion of a package structure according to some configurations of the present disclosure.

[0010] Figure 1C is a cross-section of a portion of a package structure according to some configurations of the present disclosure.

[0011] Figure 1D is a cross-section of a portion of a package structure according to some configurations of the present disclosure.

[0012] Figure 2A is a cross-section of a package structure according to some configurations of the present disclosure.

[0013] Figure 2B is a cross-section of a package structure according to some configurations of the present disclosure.

[0014] Figure 2C is a cross-section of a package structure according to some configurations of the present disclosure.

[0015] Figure 2D is a cross-section of a package structure according to some configurations of the present disclosure.

[0016] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Fig. 3I , Figure 3J , Figure 3K and Figure 3L Various stages of an exemplary method for manufacturing a package structure according to some embodiments of the present disclosure are shown.

[0017] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Various stages of an exemplary method for manufacturing a package structure according to some embodiments of the present disclosure are shown.

[0018] Common reference numerals are used throughout the drawings and detailed description to refer to the same or similar elements. The present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0019] Figure 1is a cross-section of an interposer structure 30A according to some configurations of the present disclosure. The interposer structure 30A may include one or more conductive portions (e.g., conductive vias 331 and 332), a dielectric layer (e.g., patterned dielectric layer 730), lines (e.g., lines 711, 712, 721A, and 722A), and a conductive layer (e.g., seed layers 341 and 342).

[0020] Conductive via 331 may have a surface 331a and a surface 331b opposite to surface 331a, and conductive via 332 may have a surface 332a and a surface 332b opposite to surface 332a. Conductive vias 331 and 332 are substantially free of voids (e.g., pores, air voids, air gaps, etc.). In some configurations, conductive vias 331 and 332 are spaced apart from each other by patterned dielectric layer 730A. In some configurations, conductive vias 331 and 332 taper from surfaces 331a and 332a toward surfaces 331b and 332b. Conductive vias 331 and 332 may independently include conductive materials such as metals or metal alloys. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0021] In some configurations, the patterned dielectric layer 730 may encapsulate the conductive vias 331 and 332 and expose the surfaces 331a, 331b, 332a, and 332b. In some configurations, the patterned dielectric layer 730 has an opening (or through hole), and the conductive vias 331 and 332 are disposed or formed in the opening. The patterned dielectric layer 730 may include polyimide (PI).

[0022] In some configurations, line 711 is formed on surface 331a, and line 712 is formed on surface 332a. In some configurations, line 711 and conductive via 331 are integrally formed into a single piece element or a monolithic structure. In some configurations, line 712 and conductive via 332 are integrally formed into a single piece element or a monolithic structure. In some configurations, there is no seed layer between line 711 and conductive via 331. In some configurations, conductive via 331 and line 711 are formed continuously. In some configurations, conductive via 331 and line 711 are continuously formed in the same plating process. In some configurations, conductive via 331 and line 711 have a substantially uniform grain size or a substantially uniform grain size distribution. In some configurations, the grain size of conductive via 331 is substantially the same as or close to the grain size of line 711. In some configurations, there is no seed layer between the line 712 and the conductive via 332. In some configurations, the conductive via 332 and the line 712 are formed continuously. In some configurations, the conductive via 332 and the line 712 are formed continuously in the same plating process. In some configurations, the conductive via 332 and the line 712 have a substantially uniform grain size or a substantially uniform grain size distribution. In some configurations, the grain size of the conductive via 332 is substantially the same as or close to the grain size of the line 712.

[0023] In some configurations, line 721A is disposed on or above surface 331b, and line 722A is disposed on or above surface 332b. In some configurations, lines 721A and 722A have a tapered profile. In some configurations, the distribution density of lines 721A and 722A is lower than the distribution density of lines 711 and 712. In some configurations, the width of lines 721A and 722A is greater than the width of lines 711 and 712. In some configurations, in a cross-sectional view, the spacing of line 711 is different from (e.g., less than) the spacing of line 721A. In some configurations, the spacing of line 712 is different from (e.g., less than) the spacing of line 722A. In some configurations, a portion of line 711 does not vertically overlap with line 721A. In some configurations, a portion of line 712 does not vertically overlap with line 722A.

[0024] In some configurations, seed layers 341 and 342 are between line 721A and conductive via 331. In some configurations, seed layers 341 and 342 are between line 722A and conductive via 332. In some configurations, in a cross-sectional view, conductive vias 331 and 332 taper toward seed layers 341 and 342. Seed layers 341 and 342 may independently include, for example, titanium (Ti), copper (Cu), nickel (Ni), another metal, an alloy such as titanium-tungsten alloy (TiW), or a combination thereof. In some configurations, seed layer 342 is made of or includes Cu, and seed layer 341 is made of or includes Ti.

[0025] Figure 1A is a cross-section of a package structure 1 according to some configurations of the present disclosure. The package structure 1 may include substrates 10, 20, and 20A, and an interposer (eg, a patterned interposer 30).

[0026] Substrates 10, 20, and 20A may independently include, for example, printed circuit boards, such as paper copper foil laminates, composite copper foil laminates, or polymer-impregnated fiberglass-based copper foil laminates. Substrates 10, 20, and 20A may independently include interconnect structures, which may include, for example, multiple conductive traces and / or multiple conductive vias. The interconnect structures may include redistribution layers (RDLs) and / or grounding elements. In some configurations, substrates 10, 20, and 20A may independently include organic substrates or lead frames. In some configurations, substrates 10, 20, and 20A may independently include ceramic materials or metal plates. In some configurations, substrates 10, 20, and 20A may independently include a double-layer substrate, which includes a core layer and conductive materials and / or structures disposed on the upper and bottom surfaces of the substrate. Substrates 10, 20, and 20A may independently include semiconductor wafers or electronic components. The electronic component may be a chip or die including a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. The integrated circuit devices may include active devices such as transistors, and / or passive devices such as resistors, capacitors, inductors, or a combination thereof. In some configurations, substrates 10, 20, and 20A may independently include one or more conductive elements, surfaces, contacts, or pads.

[0027] In some configurations, the substrate 10 includes a dielectric structure 100, a wiring structure 100R in the dielectric structure 100, dielectric layers 160 and 170 on opposite surfaces of the dielectric structure 100, and conductive pads 110 to 140 and 180 on opposite surfaces of the dielectric structure 100, respectively. In some configurations, the wiring structure 100R includes a plurality of wiring layers (or conductive layers) and a plurality of conductive vias connecting the wiring layers, and the dielectric structure 100 may include a plurality of dielectric layers (not shown) disposed between the wiring layers of the wiring structure 100R. In some configurations, the dielectric layer 160 defines one or more openings (e.g., notches 1601, 1602, 1603, and 1604) that expose one or more portions of the upper surface of the dielectric structure 100. In some configurations, the conductive pads 110, 120, 130, and 140 are disposed on the exposed upper surface of the dielectric structure 100 and are electrically connected to the wiring structure 100R. In some configurations, the conductive pad 180 is disposed on the bottom surface of the dielectric structure 100 and is electrically connected to the conductive pads 110 to 140 via the wiring structure 100R, and the dielectric layer 170 covers the bottom surface of the dielectric structure 100 and portions of the conductive pad 180. In some configurations, the dielectric layer 170 defines a plurality of openings (or recesses), and portions of the conductive pad 180 are exposed through the openings of the dielectric layer 170.

[0028] In some configurations, the recesses 1601, 1602, 1603, and 1604 each expose at least a portion of each conductive pad 110, 120, 130, and 140. In some configurations, the conductive pads 110, 120, 130, and 140 are each exposed by each recess 1601, 1602, 1603, and 1604. The substrate 10 may be referred to as or include a wiring structure, a circuit structure, a conductive structure, or a conductive carrier.

[0029] The substrate 20 may be disposed over the substrate 10. In some configurations, the substrate 20 is electrically connected to the substrate 10. In some configurations, the substrate 20 includes a substrate layer 201 (e.g., a semiconductor layer, such as a silicon-based layer), a dielectric layer 250 (also referred to as a "passivation layer") on the bottom surface of the substrate layer 201, and conductive pads 210 and 220 on the bottom surface of the substrate layer 201. In some configurations, the dielectric layer 250 has one or more openings (e.g., notches 2501 and 2502) that expose at least a portion of the conductive pads 210 and 220. The substrate 20 may include a semiconductor wafer or an electronic component. The electronic component may be or include a passive die or an active die, such as an application specific integrated circuit (ASIC) or any other type of active die.

[0030] In some configurations, the substrate 20A is electrically connected to the substrate 10. In some configurations, the substrate 20A includes a substrate layer 202 (e.g., a semiconductor layer, such as a silicon-based layer), a dielectric layer 260 (also referred to as a "passivation layer") on the bottom surface of the substrate layer 202, and conductive pads 230 and 240 on the bottom surface of the substrate layer 202. In some configurations, the dielectric layer 260 has one or more openings (e.g., notches 2601 and 2602) that expose at least a portion of the conductive pads 230 and 240. In some configurations, the substrate 20A (or the bottom surface 2001A of the substrate 20A) is not parallel to the substrate 10. The substrate 20A may include a semiconductor wafer or an electronic component. The electronic component may be or include a passive die or an active die, such as an ASIC or any other type of active die.

[0031] In some configurations, the patterned insert 30 is disposed between the substrate 10 and the substrates 20 and 20A. In some configurations, the patterned insert 30 electrically connects the substrate 10 to the substrates 20 and 20A. In some configurations, the patterned insert 30 includes an insulating layer 330A (also referred to as an "insulating buffer layer", "insulating portion" or "dielectric layer"), a patterned via layer 330V, a conductive portion (e.g., conductive portions 311, 312, 313, 314, 321, 322, 323 and 324), and a seed layer (e.g., seed layer structures 340 and 340'). The conductive portion may be referred to as or constitute one or more network portions that electrically connect the substrate 10 and the substrate 20. Multiple conductive portions may constitute a network portion, and one conductive portion may be referred to as a network of network portions. In some configurations, the patterned via layer 330V is within the insulating layer 330A or embedded in the insulating layer. The insulating layer 330A may be referred to as a dielectric layer that encapsulates the mesh portion and bonds the substrate 10 and the substrate 20. The patterned insert 30 may be referred to as a hybrid bond structure including the mesh portion and the insulating layer 330A. In some configurations, the conductive portions 311, 312, 313, 314, 321, 322, 323, and 324 are connected to the patterned via layer 330V. In some configurations, the conductive portions 311, 312, 313, 314, 321, 322, 323, and 324 electrically connect the substrate 10 to the substrates 20 and 20A. The patterned insert 30 may be composed of Figure 1 The insert structure 30A shown in FIG.

[0032] In some configurations, the insulating layer 330A contacts the dielectric layer 160. In some configurations, the rigidity of the insulating layer 330A is less than the rigidity of the dielectric layer 160. In some configurations, a portion of the insulating layer 330A extends within one or more recesses (e.g., recesses 1601, 1602, 1603, and 1603) of the dielectric layer 160. In some configurations, the insulating layer 330A extends over a portion of at least one side surface of the substrate 20. In some configurations, the insulating layer 330A extends over a portion of at least one side surface of the substrate 20A. In some configurations, the insulating layer 330A horizontally overlaps the substrate 10 or the substrate 20. In some configurations, the insulating layer 330A horizontally overlaps a portion of the mesh portion (e.g., one or more of the conductive portions 311, 312, 313, 314, 321, 322, 323, and 324). In some configurations, the insulating layer 330A is made of or includes one or more dielectric materials. In some configurations, the insulating layer 330A is made of or includes polyimide (PI). The insulating layer 330A may be made of Figure 1 The patterned dielectric layer 730 of the interposer structure 30A shown in FIG. 1 is formed.

[0033] In some configurations, the patterned via layer 330V includes a plurality of vias (e.g., conductive vias 331, 332, 333, and 334). In some configurations, the conductive vias 331, 332, 333, and 334 (also referred to as "conductive portions" or "via portions") are within or embedded in the insulating layer 330A. In some configurations, the conductive vias 331, 332, 333, and 334 are spaced apart from each other by the insulating layer 330A. The via portions may be inserted between the mesh portions. For example, the conductive via 331 may be inserted between the mesh portions formed by the conductive portions 311 and 321. In some configurations, the conductive vias 331, 332, 333, and 334 are substantially free of voids (e.g., holes, air voids, air gaps, etc.). In some configurations, the conductive vias 331, 332, 333, and 334 taper toward the substrates 20 and 20A. In some configurations, the insulating layer 330A and the patterned via layer 330V (e.g., conductive vias 331, 332, 333, and 334) collectively form the core layer 330 of the patterned interposer 30. In some configurations, the conductive vias 331, 332, 333, and 334 may be spaced apart from the substrate 10 and / or the substrate 20. In some other configurations, the conductive vias 331, 332, 333, and 334 may taper away from the substrates 20 and 20A (e.g., see FIG. 1 ). Figure 2A The structure shown in ).

[0034] In some configurations, the conductive portions 311, 312, 313, and 314 (also referred to as "conductors," "conductive meshes," "mesh portions," or "conductive porous structures") are connected or electrically connected to the substrate 10. In some configurations, the conductive portions 311, 312, 313, and 314 (or meshes) are proximal or near the substrate 10. The conductive mesh (or mesh portion) may be formed by two or more wires (e.g., nanowires) that cross and connect to each other. The conductive mesh (or mesh portion) may be formed by two or more wires (e.g., nanowires) that are interwoven. The conductive porous structure may be formed by a plurality of wires (e.g., nanowires) that intersect and connect to each other, such that holes or voids may be formed between the intersecting wires. In some configurations, the conductive portions 311, 312, 313, and 314 connect or electrically connect the patterned via layer 330V to the substrate 10. In some configurations, the conductive portions 311, 312, 313, and 314 are disposed above, below, outside, or protrude beyond the insulating layer 330A. In some configurations, the conductive portions 311, 312, 313, and 314 are spaced apart from each other. In some configurations, at least one or each of the conductive portions 311, 312, 313, and 314 has more holes (e.g., voids, air voids, air gaps, etc.) than the patterned via layer 330V. The holes may be formed by performing a bonding operation on wires (e.g., nanowires) that cross over, intersect, and / or tangle with each other. In some configurations, the conductive portion 311 may be formed by Figure 1 The conductive portion 312 may be formed by the wire 711 of the insert structure 30A shown in FIG. 1 , and the hole in the conductive portion 311 may be formed by performing a bonding operation on the wires 711 that cross each other, intersect each other, and / or entangle each other. In some configurations, the conductive portion 312 may be formed by Figure 1 30A, and the holes in the conductive portion 312 can be formed by performing a bonding operation on the wires 712 that cross each other, intersect each other, and / or entangle each other. In some configurations, the conductive portions 311, 312, 313, and 314 extend directly from the patterned via layer 330V. In some configurations, the conductive portions 311, 312, 313, and 314 each extend directly from each conductive via 331, 332, 333, and 334. In some configurations, a portion of one or more of the conductive portions 311, 312, 313, and 314 extends within one or more recesses (e.g., recesses 1601, 1602, 1603, and 1604) of the dielectric layer 160. In some configurations, one or more of the conductive portions 311 , 312 , 313 , and 314 can be at least partially located within one or more recesses (eg, recesses 1601 , 1602 , 1603 , and 1604 ) of the dielectric layer 160 .

[0035] In some configurations, one or more of the conductive portions 311, 312, 313, and 314 may be connected to or directly contact one or more of the corresponding conductive pads 110, 120, 130, and 140. In some configurations, one or more voids (e.g., holes, air voids, air gaps, etc.) may be formed between one or more of the conductive portions 311, 312, 313, and 314 and one or more of the corresponding conductive pads 110, 120, 130, and 140. For example, void v1 may be formed between the conductive portion 311 and the conductive pad 110. In some configurations, one or more voids (e.g., holes, air voids, air gaps, empty spaces, etc.) may be formed between one or more of the conductive portions 311, 312, 313, and 314 and one or more sidewalls of the recesses (e.g., recesses 1601, 1602, 1603, and 1604) of the dielectric layer 160. For example, void v2 can be formed between the conductive portion 312 and the sidewall of the recess 1602. In some configurations, the holes of the conductive portions 311, 312, 313, and 314 are larger than the holes of the conductive portions 321, 322, 323, and 324.

[0036] In some configurations, the conductive portions 321 and 322 (also referred to as "conductors", "conductive meshes" or "conductive porous structures") are connected or electrically connected to the substrate 20. The conductive mesh (or mesh structure) may be formed by two or more wires (e.g., nanowires) that cross and connect to each other. The conductive porous structure may be formed by a plurality of wires (e.g., nanowires) that intersect and connect to each other, so that holes or voids may be formed between the intersecting wires. In some configurations, the conductive portions 321 and 322 connect or electrically connect the patterned via layer 330V to the substrate 20. In some configurations, the conductive portions 321 and 322 are disposed above, below, outside, or protrude beyond the insulating layer 330A. In some configurations, at least one or each of the conductive portions 321 and 322 has more holes (e.g., voids, air voids, air gaps, etc.) than the patterned via layer 330V. The hole can be formed by performing a bonding operation on wires (e.g., nanowires) that cross each other, intersect each other, and / or entangle each other. In some configurations, the conductive portion 321 can be composed of Figure 1 The conductive portion 322 may be formed by the wire 721A of the insert structure 30A shown in FIG. 1 , and the hole in the conductive portion 321 may be formed by performing a bonding operation on the wires 721A that cross, intersect, and / or entangle with each other. In some configurations, the conductive portion 322 may be formed by Figure 1, and the holes in the conductive portion 322 can be formed by performing a bonding operation on the wires 722A that cross each other, intersect each other, and / or entangle each other. In some configurations, the seed layer structure 340 (or seed layer) is located between the conductive portions 321 and 322 and the patterned via layer 330V. In some configurations, each seed layer structure 340 is located between each conductive portion 321 and 322 and each conductive via 331 and 332. In some configurations, a portion of one or more of the conductive portions 321 and 322 extends within one or more recesses (e.g., recesses 2501 and 2502) of the dielectric layer 250. In some configurations, one or more of the conductive portions 321 and 322 may be at least partially located within one or more recesses (e.g., recesses 2501 and 2502) of the dielectric layer 250.

[0037] In some configurations, the conductive portions 323 and 324 (also referred to as "conductors", "conductive meshes" or "conductive porous structures") are connected or electrically connected to the substrate 20A. In some configurations, the conductive portions 323 and 324 connect or electrically connect the patterned via layer 330V to the substrate 20A. In some configurations, the conductive portions 323 and 324 are disposed above, below, outside, or protrude beyond the insulating layer 330A. In some configurations, at least one or each of the conductive portions 323 and 324 has more holes (e.g., voids, air voids, air gaps, etc.) than the patterned via layer 330V. In some configurations, the seed layer structure 340' is located between the conductive portions 323 and 324 and the patterned via layer 330V. In some configurations, each seed layer structure 340' is located between each conductive portion 323 and 324 and each conductive via 333 and 334. In some configurations, a portion of one or more of the conductive portions 323 and 324 extends within one or more recesses (e.g., recesses 2601 and 2602) of the dielectric layer 260. In some configurations, one or more of the conductive portions 323 and 324 may be at least partially located within one or more recesses (e.g., recesses 2601 and 2602) of the dielectric layer 260.

[0038] In some configurations, one or more of the conductive portions 321, 322, 323, and 324 may be connected to or directly contact one or more of the corresponding conductive pads 210, 220, 230, and 240. In some configurations, one or more voids may be formed between one or more of the conductive portions 321, 322, 323, and 324 and one or more of the corresponding conductive pads 210, 220, 230, and 240. In some configurations, the conductive portions 321, 322, 323, and 324 are spaced apart from each other. In some configurations, the conductive portions 321, 322, 323, and 324 (or meshes) are near or adjacent to the substrate 20. In some configurations, the density (or line density) of at least one of the conductive portions 321, 322, 323, and 324 is different from the density (or line density) of at least one of the conductive portions 311, 312, 313, and 314. In some configurations, a density (or line density) of at least one of conductive portions 321 , 322 , 323 , and 324 is less than a density (or line density) of at least one of conductive portions 311 , 312 , 313 , and 314 .

[0039] In some configurations, at least two or more of the conductive portions 311, 312, 313, 314, 321, 322, 323, and 324 are spaced apart from each other. In some configurations, at least one or each of the conductive portions 311, 312, 313, 314, 321, 322, 323, and 324 comprises a porous structure (e.g., a conductive porous structure). In some configurations, at least one or each of the conductive portions 311, 312, 313, 314, 321, 322, 323, and 324 has a conductive mesh structure (also referred to as a "conductive mesh").

[0040] In some configurations, conductive portions 311 and 321 are connected to conductive vias 331. In some configurations, conductive portions 311 and 321 have different numbers of holes (e.g., voids, air voids, air gaps, etc.). In some configurations, conductive portion 321 is connected to substrate 20 and conductive portion 311. In some configurations, conductive vias 331 are denser than conductive portions 311 and 321 (or conductive mesh). In some configurations, conductive portions 312 and 322 are connected to conductive vias 332. In some configurations, conductive portions 312 and 322 have different numbers of holes. In some configurations, conductive portion 322 is connected to substrate 20 and conductive portion 312. In some configurations, conductive vias 332 are denser than conductive portions 312 and 322 (conductive mesh). In some configurations, conductive portions 313 and 323 are connected to conductive vias 333. In some configurations, conductive portions 313 and 323 have different numbers of holes. In some configurations, conductive portion 323 is connected to substrate 20A and conductive portion 313. In some configurations, conductive via 333 is denser than conductive portions 313 and 323 (or conductive mesh). In some configurations, conductive portions 313 and 323 are connected to conductive via 333. In some configurations, conductive portions 314 and 324 have different numbers of holes. In some configurations, conductive portion 324 is connected to substrate 20A and conductive portion 314. In some configurations, conductive via 334 is denser than conductive portions 314 and 324 (or conductive mesh).

[0041] In some configurations, at least two or more of the conductive portions 311, 312, 313, and 314 have different thicknesses. In some configurations, at least two or more of the conductive portions 321, 322, 323, and 324 have different thicknesses. For example, the thickness of the conductive portion 321 may be different from the thickness of the conductive portion 323. In some configurations, the conductive portion 321 includes a porous structure that is recessed within the recess 2501 and does not protrude beyond the bottom surface of the substrate 20. In some configurations, the conductive portion 323 includes a porous structure that protrudes beyond the bottom surface of the substrate 20A.

[0042] In some configurations, the seed layer structures 340 and 340' contact the insulating layer 330A. In some configurations, each of the seed layer structures 340 and 340' includes seed layers 341 and 342. In some configurations, the insulating layer 330A horizontally overlaps the seed layer structures 340 and 340' (or the seed layers 341 and 342). In some configurations, the substrate 10 has a top surface 1001 facing the substrate 20, the substrate 20 has a bottom surface 2001 facing the substrate 10, and the seed layer structure 340 (or the seed layers 341 and 342) has an elevation between the elevation of the top surface 1001 of the substrate 10 and the elevation of the bottom surface 2001 of the substrate 20. The seed layer structures 340 and 340' may independently include, for example, titanium (Ti), copper (Cu), nickel (Ni), another metal, an alloy (such as titanium-tungsten alloy (TiW)), or a combination thereof.

[0043] In some configurations, the conductive portion 311 (also referred to as a "lower portion"), the conductive portion 321 (also referred to as an "upper portion"), the conductive via 331 (also referred to as a "via portion"), and the seed layers 341 and 342 may be referred to as conductive structures that electrically connect the substrate 10 and the substrate 20. In some configurations, the insulating layer 330A encapsulates the conductive structure. In some configurations, the elevation of the conductive via 331 (or via portion) is between the elevation of the top surface 1001 of the substrate 10 and the elevation of the bottom surface 2001 of the substrate 20.

[0044] In some configurations, the dielectric layer may independently include an organic material, a solder resist, PI, ABF, one or more molding compounds, one or more pre-impregnated composite fibers (e.g., prepreg materials), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination thereof, etc. The conductive layer, pad, and / or via may independently include a conductive material such as a metal or a metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0045] Figure 1B is a cross-section of a portion of a package structure according to some configurations of the present disclosure. In some configurations, Figure 1B yes Figure 1A 1B of the package structure 1 in cross section.

[0046] In some configurations, the seed layer structure 340 includes seed layers 341 and 342. In some configurations, the seed layers 341 and 342 are between the conductive portion 311 (or conductive mesh) and the conductive portion 321 (or conductive mesh). In some configurations, the seed layers 341 and 342 are made of different materials or include different materials. In some configurations, the seed layer 342 and the conductive portions 311 and 312 are made of the same material or include the same material, and the seed layer 341 has a relatively high etching selectivity relative to the conductive portions 311 and 312. The term "etching selectivity" used below indicates the ratio of the etching rate of the first material to the etching rate of the second material. In some configurations, the seed layer 342 and the conductive portions 311 and 312 are made of Cu or include Cu, and the seed layer 341 is made of Ti or includes Ti.

[0047] In some configurations, one or more voids v1 may be formed between the conductive portion 311 and the conductive pad 110. In some configurations, one or more voids v2 may be formed between the conductive portion 311 and the sidewall of the recess 1601 of the dielectric layer 160. In some configurations, one or more voids v3 may be formed between the conductive portion 321 and the conductive pad 210. In some configurations, one or more voids v4 may be formed between the conductive portion 321 and the sidewall of the recess 2501 of the dielectric layer 250. In some configurations, one or more empty spaces (e.g., voids v4) may be formed between the insulating layer 330A and a portion of the mesh portion (e.g., one or more of the conductive portions 311, 312, 313, 314, 321, 322, 323, and 324).

[0048] In some configurations, the conductive portion 311 has a plurality of voids v5, and the conductive portion 321 has a plurality of voids v6. In some configurations, the voids v5 are formed in the conductive portion 311, and the voids v6 are formed in the conductive portion 321. In some configurations, one or more of the voids v6 closer to the seed layer structure 340 is larger than one or more of the voids v5 away from the seed layer structure 340. In some configurations, the number of voids v6 is greater than the number of voids v5. In some configurations, from a cross-sectional view, the size of the voids v6 is greater than the size of the voids v5. In some configurations, the conductive portion 311 (or conductive mesh) is denser than the conductive portion 321 (or conductive mesh). In some configurations, the number or density of lines that cross and intersect each other to form the conductive portion 311 is greater than the number or density of lines that cross and intersect each other to form the conductive portion 321. In some configurations, the dielectric layer 160 defines one or more openings (e.g., notches 1601, 1602, 1603, and 1604), and the conductive portion 311 extends into the opening and includes a portion that does not contact the inner sidewall of the dielectric layer 160. The conductive portions 312, 313, 314, 322, 323, and 324 may have similar configurations according to the present disclosure. Figure 1B The structure shown in FIG. 1 is similar to the structure shown in FIG. 1 , and its description is omitted below.

[0049] Figure 1C is a cross-section of a portion of a package structure according to some configurations of the present disclosure. In some configurations, Figure 1C yes Figure 1A A cross section of a portion of the package structure 1 in FIG. 1 . In some configurations, Figure 1C yes Figure 1B A cross section of a portion of a structure in. In some configurations, Figure 1C is a cross section of a portion of the conductive portion 311 (or the conductive mesh).

[0050] In some configurations, the conductive portion 311 includes a porous structure defining voids v5. In some configurations, the conductive portion 311 includes a mesh structure defining pores (or voids v5). In some configurations, the mesh structure includes a plurality of wires (or nanowires) that cross and bond to each other. In some configurations, the voids v5 within the mesh structure of the conductive portion 311 have various shapes (e.g., irregular shapes) and various sizes.

[0051] In some configurations, the conductive portions 312, 313, 314, 321, 322, 323, and 324 may each have a configuration similar to that of some configurations according to the present disclosure. Figure 1C The structure shown in FIG. 1 is similar to the structure shown in FIG. 1 , and its description is omitted below.

[0052] Figure 1Dis a cross-section of a portion of a package structure according to some configurations of the present disclosure. In some configurations, Figure 1D yes Figure 1A A cross section of a portion of the package structure 1 in FIG. 1 . In some configurations, Figure 1D yes Figure 1B A cross section of a part of a structure.

[0053] In some configurations, the conductive portion 311 includes a porous structure defining a plurality of voids v5. In some configurations, the conductive portion 311 includes a plurality of wire segments (e.g., segments of nanowires) connected to each other. In some configurations, the voids v5 may be defined by adjacent bonded wire segments. In some configurations, the voids v5 within the porous structure of the conductive portion 311 have various shapes (e.g., irregular shapes) and various sizes.

[0054] In some cases where a dielectric layer (e.g., a silicon oxide layer) is used as a pre-bonding layer in a hybrid bonding structure, in order to provide sufficient Van der Waals interaction between the dielectric layers, it is required that the bonding surface of the dielectric layer has a relatively low surface roughness (e.g., less than 0.5 nm), and thus it is required to perform a CMP operation on the dielectric layer before the dielectric layers are bonded to each other. In addition, recessing of the conductive pad may occur after the CMP operation, and this may adversely affect the bonding between the conductive pads. Therefore, extra care is required to reduce the recessing of the conductive pad (e.g., less than about 5 nm).

[0055] According to some configurations of the present disclosure, the patterned insert includes a patterned conductive mesh formed of wires entangled and connected to each other to act as a pre-bonding layer to bond to each other. Therefore, the dielectric layer does not act as a pre-bonding layer and therefore does not need to have a low surface roughness. Therefore, the CMP operation can be omitted, the manufacturing operation can be simplified, and the cost can also be reduced.

[0056] In addition, according to some configurations of the present disclosure, the patterned insert further includes an insulating layer, which can act as a buffer layer to further compensate for the surface roughness of the dielectric layer relative to the substrate. Therefore, the dielectric layer does not need to have a low surface roughness. In addition, the insulating layer has a rigidity less than that of the dielectric layer, so the insulating layer can further provide a buffer to prevent the dielectric layer from being damaged or cracked due to impacting each other when combined with each other under pressure.

[0057] In addition, according to some configurations of the present disclosure, the insulating layer may include one or more organic dielectric materials having a Tg of less than about 180° C., and the organic dielectric material may soften and expand after heating to connect to the dielectric layer of the opposing substrate during manufacturing. In this way, the dielectric layer may have a relatively large surface roughness, and particles may be allowed on the bonding surface of the dielectric layer, and the softened organic dielectric material may fill the recesses, concave holes and / or cavities generated by the particles and the relatively large surface roughness of the dielectric layer. Therefore, the CMP operation may be omitted, and the cleaning operation for removing particles from the surface of the dielectric layer may also be omitted, and the bonding strength is still not adversely affected at all.

[0058] In addition, according to some configurations of the present disclosure, the softened organic dielectric material of the insulating layer can further fill the space between the bonded substrates (e.g., substrates 10 and 20) during manufacturing. In this way, although the bonded substrates may be tilted relative to each other or not parallel to each other, the substrates can be bonded to each other to a satisfactory degree without delamination. Therefore, the yield can be increased, the processing operations can be reduced, and the cost can also be reduced.

[0059] Figure 2A is a cross-section of a package structure 2A according to some configurations of the present disclosure. Figure 2A The package structure 2A shown in FIG. is similar to Figure 1A The packaging structures in , and the differences between them are described as follows.

[0060] In some configurations, substrate 20 is bonded to substrate 10 via patterned insert 30. In some configurations, conductive vias 331 and 332 taper toward substrate 10. In some configurations, conductive portions 311 and 312 are connected to or directly contact conductive pads 110 and 120, respectively. In some configurations, conductive portions 321 and 322 are connected to or directly contact conductive pads 210 and 220, respectively. In some configurations, the holes of conductive portions 311 and 312 are larger than the holes of conductive portions 321 and 322. In some configurations, the number of holes of conductive portions 311 and 312 is larger than the number of holes of conductive portions 321 and 322.

[0061] In some configurations, the substrate 10 includes a dielectric structure 100, a wiring structure 100R in the dielectric structure 100, a core layer 105, dielectric layers 160 and 170 on opposite surfaces of the dielectric structure 100, and conductive pads 110 to 120 and 180 on opposite surfaces of the dielectric structure 100, respectively. In some configurations, the wiring structure 100R includes a plurality of wiring layers 101L, 102L, 103L, 104L, and 170L (or conductive layers), a plurality of conductive vias 101V, 103V, and 104V, and a plurality of conductive vias 101T penetrating the core layer 105. The conductive vias 101T may include a conductive layer on a sidewall of the penetrating hole of the core layer 105 and a dielectric material filled in the penetrating hole surrounded by the conductive layer, and the conductive pad 110 is electrically connected to the conductive layer of the conductive via 101T. In some configurations, the dielectric structure 100 includes a plurality of dielectric layers 101, 102, and 103 disposed between the wiring layers 101L, 102L, 103L, and 170L. In some configurations, the dielectric structure 100 further includes at least one dielectric layer 104 disposed between the wiring layer 104L and the conductive pads 110 and 120. In some configurations, the conductive pads 110 and 120 are disposed on the conductive vias 101T and connected to the conductive pad 180 via the wiring structure 100R.

[0062] In some configurations, the substrate 20 includes a substrate layer 201, conductive pads 210 and 220, a dielectric layer 250, and a redistribution layer (RDL) 270. In some configurations, the RDL 270 includes a plurality of conductive layers 203L, 204L, and 205L, a plurality of conductive vias 203V, 204V, and 205V, and a plurality of dielectric layers 203, 204, and 205. One or more of the conductive layers 203L, 204L, and 205L may be or include a conductive pattern including a plurality of conductive pads. One or more of the conductive pads may include a seed layer portion and a pad portion formed directly on the seed layer portion. The conductive vias 203V, 204V, and 205V may include a seed layer portion and a via portion formed directly on the seed layer portion.

[0063] In some configurations, substrate 10 may be referred to as a “lower stacking structure” or a “low-density conductive structure”, and substrate 20 may be referred to as a “higher stacking structure” or a “high-density conductive structure”. In some configurations, the line width of the conductive structure (e.g., conductive layer, conductive pad, etc.) of substrate 10 is greater than the line width of the conductive structure (e.g., conductive layer, conductive pad, etc.) of substrate 20. In some configurations, the line spacing of the conductive structure (e.g., conductive layer, conductive pad, etc.) of substrate 10 is greater than the line spacing of the conductive structure (e.g., conductive layer, conductive pad, etc.) of substrate 20. In some configurations, the density of at least one of the conductive portions 321, 322, 323, and 324 is greater than the density of at least one of the conductive portions 311, 312, 313, and 314. In some configurations, at least one of the voids v6 within at least one of the conductive portions 321, 322, 323, and 324 is smaller than at least one of the voids within at least one of the conductive portions 311, 312, 313, and 314. In some configurations, package structure 2A may be referred to as a fan-out substrate (FOSUB) structure.

[0064] Figure 2B is a cross-section of a package structure 2B according to some configurations of the present disclosure. Figure 2B The package structure shown in 2B is similar to Figure 1A The packaging structures in , and the differences between them are described as follows.

[0065] In some configurations, the substrate 20 further includes a seed layer 280 between the substrate layer 201 and the conductive portions 321 and 322 , and the substrate 20A further includes a seed layer 280 ′ between the substrate layer 202 and the conductive portions 323 and 324 .

[0066] In some configurations, conductive portions 321 and 322 may be formed by bonding and annealing a wire extending from seed layer 280 and a wire extending from seed layer structure 340. In some configurations, there is substantially no void formed between seed layer 280 and conductive portion 321. In some configurations, there is substantially no void formed between seed layer 280 and conductive portion 322. In some configurations, conductive portions 323 and 324 may be formed by bonding and annealing a wire extending from seed layer 280' and a wire extending from seed layer structure 340'. In some configurations, there is substantially no void formed between seed layer 280' and conductive portion 323. In some configurations, there is substantially no void formed between seed layer 280' and conductive portion 324.

[0067] Figure 2C is a cross-section of a package structure 2C according to some configurations of the present disclosure. Figure 2C The package structure shown in 2C is similar to Figure 1A The packaging structures in , and the differences between them are described as follows.

[0068] In some configurations, the conductive portion 311 includes a porous structure and a filler metal portion that contacts the porous structure. The filler metal portion is configured to reduce the voids (e.g., voids v5) within the porous structure. The filler metal portion is configured to reduce the number and / or size of the voids (e.g., voids v5) within the porous structure. In some configurations, the filler metal portion is adjacent to the edge of the void v5. In some configurations, the porous structure includes a first metal, and the filler metal portion includes a solid solution of the first metal and a second metal different from the first metal. In some configurations, the first metal may be or include Cu, and the second metal may be or include germanium (Ge), gallium (Ga), silver (Ag), or a combination thereof. In some configurations, the filler metal portion may include a solid solution CuGe alloy, a solid solution CuGa alloy, a solid solution CuAg alloy, or a combination thereof. In some configurations, the filler metal portion may be exposed to the void v5. The filler metal portion may be characterized by EDS.

[0069] Figure 2D is a cross-section of a package structure 2D according to some configurations of the present disclosure. Figure 2D The package structure shown in 2D is similar to Figure 1A The packaging structures in , and the differences between them are described as follows.

[0070] In some configurations, substrates 20 and 20A are substantially parallel to substrate 10. In some configurations, conductive vias 331, 332, 333, and 334 taper toward substrate 10. In some configurations, substrate 10 further includes a seed layer 190 between dielectric structure 100 and conductive portions 321 and 322, and a seed layer 190' between dielectric structure 100 and conductive portions 323 and 324.

[0071] In some configurations, conductive portions 311 and 312 may be formed by bonding and annealing a wire extending from seed layer 280 and a wire extending directly from conductive vias 331 and 332. In some configurations, there is substantially no void formed between seed layer 280 and conductive portion 311. In some configurations, there is substantially no void formed between seed layer 280 and conductive portion 312. In some configurations, conductive portions 313 and 314 may be formed by bonding and annealing a wire extending from seed layer 280' and a wire extending directly from conductive vias 333 and 333. In some configurations, there is substantially no void formed between seed layer 280' and conductive portion 313. In some configurations, there is substantially no void formed between seed layer 280' and conductive portion 314.

[0072] In some configurations, conductive portions 321 and 322 may be formed by bonding and annealing a wire extending from seed layer 190 and a wire extending from seed layer structure 340. In some configurations, there is substantially no void formed between seed layer 190 and conductive portion 321. In some configurations, there is substantially no void formed between seed layer 190 and conductive portion 322. In some configurations, conductive portions 323 and 324 may be formed by bonding and annealing a wire extending from seed layer 190' and a wire extending from seed layer structure 340'. In some configurations, there is substantially no void formed between seed layer 190' and conductive portion 323. In some configurations, there is substantially no void formed between seed layer 190' and conductive portion 324.

[0073] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Fig. 3I , Figure 3J , Figure 3K and Figure 3L Various stages of an exemplary method for manufacturing a package structure 1 according to some embodiments of the present disclosure are shown.

[0074] See also Figure 3A , a carrier 600 may be provided, and conductive layers 741 and 742 may be formed on the carrier 600. In some configurations, the conductive layers 741 and 742 are made of or include different materials. In some configurations, the conductive layers 741 and 742 may act as seed layers in a subsequent plating process. The conductive layers 741 and 742 may be formed by sputtering.

[0075] See also Figure 3B , the patterned dielectric layer 730 may be formed on the conductive layer 742. In some configurations, the patterned dielectric layer 730 has openings (or recesses) that expose the surface of the conductive layer 742. The patterned dielectric layer 730 may include polyimide (PI).

[0076] See also Figure 3C, a template 610 including a plurality of holes 610H may be disposed above a surface of a patterned dielectric layer 730, lines 711 and 712 may be formed in the holes 610H of the template 610, and conductive vias 331 and 332 may be formed in the openings of the patterned dielectric layer 730. In some configurations, the lines 711 and 712 and the conductive vias 331 and 332 are formed by the same operation. In some configurations, a plating operation or a deposition operation may be performed to form the lines 711 and 712 and the conductive vias 331 and 332. In some configurations, the conductive vias 331 and 332 and the lines 711 and 712 are continuously formed in the same plating operation or the same deposition operation.

[0077] See also Figure 3D , the template 610 can be removed.

[0078] See also Figure 3E , the wires 711 and 712 may be covered by the colloid layer 620, and the carrier 630 may be disposed over the colloid layer 620. The colloid layer 620 may fill in the wires 711 and 712 and on the exposed surface of the patterned dielectric layer 730. The colloid layer 620 may serve as a protective layer for the wires 711 and 712.

[0079] See also Figure 3F , the carrier 600 can be removed.

[0080] See also Figure 3G , Figure 3F The structure shown in FIG. 6 may be flipped, a template 640 including a plurality of holes 640H may be disposed over a conductive layer 741, and wires 721, 722, and 723 may be formed in the holes 640H of the template 640. In some configurations, a plating operation or a deposition operation may be performed to form the wires 721, 722, and 723. In some configurations, the width of the wires 721, 722, and 723 is greater than the width of the wires 711 and 712. In some configurations, the distribution density of the wires 721, 722, and 723 is lower than the distribution density of the wires 711 and 712.

[0081] See also Figure 3H , the template 640 can be removed.

[0082] See also Fig. 3I, portions of conductive layers 741 and 742 may be removed to form seed layers 341 and 342, respectively. In some configurations, line 743 above the removed portions of conductive layers 741 and 742 is removed along with the removal of portions of conductive layers 741 and 742. In some configurations, an etching operation may be performed to remove portions of conductive layers 741 and 742 and line 723. In some configurations, lines 721 and 722 may be partially etched to form lines 721A and 722A having a reduced width and a tapered configuration. The distribution density of lines 721A and 722A is lower than the distribution density of lines 711 and 712. In some configurations, the width of lines 721A and 722A is greater than the width of lines 711 and 712.

[0083] See also Figure 3J , the carrier 630 and the colloid layer 620 may be removed. In this way, a patterned interposer including a patterned dielectric layer 730 (also referred to as an "insulating buffer layer"), conductive vias (e.g., conductive vias 331 and 332), and conductive lines (e.g., lines 711, 712, 721A, and 722A) may be formed. In this way, an interposer structure 30A may be formed.

[0084] See also Figure 3K , substrates 10A, 20, and 20A may be provided, and the substrates 20 and 20A may be connected or bonded to the substrate 10A through a patterned insert. The patterned insert may be disposed or sandwiched between the substrate 10 and the substrates 20 and 20A to bond the substrates 20 and 20A to the substrate 10A. The substrate 10A may include a dielectric structure 100, a wiring structure 100R in the dielectric structure 100, dielectric layers 160 and 170 on opposite surfaces of the dielectric structure 100, and conductive pads (e.g., conductive pads 110, 120, 130, 140, and 180) on opposite surfaces of the dielectric structure 100, respectively. Each substrate 20 may include a substrate layer 201, a dielectric layer 250 on a bottom surface of the substrate layer 201, and conductive pads 210 and 220 on a bottom surface of the substrate layer 201. Each substrate 20A may include a substrate layer 202 , a dielectric layer 260 on a bottom surface of the substrate layer 202 , and conductive pads 230 and 240 on a bottom surface of the substrate layer 202 .

[0085] In some configurations, the wires of the patterned insert are connected to the conductive pads of the substrates 10A, 20, and 20A. In some configurations, the wires of the patterned insert are at least partially disposed in recesses that expose the conductive pads of the substrates 10A, 20, and 20A. The wires may be connected or bonded to the conductive pads by thermal compression bonding (TCB). In some configurations, a sintering operation may be performed on the wires and the conductive pads to bond the wires to the corresponding conductive pads. The sintering operation may be performed at a temperature of about 170° C. to about 200° C. The sintering operation may be performed at a pressure of about 200 MPa to about 230 MPa (e.g., about 215 MPa). The sintering operation may be performed for about 40 seconds to about 2 minutes, for example, about 1 minute.

[0086] In some configurations, this can be omitted Fig. 3I 6, a patterned insert supported by a carrier 630 may be provided, and substrates 20 and 20A may be bonded to the lines of the patterned insert supported by the carrier 630. Next, the carrier 630 may be removed, and the lines of the patterned insert opposite the substrates 20 and 20A may be bonded to the substrate 10A to form Figure 3K The structure shown in .

[0087] See also Figure 3L , an annealing operation may be performed on the sintered wire to form a conductive mesh (e.g., conductive portions 311, 312, 313, 314, 321, 322, 323, and 324) that connects the conductive pads (e.g., conductive pads 110, 120, 130, 140, 210, 220, 230, and 240) of the substrates 10A, 20, and 20A to the conductive vias (e.g., conductive vias 331, 332, 333, and 334) of the patterned insert. Next, a singulation operation may be performed on the substrate 10A after the annealing operation to form package structures 1 and 1'. The package structure 1' has a structure similar to that of the package structure 1, except that the insulating layer 330A has a different structure. For example, the insulating layer 330A of the package structure 1 has an edge substantially aligned with an edge of the substrate 10 adjacent to the substrate 20A, and the insulating layer 330A of the package structure 1 ′ has an edge substantially aligned with an edge of the substrate 10 adjacent to the substrate 20 .

[0088] In some configurations, substrate 10 may be connected to substrate 20 by connecting conductive pads 110, 120, 130, and 140 to conductive pads 210, 220, 230, and 240 via a conductive mesh (e.g., conductive portions 311, 312, 313, 314, 321, 322, 323, and 324) of a patterned insert. In some configurations, a conductive mesh having voids or holes may be formed by an annealing operation performed on the wires. In some configurations, the annealing operation causes metal atoms (e.g., Cu atoms) of the sintered wires to diffuse and then form a conductive mesh. In some configurations, voids formed in a conductive mesh formed by wires having a larger width and / or a lower distribution density may be larger than voids formed in a conductive mesh formed by wires having a smaller width and / or a higher distribution density. In some configurations, the number of voids formed in a conductive mesh formed by lines having a larger width and / or a lower distribution density may be greater than the number of voids formed in a conductive mesh formed by lines having a smaller width and / or a higher distribution density. In some configurations, the number of voids formed in conductive portions 321, 322, 323, and 324 is greater than the number of voids formed in conductive portions 311, 312, 313, and 314. In some configurations, the voids formed in conductive portions 321, 322, 323, and 324 are greater than the voids formed in conductive portions 311, 312, 313, and 314.

[0089] In some other configurations, before performing the annealing operation, a filler metal may be placed in the sintered wire or at least partially cover the sintered wire. The filler metal may be placed in the holes of the sintered wire. The filler metal may include Ge, Ga, Ag, Cu, or a combination thereof. Ge and / or Ga that are liquid at room temperature may be directly placed in the sintered wire or at least partially cover the sintered wire. Ag and / or Cu may be placed in the sintered wire or at least partially cover the sintered wire by an electroless plating operation. After placing the filler metal, the size and number of voids or holes formed in the conductive mesh after the annealing operation may be reduced. After performing the annealing operation after placing the filler metal, a package structure 2C may be formed.

[0090] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Various stages of an exemplary method for manufacturing a package structure 2D according to some embodiments of the present disclosure are shown.

[0091] See also Figure 4A , which can be executed similar to Figures 3A-3D712 to form conductive vias (e.g., conductive vias 331 and 332) embedded in patterned dielectric layer 730 and lines (e.g., lines 711 and 712) extending directly from the conductive vias. A substrate 20 including substrate layer 201, seed layer 280, dielectric layer 250, and lines 811 and 812 may be provided, and lines 811 and 812 may be connected to lines 711 and 712 by a sintering operation. The sintering operation for bonding the lines to each other may be performed at room temperature. In some configurations, additional conductive vias may be formed within patterned dielectric layer 730, additional lines may be formed directly on the additional conductive vias, and one or more additional substrates (e.g., Figure 4E The substrate 20A shown in FIG. 20A may be connected to the additional lines.

[0092] See also Figure 4B , which can be executed similar to Figure 3L The operation shown in FIG. 3 is to anneal the connected wires to form a conductive mesh (eg, conductive portions 311 and 312 ).

[0093] See also Figure 4C , the carrier 630 can be removed.

[0094] See also Figure 4D , which can be executed similar to Figure 3G-3I The operations shown in are to form lines (eg, lines 711A and 712A) on a side of the patterned dielectric layer 730 opposite the conductive mesh connected to the substrate 20 .

[0095] See also Figure 4E , which can be executed similar to Figure 3K and 3L The operations shown in FIG. 1 are performed to connect the wire to the substrate 10. In some configurations, a similar operation may be performed. Figure 3K and 3L The operations shown in FIG. 3 are to connect the substrates 20 and 20A to the substrate 10 via the conductive mesh on the insulating layer 330A. In this way, the package structure 2D can be formed.

[0096] Unless otherwise specified, spatial descriptions such as "above", "below", "up", "left", "right", "lower", "top", "bottom", "vertical", "horizontal", "side", "above", "below", "upper", "above", "below", etc. are indicated relative to the orientation shown in the figure. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that embodiments of the structures described herein may be spatially configured in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not deviated by such configurations.

[0097] As used herein, the terms "approximately," "substantially," "generally," "about," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, these terms may refer to instances where the event or circumstance occurred exactly as well as instances where the event or circumstance occurred very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation of less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value may be considered to be "substantially" the same as or equal to the second numerical value. For example, "substantially" vertical can refer to an angular variation range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0098] If the displacement between the two surfaces is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar. If the displacement between the highest point and the lowest point of a surface is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm, then the surface can be considered to be substantially flat.

[0099] As used herein, the singular forms "a," "an," and "the" may include plural or plural referents unless the context clearly indicates otherwise.

[0100] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to carry an electric current. Conductive materials are materials that present little or no resistance to the flow of electric current. One unit of measurement for conductivity is Siemens per meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m, for example at least 10 5 S / m or at least 10 6 S / m of a material. The conductivity of a material sometimes varies with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0101] In addition, amounts, ratios and other numerical values ​​are sometimes presented herein in a range format. It should be understood that such a range format is used for the sake of convenience and brevity, and should be flexibly construed to include not only the values ​​explicitly specified as the limits of the range, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly specified.

[0102] Although the present disclosure has been described and illustrated with reference to the specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes may be made and equivalents may be replaced without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in the present disclosure and the actual equipment. There may be other embodiments that are not specifically described in the present disclosure. The description and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to make specific situations, materials, material compositions, methods or processes suitable for the goals, spirit and scope of the present disclosure. All such modifications are deemed to be included within the scope of the appended claims. Although the disclosed method has been described herein with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. An insert structure, comprising: a conductive portion having a first surface and a second surface opposite to the first surface; a dielectric layer encapsulating the conductive portion and exposing the first surface and the second surface; a plurality of first lines formed on the first surface; as well as A plurality of second wires are disposed above the second surface.

2. The insert structure according to claim 1, wherein: In a cross-sectional view, a pitch of the plurality of first lines is different from a pitch of the plurality of second lines. 3 . The interposer structure of claim 1 , further comprising a seed layer between the conductive portion and the plurality of second lines.

4. The insert structure according to claim 3, wherein: In a cross-sectional view, the conductive portion tapers toward the seed layer. 5 . The insert structure of claim 4 , wherein a portion of the plurality of first electric wires does not vertically overlap with the plurality of second electric wires. The interposer structure according to claim 4 , wherein the conductive portion and the plurality of first lines are continuously formed.

7. A packaging structure, comprising: a first substrate; a second substrate overlying the first substrate; as well as An inserter, which is between the first substrate and the second substrate, the inserter comprising: a mesh portion electrically connecting the first substrate and the second substrate; as well as A dielectric layer at least partially encapsulates the web portion and bonds the first substrate to the second substrate. 8 . The package structure according to claim 7 , wherein the interposer further comprises a through hole portion inserted between the mesh portions. 9 . The package structure according to claim 8 , wherein the through-hole portion is separated from the first substrate or the second substrate. 10 . The package structure according to claim 7 , wherein the dielectric layer horizontally overlaps the web portion. 11 . The package structure according to claim 7 , wherein the mesh portion includes a first mesh on a proximal side of the first substrate and a second mesh on a proximal side of the second substrate, and a line density of the first mesh is different from a line density of the second mesh. 12 . The package structure according to claim 11 , wherein the second substrate comprises a die, and the circuit density of the second web is greater than the circuit density of the first web.

13. A packaging structure, comprising: a first substrate; a second substrate overlying the first substrate; as well as an insert between the first substrate and the second substrate, the insert comprising a conductive structure electrically connecting the first substrate and the second substrate, The conductive structure includes an upper portion, a lower portion, and a seed layer between the upper portion and the lower portion, a first void is formed in the upper portion, and a second void is formed in the lower portion.

14. The packaging structure according to claim 13, wherein the first substrate has a top surface facing the second substrate, the second substrate has a bottom surface facing the first substrate, and the elevation of the seed layer is between the elevation of the top surface of the first substrate and the elevation of the bottom surface of the second substrate. 15 . The package structure of claim 14 , wherein the interposer further comprises a dielectric layer encapsulating the conductive structure, and the dielectric layer horizontally overlaps the seed layer. The package structure according to claim 15 , wherein the dielectric layer horizontally overlaps the first substrate or the second substrate. 17 . The package structure of claim 14 , wherein the conductive structure further comprises a via portion between the lower portion and the seed layer, and the via portion tapers toward the seed layer. 18 . The package structure of claim 17 , wherein the via portion is between the elevation of the top surface of the first substrate and the elevation of the bottom surface of the second substrate. 19 . The package structure according to claim 17 , wherein, in a cross-sectional view, a size of the first void is greater than a size of the second void. 20 . The package structure of claim 14 , wherein the first substrate comprises a first dielectric layer defining a first opening, and the lower portion extends into the first opening, wherein a portion of the lower portion does not contact an inner sidewall of the first opening.

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