Chip packaging structure, preparation method and electronic device
By designing a stacked chip packaging structure, including a first interconnection unit, a glass core plate unit, a second interconnection unit and a chip unit, and wrapping the side walls of the chip and the glass core plate in the packaging unit, the stability problem caused by the exposure of the glass core plate is solved, and a higher stability and reliability of the chip packaging structure is achieved.
Patent Information
- Application Number
- CN202411812001.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-03-11
AI Technical Summary
In the packaging methods of existing semiconductor devices, the glass core plate is often exposed, which reduces the stability of the chip packaging structure and may affect the product yield.
A chip packaging structure is designed, by stacking the first interconnection unit, the glass core plate unit, the second interconnection unit and the chip unit in sequence, and wrapping the side walls of the chip and the glass core plate in the packaging unit to form a packaging structure to protect the glass core plate.
Through effective packaging of glass core plates, the stability of the chip packaging structure is significantly improved, the overall mechanical performance and reliability are enhanced, and the adverse impact on product yield is reduced.
Smart Images
Figure CN119601562A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing, and more specifically, to a chip packaging structure, a preparation method and an electronic device. Background Art
[0002] In the field of semiconductor device packaging technology, glass core boards are favored for their excellent thermal stability, low expansion coefficient, excellent insulation and high strength. The use of glass core boards has significantly improved the performance and reliability of electronic devices. However, in the current packaging methods on the market, glass core boards are often exposed, which not only reduces the stability of the chip packaging structure, but may also have an adverse effect on product yield. Summary of the invention
[0003] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a chip packaging structure, the chip packaging structure includes a first interconnection unit, a glass core board unit, a second interconnection unit and a chip unit which are stacked in sequence, wherein the wires in the first interconnection unit and the wires in the second interconnection unit are connected through the glass core board unit, the chip unit includes at least one chip, the pin side of the chip is arranged toward the second interconnection unit and is electrically connected to the second interconnection unit;
[0004] The chip packaging structure also includes a packaging unit, which is located at least around the chip. The packaging unit is also located on the side walls of the glass core board unit and the side walls of the first interconnection unit, and the peripheral side of the second interconnection unit is exposed relative to the packaging unit.
[0005] In a possible implementation, the encapsulation unit includes a first encapsulation unit and a second encapsulation unit;
[0006] The first packaging unit wraps around the chip, the second packaging unit covers the side walls of the first interconnection unit and the side walls of the glass core board unit, the first packaging unit and the second packaging unit are not connected, wherein the first packaging unit and the second packaging unit are separated by the second interconnection unit, and the materials of the first packaging unit and the second packaging unit are different.
[0007] In a possible implementation manner, at a position of a side wall of the second interconnection unit, the first encapsulation unit, the second encapsulation unit, and the side wall of the second interconnection unit form a flat plane.
[0008] In a possible implementation manner, the orthographic projection of the first packaging unit on the second interconnection unit is at least partially located outside the orthographic projection of the chip unit on the second interconnection unit;
[0009] The orthographic projection of the second packaging unit on the second interconnection unit does not overlap with the orthographic projection of the first interconnection unit on the second interconnection unit, and the orthographic projection of the second packaging unit on the second interconnection unit overlaps with the orthographic projection of the glass core board unit on the second interconnection unit.
[0010] In one possible implementation, the thickness of the second packaging unit at the side wall of the first interconnected unit is a first thickness, and the thickness of the second packaging unit at the side wall of the glass core board unit is a second thickness, and the first thickness is greater than the second thickness, and the first thickness is 5 microns to 50 microns more than the second thickness.
[0011] In a possible implementation, the side wall of the first interconnected unit, the side wall of the glass core plate unit, and the side wall of the second interconnected unit form a step structure;
[0012] The side wall of the second interconnected unit extends relative to the side wall of the glass core plate unit to form a first step structure, and the side wall of the glass core plate unit extends relative to the side wall of the first interconnected unit to form a second step structure.
[0013] In a possible implementation, the chip packaging structure further includes a conductive ball, the conductive ball is located on a side of the first interconnect unit away from the glass core board unit, and the conductive ball is connected to a wire in the first interconnect unit.
[0014] Another object of the present application is to provide a method for preparing a chip packaging structure, the method comprising:
[0015] A wafer to be cut is provided, wherein the wafer to be cut comprises a first interconnection layer, a glass core board, a second interconnection layer, a chip layer and a packaging layer which are stacked in sequence, the chip layer comprises a plurality of chip units, a gap channel exists between two adjacent chip units, each of the chip units comprises at least one chip, and a pin side of the chip is arranged toward the second interconnection layer and is electrically connected to the second interconnection layer;
[0016] Performing a first cutting on the first interconnect layer along the gap channels between adjacent chip units, and dividing the first interconnect layer into a plurality of first interconnect units through the formed first cutting channels;
[0017] Performing a second cutting on the glass core board along the first cutting channel, dividing the glass core board into a plurality of glass core board units through the formed second cutting channel;
[0018] Glue is filled in the channel formed by cutting, and the packaging glue, the second interconnection layer and the packaging layer are cut along the gap channel between adjacent chip units to obtain a chip packaging structure.
[0019] In a possible implementation manner, a width of a first cutting channel formed by the first cutting is greater than a width of a second cutting channel formed by the second cutting.
[0020] Another object of the present application is to provide an electronic device, which includes a chip packaging structure provided by multiple chip packaging structures provided by the present application or a chip packaging structure prepared by a preparation method of multiple chip packaging structures provided by the present application.
[0021] Based on any one of the above aspects, the embodiments of the present application provide a chip packaging structure, a preparation method and an electronic device. In this way, the above structure can realize the packaging of the glass core board unit and improve the stability of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0023] Figure 1 One of the schematic diagrams of a chip packaging structure provided in this embodiment;
[0024] Figure 2 for Figure 1 A partial enlarged view of the dotted box in the middle;
[0025] Figure 3 A second schematic diagram of a chip packaging structure provided in this embodiment;
[0026] Figure 4 A step diagram of a method for preparing a chip packaging structure provided in this embodiment;
[0027] Figure 5 for Figure 4 Corresponding process flow chart.
[0028] Icons: chip packaging structure-1, first interconnection layer-10, glass core board-11, second interconnection layer-12, chip layer-13, packaging layer-14, first interconnection unit-100, side wall of the first interconnection unit-1001, glass core board unit-110, side wall of the glass core board unit-1101, second interconnection unit-120, side wall of the second interconnection unit-1201, chip unit-130, chip-1301, pin side-13010, packaging unit-140, first packaging unit-1401, second packaging unit-1402, conductive ball-150. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0030] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0031] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0032] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0033] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0034] In order to solve the technical problems mentioned in the aforementioned background technology, the inventor innovatively designed the following technical solution, and the specific implementation solution of the present application will be described in detail below with reference to the accompanying drawings.
[0035] See also Figure 1 , Figure 1 This is one of the schematic diagrams of a chip packaging structure 1 provided in this embodiment. The chip packaging structure 1 includes a first interconnect unit 100, a glass core board unit 110, a second interconnect unit 120 and a chip unit 130 which are stacked in sequence. The wires in the first interconnect unit 100 and the wires in the second interconnect unit 120 are connected through the glass core board unit 110, and the chip unit 130 includes at least one chip 1301, and the pin side 13010 of the chip 1301 is arranged toward the second interconnect unit 120 and is electrically connected to the second interconnect unit 120.
[0036] In this embodiment, the wires in the first interconnection unit 100 and the wires in the second interconnection unit 120 are interconnected through the glass core board unit 110. The glass core board unit 110 ensures stable and efficient transmission of electrical signals between the two layers of interconnection units due to its unique low thermal expansion coefficient and excellent insulation performance, which not only improves the quality of signal transmission, but also significantly enhances the thermal stability of the entire chip packaging structure 1. The chip unit 130 includes at least one chip 1301, whose pin side 13010 faces the second interconnection unit 120 and is electrically connected thereto, so that the chip 1301 can be effectively connected to the external circuit to realize signal input and output.
[0037] It is worth noting that the chip unit 130 includes at least one chip 1301. The chip 1301 can be a high bandwidth memory (HBM) or an application-specific integrated circuit (ASIC), etc. The number and type of the chip 1301 are not specifically limited here and need to be selected according to actual conditions.
[0038] The chip packaging structure 1 also includes a packaging unit 140 , which is located at least around the chip 1301 , and is also located on the side walls of the glass core board unit 110 and the first interconnection unit 100 . The peripheral side of the second interconnection unit 120 is exposed relative to the packaging unit 140 .
[0039] In this embodiment, the packaging unit 140 is located at least around the chip 1301 and the side walls of the glass core board unit 110 and the side walls of the first interconnection unit 100. Its main function is to protect internal devices and prevent external physical damage and environmental factors (such as moisture, temperature changes, etc.) from affecting the internal components.
[0040] Further, please see again Figure 1 The encapsulation unit 140 includes a first encapsulation unit 1401 and a second encapsulation unit 1402 .
[0041] The first packaging unit 1401 wraps around the chip 1301, and the second packaging unit 1402 covers the side walls of the first interconnection unit 100 and the side walls of the glass core board unit 110. The first packaging unit 1401 and the second packaging unit 1402 are not connected, wherein the first packaging unit 1401 and the second packaging unit 1402 are separated by the second interconnection unit 120, and the materials of the first packaging unit 14010 and the second packaging unit 1402 are different.
[0042] In this embodiment, the first packaging unit 1401 and the second packaging unit 1402 are separated by the second interconnection unit 120. The first packaging unit 1401 and the second packaging unit 1402 use different materials to achieve different packaging requirements, which helps to isolate different functional areas and reduce potential interference and thermal management problems. For example, the first packaging unit 1401 is used to wrap around the chip 1301. The material of the first packaging unit 1401 can be epoxy molding compound (EMC). EMC can effectively fix the chip 1301 to prevent it from displacement during the packaging process, while providing mechanical support and electrical insulation to ensure that the chip 1301 will not be physically damaged during the packaging process, and effectively isolate the electrical connection between the chip 1301 and the external circuit to prevent electrical short circuits and signal interference. In addition, EMC also has good bonding ability, ensuring the close combination of the first packaging unit 1401 and the chip 1301, and improving the reliability and stability of the package.
[0043] The second packaging unit 1402 covers the side wall of the first interconnection unit 100 and the side wall of the glass core board unit 110. The second packaging unit 1402 can be a resin material, such as epoxy resin. Epoxy resin has excellent mechanical properties and bonding ability, and can prevent physical damage and erosion by environmental factors. In addition, epoxy resin also has a certain elasticity, which can effectively absorb and disperse external impact and vibration, and protect the devices inside the chip packaging structure 1.
[0044] Further, please see again Figure 1 At the side wall position of the second interconnect unit 120 , the first encapsulation unit 1401 and the second encapsulation unit 1402 form a flat plane with the side wall of the second interconnect unit 120 .
[0045] In this embodiment, the first packaging unit 1401 and the second packaging unit 1402 are separated by the second interconnection unit 120. At the same time, the side walls of the first packaging unit 1401, the second packaging unit 1402 and the second interconnection unit 120 form a complete and continuous plane, which not only significantly improves the overall appearance of the chip packaging structure 1, but also ensures the integrity and mechanical stability of the chip packaging structure 1.
[0046] Further, please see again Figure 1, the orthographic projection of the first packaging unit 1401 on the second interconnect unit 120 is at least partially located outside the orthographic projection of the chip 1301 unit 130 on the second interconnect unit 120 .
[0047] The orthographic projection of the second packaging unit 1402 on the second interconnection unit 120 does not overlap with the orthographic projection of the first interconnection unit 100 on the second interconnection unit 120 , and the orthographic projection of the second packaging unit 1402 on the second interconnection unit 120 overlaps with the orthographic projection of the glass core board unit 110 on the second interconnection unit 120 .
[0048] In this embodiment, when the second interconnect unit 120 is used as a reference plane, the orthographic projection range of the first packaging unit 1401 is outside the orthographic projection range of the chip unit 130, which means that the first packaging unit 1401 tightly wraps the chip unit 130, and the chip unit 130 is the core component of the entire chip packaging structure 1, and the first packaging unit 1401 provides it with necessary physical protection and electrical isolation.
[0049] The second packaging unit 1402 covers the side walls of the first interconnected unit 100 and the side walls of the glass core board unit 110, while the orthographic projection range of the second packaging unit 1402 does not overlap with the orthographic projection range of the first interconnected unit 100, but overlaps with the orthographic projection range of the glass core board unit 110, which means that the glass core board unit 110 extends out compared to the first interconnected unit 100 to form a unique step structure, which not only increases the contact area between the side walls of the first interconnected unit 100 and the side walls of the glass core board unit 110 and the second packaging unit 1402, but also makes the thickness of the second packaging unit 1402 different at the side wall position of the first interconnected unit 100.
[0050] Specifically, see Figure 2 , Figure 2 for Figure 1 A partial enlarged view of the dotted box in the middle. The thickness of the second encapsulation unit 1402 at the side wall 1001 of the first interconnected unit is greater than the thickness of the second encapsulation unit 1402 at the side wall 1101 of the glass core plate unit. The thickness of the second encapsulation unit 1402 at the side wall 1001 of the first interconnected unit is the first thickness h1, and the thickness of the second encapsulation unit 1402 at the side wall 1101 of the glass core plate unit is the second thickness h2. The first thickness h1 is 5 to 50 microns more than the second thickness h2. For example, the first thickness h1 is 5, 10, 15, 20, 25, 30, 35, 40, 45, and 50 microns more than the second thickness h2.
[0051] For further information, see Figure 2The side wall 1001 of the first interconnected unit, the side wall 1101 of the glass core unit and the side wall 1201 of the second interconnected unit form a step structure. The side wall 1201 of the second interconnected unit extends relative to the side wall 1101 of the glass core unit to form a first step structure, and the side wall 1101 of the glass core unit extends relative to the side wall 1001 of the first interconnected unit to form a second step structure.
[0052] In this embodiment, the step structure design can provide additional support to enhance the overall strength and stability of the chip packaging structure 1. At the same time, the step structure design can provide more contact area for the packaging unit 140, which helps to closely combine the packaging unit 140 with the first interconnection unit 100, the glass core board unit 110 and the second interconnection unit 120, thereby improving the overall performance and reliability of the chip packaging structure 1.
[0053] For further information, see Figure 3 The chip packaging structure 1 further includes a conductive ball 150 , which is located on a side of the first interconnect unit 100 away from the glass core board unit 110 , and is connected to a wire in the first interconnect unit 100 .
[0054] In this embodiment, the conductive ball 150 is used as an electrical connection point to realize signal and power transmission between the chip 1301 and the external circuit. This connection method has low resistance, high reliability and good durability, ensuring efficient and stable communication between the chip 1301 and the external device.
[0055] Based on the same concept, the present application also provides a method for preparing a chip packaging structure, see Figure 4 and Figure 5 , Figure 4 A step diagram of a method for preparing a chip packaging structure provided in this embodiment, Figure 5 for Figure 4 Corresponding process flow chart, the method comprises the following steps:
[0056] Step S110, providing a wafer to be cut, wherein the wafer to be cut comprises a first interconnection layer 10, a glass core board 11, a second interconnection layer 12, a chip layer 13 and a packaging layer 14 which are stacked in sequence, the chip layer 13 comprises a plurality of chip units 130, a gap channel exists between two adjacent chip units 130, each chip unit 130 comprises at least one chip 1301, and a pin side 13010 of the chip 1301 is arranged toward the second interconnection layer 12 and is electrically connected to the second interconnection layer 12;
[0057] In this embodiment, the wafer is the basic material in semiconductor manufacturing, including a first interconnect layer 10, a glass core board 11, a second interconnect layer 12, a chip layer 13 and a packaging layer 14 that are stacked. The first interconnect layer 10 is similar to the second interconnect layer 12, and usually contains metal wires and insulating materials for achieving electrical connections inside the wafer or between other components. The glass core board 11 provides excellent electrical insulation performance and thermal stability, and at the same time serves as a structural support to ensure the robustness of the entire chip packaging structure 1. The chip layer 13 is the core of the entire wafer and includes a plurality of chip units 130, which are separated by gap channels to facilitate subsequent cutting and packaging processes.
[0058] Step S120 , performing a first cutting on the first interconnect layer 10 along the gap channels between adjacent chip units 130 , and dividing the first interconnect layer 10 into a plurality of first interconnect units 100 through the formed first cutting channels.
[0059] Step S130 , cutting the glass core board 11 for a second time along the first cutting channel, and dividing the glass core board 11 into a plurality of glass core board units 110 through the formed second cutting channel.
[0060] Step S140 , filling glue in the channels formed by cutting, and cutting the packaging glue, the second interconnection layer 12 and the packaging layer 14 along the gap channels between adjacent chip units 130 to obtain a chip packaging structure 1 .
[0061] In this embodiment, the channel formed by cutting is filled with packaging glue, the material of the glue includes resin, and after the glue is cured, the packaging glue, the second interconnection layer 12 and the packaging layer 14 are cut along the gap channel between adjacent chip units 130 to finally obtain a separate chip packaging structure 1.
[0062] Further, the width of the first cutting channel formed by the first cutting is greater than the width of the second cutting channel formed by the second cutting.
[0063] In this embodiment, the widths of the two cuts of the wafer are reduced successively to realize the design of a step structure. The step structure design can provide additional support to enhance the overall strength and stability of the chip packaging structure 1. At the same time, the step structure design can provide more contact area for the packaging unit 140, thereby improving the overall performance and reliability of the chip packaging structure 1.
[0064] Based on the same inventive concept, another object of the present application is to provide an electronic device, the electronic device comprising a plurality of chip packaging structures 1 provided in the present application or a chip packaging structure 1 prepared by a plurality of chip packaging structure preparation methods provided in the present application. The chip packaging structure 1 implements the encapsulation of the glass core board unit 110, improves the reliability of the chip packaging structure 1, protects the chip 1301 from physical and chemical damage, and thus improves the stability of electrical connection and data transmission in the electronic device.
[0065] In summary, the present application provides a chip packaging structure, a preparation method and an electronic device. The chip packaging structure includes a first interconnection unit, a glass core board unit, a second interconnection unit and a chip unit which are stacked in sequence. The wires in the first interconnection unit and the wires in the second interconnection unit are connected through the glass core board unit, and the chip unit includes at least one chip, and the pin side of the chip is arranged toward the second interconnection unit and is electrically connected to the second interconnection unit. The chip packaging structure also includes a packaging unit, which is located at least around the chip. The packaging unit is also located on the side wall of the glass core board unit and the side wall of the first interconnection unit, and the peripheral side of the second interconnection unit is exposed relative to the packaging unit. In this way, through the above structure, the effective packaging of the glass core board unit is achieved, thereby enhancing the stability of the chip packaging structure.
[0066] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A chip packaging structure, characterized in that: The chip packaging structure comprises a first interconnection unit, a glass core board unit, a second interconnection unit and a chip unit which are stacked in sequence, wherein the wires in the first interconnection unit and the wires in the second interconnection unit are connected through the glass core board unit, and the chip unit comprises at least one chip, and the pin side of the chip is arranged toward the second interconnection unit and is electrically connected to the second interconnection unit; The chip packaging structure also includes a packaging unit, which is located at least around the chip. The packaging unit is also located on the side walls of the glass core board unit and the side walls of the first interconnection unit, and the peripheral side of the second interconnection unit is exposed relative to the packaging unit.
2. The chip packaging structure according to claim 1, characterized in that: The packaging unit includes a first packaging unit and a second packaging unit; The first packaging unit wraps around the chip, the second packaging unit covers the side walls of the first interconnection unit and the side walls of the glass core board unit, the first packaging unit and the second packaging unit are not connected, wherein the first packaging unit and the second packaging unit are separated by the second interconnection unit, and the materials of the first packaging unit and the second packaging unit are different.
3. The chip packaging structure according to claim 2, characterized in that: At the side wall position of the second interconnection unit, the first encapsulation unit, the second encapsulation unit and the side wall of the second interconnection unit form a flat plane.
4. The chip packaging structure according to claim 2, characterized in that: The orthographic projection of the first packaging unit on the second interconnection unit is at least partially located outside the orthographic projection of the chip unit on the second interconnection unit; The orthographic projection of the second packaging unit on the second interconnection unit does not overlap with the orthographic projection of the first interconnection unit on the second interconnection unit, and the orthographic projection of the second packaging unit on the second interconnection unit overlaps with the orthographic projection of the glass core board unit on the second interconnection unit.
5. The chip packaging structure according to claim 2, characterized in that: The thickness of the second packaging unit at the side wall of the first interconnected unit is a first thickness, and the thickness of the second packaging unit at the side wall of the glass core board unit is a second thickness. The first thickness is greater than the second thickness, and the first thickness is 5 to 50 microns more than the second thickness.
6. The chip packaging structure according to claim 1, characterized in that: The side wall of the first interconnected unit, the side wall of the glass core plate unit and the side wall of the second interconnected unit form a step structure; The side wall of the second interconnected unit extends relative to the side wall of the glass core plate unit to form a first step structure, and the side wall of the glass core plate unit extends relative to the side wall of the first interconnected unit to form a second step structure.
7. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a conductive ball, which is located on a side of the first interconnection unit away from the glass core board unit, and is connected to a wire in the first interconnection unit.
8. A method for preparing a chip packaging structure, characterized in that: The method comprises: A wafer to be cut is provided, wherein the wafer to be cut comprises a first interconnection layer, a glass core board, a second interconnection layer, a chip layer and a packaging layer which are stacked in sequence, the chip layer comprises a plurality of chip units, a gap channel exists between two adjacent chip units, each of the chip units comprises at least one chip, and a pin side of the chip is arranged toward the second interconnection layer and is electrically connected to the second interconnection layer; Performing a first cutting on the first interconnect layer along the gap channels between adjacent chip units, and dividing the first interconnect layer into a plurality of first interconnect units through the formed first cutting channels; Performing a second cutting on the glass core board along the first cutting channel, dividing the glass core board into a plurality of glass core board units through the formed second cutting channel; Glue is filled in the channel formed by cutting, and the packaging glue, the second interconnection layer and the packaging layer are cut along the gap channel between adjacent chip units to obtain a chip packaging structure.
9. The method for preparing a chip packaging structure according to claim 8, characterized in that: The width of the first cutting channel formed by the first cutting is greater than the width of the second cutting channel formed by the second cutting.
10. An electronic device, characterized in that: The electronic device comprises the chip packaging structure described in any one of claims 1 to 7 or a chip packaging structure prepared by the method for preparing the chip packaging structure described in any one of claims 8 to 9.