Adjustable wide-adaptation MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) opening gate driving circuit and driving method

Abstract

The invention discloses an adjustable wide-adaptation MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) opening gate driving circuit and a driving method, and relates to the field of power According to the circuit, drain-source side information of the power MOSFET to be controlled is not introduced in design, and drain-source voltage and current track regulation and control in the opening process of the power MOSFET to be controlled are realized only by finely controlling grid voltage of the power MOSFET to be controlled. According to the circuit, parasitic parameters of the to-be-controlled power MOSFET are matched through parameter configuration so as to improve the applicability, and in the opening process of the to-be-controlled power MOSFET, the voltage rising slope of the grid voltage in the stage of being higher than the threshold voltage is regulated and controlled, so that drain-source voltage and current track regulation and control are achieved, and the reliability of the power MOSFET is improved. The electromagnetic noise generated by the drain-source current in the reverse recovery stage in the switching-on process is regulated and controlled according to the requirements of the power electronic device; the problems that an existing power MOSFET drive circuit is difficult to finely and continuously regulate and control grid voltage in the turn-on process, drain-source voltage and current cannot meet low electromagnetic interference and low loss at the same time in the turn-on process, and the requirement for high power density of a power electronic device is difficult to meet are solved.

Description

Technical Field

[0001] The invention relates to the field of power electronics, and in particular to an adjustable wide-adaptability MOSFET turn-on gate drive circuit and a drive method. Background Art

[0002] During the turn-on process of a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the gate driver is required to convert the turn-on digital signal into an analog turn-on signal suitable for the power MOSFET, and apply it to the gate of the power MOSFET to complete the turn-on action. During the turn-on process of the power MOSFET, the electromagnetic interference caused by the increase of the drain-source current and the turn-on loss are contradictory, and the drain-source voltage and current trajectory needs to be changed by adjusting the gate signal trajectory to meet the needs of power electronic devices.

[0003] At present, the existing drive circuit can only adjust the power side voltage and current trajectory of the power MOSFET device during the turn-on process by adjusting the gate resistance. It is unable to simultaneously meet the requirements of low electromagnetic interference and low loss during the turn-on process, and it is difficult to meet the high power density requirements of power electronic devices. Summary of the invention

[0004] The present invention is to solve the problem that the existing power MOSFET drive circuit cannot simultaneously meet the requirements of low electromagnetic interference and low loss during the turn-on process, and is difficult to meet the high power density requirements of power electronic devices, and provides an adjustable wide-adaptability MOSFET turn-on gate drive circuit and a drive method. The present invention starts from the perspective of the power MOSFET turn-on process mechanism, provides an adjustable wide-adaptability MOSFET turn-on gate drive circuit and a drive method, performs trajectory planning for the gate-source voltage trajectory of the power MOSFET turn-on process, and finely controls the drain-source side voltage and current trajectory of the turn-on process, so as to achieve the purpose of low electromagnetic interference and low turn-on loss of the power MOSFET during the turn-on process.

[0005] At the same time, the adjustable wide-adaptability MOSFET turn-on gate drive circuit and drive method proposed in the present invention can adjust parameters according to the parasitic parameters of the power MOSFET to adapt to power MOSFETs with different parasitic parameters.

[0006] In addition, the adjustable wide-adaptability MOSFET turn-on gate drive circuit and drive method proposed in the present invention only realizes the regulation of the voltage and current trajectory on the drain-source side by controlling the gate of the power MOSFET, without introducing high-voltage information on the drain-source side, reducing insulation requirements and improving power density.

[0007] The technical solution adopted by the present invention is:

[0008] A controllable wide-adaptability MOSFET turn-on gate drive circuit, the circuit is applicable to a power electronic device using a power MOSFET transistor, the power electronic device comprises an electric energy converter and an inverter, the circuit is used to drive a power MOSFET to be controlled (08), the controllable wide-adaptability MOSFET turn-on gate drive circuit comprises:

[0009] A first pre-charging module (01) comprises a first PMOS tube (MP1) and a second PMOS tube (MP2), wherein gate inputs thereof are respectively connected to a first turn-on enable signal (Vctrl1) and a second turn-on enable signal (Vctrl2), a source of the first PMOS tube (MP1) is connected to a power supply VDD, a drain of the second PMOS tube (MP2) is connected to a node net1, and a drain of the first PMOS tube (MP1) is connected to a source of the second PMOS tube (MP2);

[0010] A second pre-charging module (02) comprises a third PMOS tube (MP3) and a fourth PMOS tube (MP4), wherein gate inputs thereof are respectively connected to a third turn-on enable signal (Vctrl3) and a second turn-on enable signal (Vctrl2), a source of the third PMOS tube (MP3) is connected to a power supply VDD, and a drain is connected to a node net4; a source of the fourth PMOS tube (MP4) is connected to the node net4, and a drain is connected to a ground (GND);

[0011] A first charging module (04) comprises a first NMOS tube (MN1), a first resistor (R1), a second resistor (R2), a third resistor (R3), and a diode (D1); a gate input of the first NMOS tube (MN1) is connected to a fourth enable signal (Vctrl4); a drain of the first NMOS tube (MN1) is connected to a node net1 via the first resistor (R1); a source of the first NMOS tube (MN1) is connected to a node net6 and is connected to a node net3 via the third resistor (R3); a cathode of the diode (D1) is connected to a node net3; an anode of the diode (D1) is connected to a node net2 and is connected to a node net1 via the second resistor (R2);

[0012] The second charging module (05) comprises a fifth PMOS tube (MP5), a second NMOS tube (MN2) and a fourth resistor (R4); the source of the fifth PMOS tube (MP5) is connected to a power supply VDD, the gate of the fifth PMOS tube is connected to a node net4, and the drain of the fifth PMOS tube is connected to the drain of the second NMOS tube (MN2); the gate of the second NMOS tube (MN2) is connected to a node net2, and the source of the second NMOS tube (MN2) is connected to an output terminal Vgate via a fourth resistor (R4);

[0013] The bias module (03) comprises a third NMOS transistor (MN3) and a fifth resistor (R5), wherein the drain of the third NMOS transistor (MN3) is connected to the node net5 and connected to the node net3 via the fifth resistor (R5); the gate of the third NMOS transistor (MN3) is connected to the input bias signal Vbias; and the source of the third NMOS transistor (MN3) is connected to the ground (GND);

[0014] A third charging module (06), comprising a fourth NMOS tube (MN4), wherein the drain of the fourth NMOS tube (MN4) is connected to the power supply VDD, the gate is connected to the node net5, and the source is connected to the output terminal Vgate;

[0015] A parameter configuration module (07), comprising an adjustable sixth resistor (R6) and an adjustable first capacitor (C1), the sixth resistor (R6) and the third resistor (R3) in the first charging module (04) being connected to a node net6, and the sixth resistor (R6) being connected to a ground (GND) via the first capacitor (C1);

[0016] The external gate resistor (09) is used to connect the gate of the external power MOSFET (08) to be controlled.

[0017] Furthermore, the first pre-charging module (01) and the first charging module (04) are connected to a node net1; the second pre-charging module (02) and the second charging module (05) are connected to a node net4;

[0018] The input of the first pre-charging module (01) is a first enable signal (Vctrl1) and a second enable signal (Vctrl2);

[0019] The input of the second pre-charging module (02) is a second enable signal (Vctrl2) and a third enable signal (Vctrl3);

[0020] The input of the first charging module (04) is a fourth enable signal (Vctrl4), the first charging module (04) is connected to the first pre-charging module (01) at a node net1, connected to the second charging module (05) at a node net2 and a node net3, connected to the bias module (03) at a node net3, and connected to the output end of the parameter configuration module (03);

[0021] The second energy charging module (05) is connected to the second pre-charging module (02) at a node net4, is connected to the first energy charging module (04) at a node net2 and a node net3, and is connected to the third energy charging module (06) at an output terminal (Vgate);

[0022] The bias module (03) is connected to the first charging module (04) at a node net3, and is connected to the third charging module (06) at a node net5, and the input of the bias module (03) is a bias signal Vbias;

[0023] The third energy charging module (06) is connected to the bias module (03) at a node net5, and is connected to the external gate resistor (09) via an output terminal (Vgate) of the second energy charging module (05);

[0024] The output end of the parameter configuration module (07) is connected to the first charging module (04) at a node net6.

[0025] Based on a driving method for turning on a gate drive circuit of a MOSFET with adjustable wide adaptability, the method is:

[0026] The first pre-charging module (01) is used to increase the potentials of the node net1, the node net2 and the node net3 in the pre-opening stage according to the first opening enable signal (Vctrl1) and the second opening enable signal (Vctrl2);

[0027] The second pre-charging module (02) is used to increase the potential of the node net4 in the pre-opening stage according to the third opening enable signal (Vctrl3) and in combination with the state of the first pre-charging module (01);

[0028] The bias module (03) is used to establish a net5 node voltage affected by the parameter configuration module (07) according to the bias signal Vbias and in combination with the voltage information of the nodes net1, net2 and net3;

[0029] The first charging module (04) is used to change the voltages of the nodes net1, net2, net3 and net6 during the opening process according to the fourth opening enable signal (Vctrl4) and the internal parameters of the parameter configuration module (07);

[0030] The second charging module (05) is used to provide a charging current to the output terminal Vgate during the opening process according to the voltages of the nodes net2, net3 and net4;

[0031] The third charging module (06) is used to change the voltage of the output terminal Vgate during the opening process according to the voltage of the node net5, and provide a charging current to the gate of the power MOSFET (08) to be controlled;

[0032] The parameter configuration module (07) is used to adjust the voltage variation trend of the node net5 and the node net6 during the opening process, and finally influence the gate voltage trajectory of the controlled power MOSFET (08) through the output terminal Vgate during the opening process.

[0033] Furthermore, the values ​​of the sixth resistor (R6) and the first capacitor (C1) in the parameter configuration module (07) are configured according to the parasitic parameters of the power MOSFET (08) to be controlled; and the specific expression method of the voltage waveform of the node net6 in the first charging module (04) is:

[0034] During the turn-on process of the power MOSFET (08) to be controlled, when the gate voltage of the power MOSFET (08) to be controlled is lower than the threshold voltage (Vth), the voltage of the node net6 rises rapidly and linearly;

[0035] During the turn-on process of the power MOSFET (08) to be controlled, when the gate voltage of the power MOSFET (08) to be controlled is higher than the threshold voltage (Vth), the voltage of the node net6 rises linearly and controllably.

[0036] Furthermore, during the turning-on process of the controlled power MOSFET (08), the gate voltage waveform generated by the voltage of the node net6 being affected by the resistance and capacitance values ​​of the sixth resistor (R6) and the first capacitor (C1) in the parameter configuration module (07) is specifically expressed as follows:

[0037] When the capacitance value of the first capacitor (C1) remains unchanged, the greater the resistance value of the sixth resistor (R6), the higher the starting voltage of the linearly controllable rising phase of the gate voltage of the controlled power MOSFET (08) connected to the output terminal (Vgate) via the external gate resistor (09);

[0038] When the resistance value of the sixth resistor (R6) remains unchanged, the larger the capacitance value of the first capacitor (C1), the smaller the slope of the gate voltage of the power MOSFET (08) to be controlled connected via the output terminal (Vgate) via the external gate resistor (09) in the stage where the gate voltage is higher than the threshold voltage (Vth), and vice versa.

[0039] Furthermore, during the turn-on process of the power MOSFET to be controlled (08), the gate voltage waveform of the power MOSFET to be controlled (08) follows the voltage waveform of the node net6 in the first charging module (04), and its specific expression method is: when the gate voltage of the power MOSFET to be controlled (08) is greater than the threshold voltage (Vth), the rising slope of the gate voltage of the power MOSFET to be controlled (08) is the same as the rising slope of the node net6 voltage.

[0040] Furthermore, the gate voltage waveform of the power MOSFET (08) to be controlled during the turn-on process is specifically expressed as follows:

[0041] When the gate voltage of the power MOSFET (08) to be controlled is lower than the threshold voltage (Vth), the gate voltage of the power MOSFET (08) to be controlled quickly reaches the threshold voltage (Vth);

[0042] When the gate voltage of the power MOSFET (08) to be controlled is greater than the threshold voltage (Vth) but less than the Miller platform (Vmiller), the gate voltage of the power MOSFET (08) to be controlled rises linearly and controllably;

[0043] When the gate voltage of the power MOSFET (08) to be controlled is at the Miller platform (Vmiller), the gate voltage of the power MOSFET (08) to be controlled is maintained at the Miller platform (Vmiller) voltage;

[0044] When the gate voltage of the power MOSFET (08) to be controlled is greater than the Miller platform (Vmiller), the gate voltage of the power MOSFET (08) to be controlled resumes a linear and controllable rise.

[0045] Furthermore, during the turning-on process of the power MOSFET to be controlled (08), the specific expression method of the drain-source current and drain-source voltage waveforms of the power MOSFET to be controlled (08) is as follows:

[0046] When the resistance value of the sixth resistor (R6) remains unchanged, the larger the capacitance value of the first capacitor (C1), the smaller the slope of the drain-source current of the power MOSFET (08) to be controlled, and the smaller the absolute value of the slope of the drain-source voltage;

[0047] When the capacitance value of the first capacitor (C1) remains unchanged, the larger the resistance value of the sixth resistor (R6), the smaller the slope of the drain-source current of the controlled power MOSFET (08), and the smaller the absolute value of the slope of the drain-source voltage.

[0048] Furthermore, during the turning-on process of the power MOSFET (08) to be controlled, the driving circuit does not need to introduce information on the drain-source side of the power MOSFET (08) to be controlled, but only utilizes the change characteristics of the transconductance capacitance of the power MOSFET (08) to control the gate of the power MOSFET (08) to be controlled, thereby finally completing the control of the drain-source voltage and current trajectory of the power MOSFET (08) to be controlled.

[0049] Beneficial effects:

[0050] Compared with the prior art, the present invention has the following advantages:

[0051] 1. During the turn-on process of the power MOSFET to be controlled, the drain-source voltage and current trajectory of the power MOSFET to be controlled are finely regulated, so that the power MOSFET has the characteristics of low electromagnetic interference and low turn-on loss during the turn-on process;

[0052] 2. Matching the parasitic parameters of the power MOSFET to be controlled through the parameter configuration module to improve the universality of the opening drive circuit;

[0053] 3. Avoid the introduction of high voltage information on the drain-source side of the power MOSFET to be controlled, reduce insulation requirements, and improve power density. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic diagram of the structure of the gate drive circuit for the adjustable wide adaptability MOSFET;

[0055] Figure 2 A circuit diagram for opening a gate drive circuit for an adjustable wide adaptability MOSFET;

[0056] Figure 3 The voltage waveform of node net6 of the gate drive circuit for the adjustable wide adaptability MOSFET;

[0057] Figure 4 A voltage waveform diagram of a node net6 of a gate drive circuit for an adjustable wide adaptability MOSFET that is affected by a sixth resistor in a parameter configuration module;

[0058] Figure 5 A voltage waveform diagram of a node net6 of a gate drive circuit for an adjustable wide-adaptability MOSFET that is affected by the first capacitor in a parameter configuration module;

[0059] Figure 6 The waveform diagram of the node net6 of the gate drive circuit for the adjustable wide adaptability MOSFET and the voltage applied to the gate of the power MOSFET to be controlled;

[0060] Figure 7 The gate voltage waveform diagram of the power MOSFET to be controlled when the gate drive circuit of the adjustable wide adaptability MOSFET is turned on (including the gate voltage waveform of the power MOSFET to be controlled at the node net6 and the turn-on process);

[0061] Figure 8 The waveform diagram of drain-source voltage and drain-source current of the power MOSFET to be controlled affected by the first capacitor in the parameter configuration module;

[0062] Fig. 9 The waveform diagram of the drain-source voltage and drain-source current of the power MOSFET to be controlled affected by the sixth resistor in the parameter configuration module. DETAILED DESCRIPTION

[0063] Specific implementation method 1: refer to Figures 1 to 9 Specifically describe this embodiment, a controllable wide adaptability MOSFET turn-on gate drive circuit and driving method described in this embodiment, such as Figure 1 , 2 As shown, it is suitable for a power electronic device using a power MOSFET, and the power electronic device includes an electric energy converter and an inverter.

[0064] The method comprises a first pre-charging module, a second pre-charging module, a first charging module, a second charging module, a bias module, a third charging module, a parameter configuration module, an external power MOSFET to be controlled and an external gate resistor, Figure 2 As shown, where:

[0065] The first pre-charge module includes a first PMOS transistor MP1 and a second PMOS transistor MP2, whose gate inputs are respectively connected to a first turn-on enable signal Vctrl1 and a second turn-on enable signal Vctrl2, a source of the first PMOS transistor MP1 is connected to a power supply VDD, and a drain of the second PMOS transistor MP2 is connected to a node net1;

[0066] The second pre-charge module includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4, whose gate inputs are respectively connected to the third turn-on enable signal Vctrl3 and the second turn-on enable signal Vctrl2, the source of the third PMOS transistor MP3 is connected to the power supply VDD, and the drain is connected to the node net4; the source of the fourth PMOS transistor MP4 is connected to the node net4, and the drain is connected to the ground GND;

[0067] The first charging module comprises a first NMOS transistor MN1, a first resistor R1, a second resistor R2, a third resistor R3, and a diode D1; the gate input of the first NMOS transistor (MN1) is connected to a fourth enable signal (Vctrl4), the drain of the first NMOS transistor MN1 is connected to a node net1 through the first resistor R1, the source of the first NMOS transistor is connected to a node net6, and is connected to a node net3 through the third resistor R3; the cathode of the diode (D1) is connected to the node net3, the anode of the diode is connected to the node net2, and is connected to the node net1 through the second resistor (R2);

[0068] The second charging module includes a fifth PMOS tube MP5, a second NMOS tube MN2 and a fourth resistor R4; the source of the fifth PMOS tube MP5 is connected to the power supply VDD, the gate of the fifth PMOS tube is connected to the node net4, and the drain of the fifth PMOS tube is connected to the drain of the second NMOS tube MN2; the drain of the second NMOS tube is connected to the drain of the fifth PMOS tube, the gate of the second NMOS tube is connected to the node net2, and the source of the second NMOS tube is connected to the output terminal Vgate through the fourth resistor R4;

[0069] The bias module includes a third NMOS tube MN3 and a fifth resistor R5, the drain of the third NMOS tube is connected to the node net5, and is connected to the node net3 through the fifth resistor R5; the gate of the third NMOS tube is connected to the input bias signal Vbias; the source of the third NMOS tube is connected to the ground GND;

[0070] The third charging module includes a fourth NMOS tube MN4, the drain of the fourth NMOS tube is connected to the power supply VDD, the gate is connected to the node net5, and the source is connected to the output terminal Vgate;

[0071] The parameter configuration module includes an adjustable sixth resistor R6 and an adjustable first capacitor C1, the sixth resistor R6 and the third resistor R3 in the first charging module O4 are connected to a node net6, and the sixth resistor is connected to the ground GND through the first capacitor C1;

[0072] The first pre-charging module and the second pre-charging module are respectively connected to the first charging module and the second charging module at nodes net1, net2 and net3; the input of the first pre-charging module is the first enable signal Vctrl1 and the second enable signal Vctrl2; the input of the second pre-charging module is the second enable signal Vctrl2 and the third enable signal Vctrl3; the input of the first charging module is the fourth enable signal Vctrl4, which is connected to the first pre-charging module at node net1, connected to the second charging module at nodes net2 and net3, connected to the bias module at node net3, and connected to the output end of the parameter configuration module; The second charging module is connected to the second pre-charging module at node net4, connected to the first charging module at nodes net2 and net3, and connected to the third charging module at the output end Vgate; the bias module is connected to the first charging module at node net3, and connected to the third charging module at node net5, and the input of the bias module is the bias signal Vbias; the third charging module is connected to the bias module at node net5, and is connected to the external gate resistor through the output end Vgate of the second charging module; the output end of the parameter configuration module is connected to the first charging module at node net6; the external power MOSFET to be controlled is connected to the output end Vgate through the external gate resistor.

[0073] Specific implementation method 2: During the process of turning on the power MOSFET to be controlled, the functions of the above modules are specifically manifested as follows:

[0074] The first pre-charging module is used to increase the potentials of the nodes net1, net2 and net3 in the pre-opening stage according to the first opening enable signal Vctrl1 and the second opening enable signal Vctrl2;

[0075] The second pre-charging module is used to increase the potential of the node net4 in the pre-opening stage according to the third opening enable signal Vctrl3 and in combination with the state of the first pre-charging module;

[0076] The bias module is used to establish the net5 node voltage affected by the parameter configuration module according to the bias signal Vbias and in combination with the voltage information of the nodes net1, net2 and net3;

[0077] The first charging module is used to change the voltages of nodes net1, net2 and net3 during the turning-on process of the power MOSFET to be controlled according to the fourth turning-on enable signal Vctrl4 and the configuration parameters of the parameter configuration module;

[0078] The second charging module is used to provide a charging current to the output terminal Vgate according to the voltages of the nodes net2, net3 and net4 during the turning-on process of the power MOSFET to be controlled;

[0079] The third charging module is used to change the voltage of the output terminal Vgate according to the voltage of the node net5 during the turning-on process of the power MOSFET to be controlled, and provide a charging current to the gate of the power MOSFET to be controlled;

[0080] The parameter configuration module is used to adjust the voltage change trajectory of the node net5 and the node net6 during the opening process of the power MOSFET to be controlled, and finally affects the gate voltage trajectory of the power MOSFET to be controlled during the opening process.

[0081] For the adjustable wide adaptability MOSFET gate drive circuit, the working principle between the modules is as follows:

[0082] During the turning-on process of the power MOSFET to be controlled, the first turn-on enable signal Vctrl1 and the second turn-on enable signal Vctrl2 in the first pre-charging module are pulled low, so that the first PMOS tube MP1 and the second PMOS tube MP2 establish a channel, and the potential of the node net1 is pulled up;

[0083] The second pre-charge module pulls down the second opening enable signal Vctrl2 and the third opening enable signal Vctrl3, so that the third PMOS transistor MP3 and the fourth PMOS transistor MP4 establish a channel, and pull up the potential of the node net4;

[0084] The first charging module is affected by the fourth enable signal Vctrl4, and drives the first NMOS transistor MN1 to establish a channel, so that the node net1 establishes a first current path to the parameter configuration module through the first resistor R1 and the first NMOS transistor MN1, and raises the potential of the node net6. The potential increase of the node net6 is affected by the sixth resistor R6 and the first capacitor C1 in the parameter configuration module, and is also affected by the parasitic capacitance of the power MOSFET to be controlled;

[0085] At the same time, the node net1 establishes a second current path to the node net3 through the first resistor R1, the first NMOS transistor MN1, and the third resistor R3, raising the potential of the node net3, and the potential raising of the node net3 is affected by the sixth resistor R6 and the first capacitor C1 in the parameter configuration module, and is also affected by the parasitic capacitance of the power MOSFET to be controlled;

[0086] At the same time, the node net1 establishes a third current path to the node net3 through the second resistor R2 and the diode D1, raising the potential of the node net3, and the potential raising of the node net3 is affected by the sixth resistor R6 and the first capacitor C1 in the parameter configuration module, and is also affected by the parasitic capacitance of the power MOSFET to be controlled;

[0087] The bias voltage Vbias in the bias module maintains a constant voltage value, so that the third NMOS transistor MN3 is always in a conducting state. Therefore, affected by the node net3 in the first energy charging module, the bias module quickly raises the potential of the node net5 through the node net3 via the fifth resistor R5, so that the fourth NMOS transistor MN4 in the third energy charging module can quickly establish a channel and obtain a current-carrying capacity;

[0088] The fifth PMOS transistor MP5 in the second charging module is affected by the potential of the node net4 in the second pre-charging module to establish a channel, and the second NMOS transistor is affected by the fourth turn-on enable signal Vctrl4 to establish a channel, so that the second charging module establishes a fourth current path to the output terminal Vgate through the fifth PMOS transistor MP5, the second NMOS transistor MN2, and the fourth resistor R4; further, the flow capacity of the fourth current path is affected by the potential of the node net4 in the second pre-charging module and the node net2 in the first charging module;

[0089] The fourth NMOS tube MN4 in the third charging module is affected by the potential of the final node net5 of the bias module to establish a channel, establish a fifth current path to the output terminal Vgate, and its current carrying capacity is affected by the potential of the node net5. Specific implementation method three:

[0091] The values ​​of the sixth resistor R6 and the first capacitor C1 in the parameter configuration module can be configured according to the parasitic parameters of the power MOSFET to be controlled. During the opening process of the power MOSFET to be controlled, the voltage waveform of the node net6 is as follows: during the opening process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled is lower than the threshold voltage, the voltage of the node net6 rises rapidly and linearly; during the opening process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled is higher than the threshold voltage, the voltage of the node net6 rises linearly and controllably, such as Figure 3 shown.

[0092] The resistance value of the sixth resistor R6 and the capacitance value of the first capacitor C1 in the parameter configuration module regulate the voltage of the node net6 during the turn-on process of the power MOSFET to be controlled, and affect the voltage waveform of the node net6, which is specifically manifested as follows:

[0093] When the capacitance value of the first capacitor C1 remains unchanged, the larger the resistance value of the sixth resistor R6 is, the higher the starting voltage of the linear controllable rising phase of the node net6 voltage will be when the gate voltage of the power MOSFET to be controlled is higher than the threshold voltage. Figure 4 As shown; when the resistance value of the sixth resistor R6 remains unchanged, the larger the capacitance value of the first capacitor C1, when the gate voltage of the power MOSFET to be controlled is higher than the threshold voltage Vth, the smaller the voltage slope of the node net6 voltage in the linear controllable rising stage, such as Figure 5 As shown;

[0094] The adjustable wide-adaptability MOSFET gate drive circuit is applied to the gate voltage trajectory of the power MOSFET to be controlled, which follows the node net6 voltage trajectory. When the gate voltage of the power MOSFET to be controlled is higher than the threshold voltage (Vth), its voltage rising slope is the same as the node net6 voltage rising slope, such as Figure 6 As shown;

[0095] like Figure 7 As shown, the voltage waveform of the adjustable wide-adaptability MOSFET turn-on gate drive circuit applied to the gate of the power MOSFET to be controlled during the turn-on process of the power MOSFET to be controlled is:

[0096] When the gate voltage of the power MOSFET to be controlled is lower than the threshold voltage Vth, the gate voltage of the power MOSFET to be controlled quickly reaches the threshold voltage;

[0097] When the gate voltage of the power MOSFET to be controlled is greater than the threshold voltage Vth but less than the Miller platform Vmiller, the gate voltage of the power MOSFET to be controlled rises linearly and controllably;

[0098] When the gate voltage of the power MOSFET to be controlled is at the Miller platform Vmiller, the gate voltage of the power MOSFET to be controlled is maintained at the Miller platform (Vmiller) voltage;

[0099] When the gate voltage of the power MOSFET (08) to be controlled is greater than the Miller platform (Vmiller), the gate voltage of the power MOSFET (08) to be controlled resumes a linear and controllable rise.

[0100] In the process of turning on the power MOSFET to be controlled, the drain-source current and drain-source voltage waveforms of the power MOSFET to be controlled are affected by the parameter configuration module, which is specifically manifested as follows:

[0101] When the resistance value of the sixth resistor (R6) remains unchanged, the larger the capacitance value of the first capacitor (C1), the smaller the slope of the drain-source current of the power MOSFET to be controlled, and the smaller the absolute value of the slope of the drain-source voltage. Figure 8 As shown;

[0102] When the capacitance value of the first capacitor (C1) remains unchanged, the larger the resistance value of the sixth resistor (R6), the smaller the slope of the drain-source current of the power MOSFET to be controlled, and the smaller the absolute value of the slope of the drain-source voltage. Fig. 9 As shown; Specific implementation method four:

[0104] The present invention provides a controllable wide-adaptability MOSFET turn-on gate drive circuit and a drive method from the perspective of the power MOSFET turn-on process mechanism. The controllable wide-adaptability MOSFET turn-on gate drive circuit and the drive method adjust the voltage change trajectory of the node net6 through the voltage characteristics of the RC circuit composed of the sixth resistor R6 and the first capacitor C1 in the parameter configuration module during the charging process, such as Figure 3 , 4 , 5; further, by turning on the gate drive circuit and driving method of the adjustable wide-adaptable MOSFET, the gate voltage trajectory of the power MOSFET to be controlled follows the voltage trajectory of the node net6, and the gate voltage trajectory of the power MOSFET to be controlled is planned by planning the voltage trajectory of the node net6, such as Figure 6 As shown; the gate voltage of the controlled power MOSFET during the turn-on process is controlled by the adjustable wide-adaptive MOSFET turn-on gate drive circuit and the drive method to realize the planned voltage trajectory, such as Figure 7 As shown; thus, the adjustable wide adaptability MOSFET turn-on gate drive circuit and driving method realize the drain-source voltage and current trajectory control through the gate voltage fine control, and realize the fine control of the drain-source current overshoot, drain-source current slope, and drain-source voltage slope of the controlled power MOSFET during the turn-on process, such as Figure 8, 9 shown.

[0105] At the same time, the adjustable wide-adaptability MOSFET turn-on gate drive circuit and drive method proposed in the present invention can adjust parameters according to the parasitic parameters of the power MOSFET through a parameter configuration module to adapt to power MOSFETs with different parasitic parameters.

[0106] In addition, the adjustable wide-adaptability MOSFET turn-on gate drive circuit and drive method proposed in the present invention do not introduce the drain-source side information of the controlled power MOSFET in design, and sense the stage of the controlled power MOSFET turn-on process through the gate-source side characteristics of the controlled power MOSFET, and based on this, realize the control of the drain-source side voltage and current trajectory of the controlled power MOSFET during the turn-on process through gate-source side control, reduce insulation requirements and circuit complexity, and improve power density. The drive circuit matches the parasitic parameters of the controlled power MOSFET through a parameter matching module, and during the turn-on process of the controlled power MOSFET, regulates the voltage rising slope of the gate voltage in the stage greater than the threshold voltage (Vth), thereby realizing the control of the drain-source side voltage and current trajectory, and then regulates the electromagnetic noise generated by the drain-source current overshoot during the turn-on process according to the requirements of the power electronic device, and seeks the best between the electromagnetic noise and the turn-on loss.

[0107] This circuit solves the problems that the existing power MOSFET drive circuit is difficult to finely and continuously control the gate voltage during the opening process, cannot meet the requirements of low electromagnetic interference and low loss at the same time during the opening process, and is difficult to meet the high power density requirements of power electronic devices. The circuit does not introduce the drain-source side information of the power MOSFET to be controlled in design. It only finely controls the gate voltage of the power MOSFET to be controlled, realizes the control of the drain-source side voltage and current trajectory of the power MOSFET to be controlled during the opening process, reduces insulation requirements and circuit complexity, and improves power density.

[0108] The present invention is described by several specific embodiments, and it should be understood by those skilled in the art that various changes and equivalent substitutions may be made to the present invention without departing from the scope of the present invention. In addition, various modifications may be made to the present invention for specific situations or specific circumstances without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed, but should include all implementation methods falling within the scope of the claims of the present invention.

Claims

1. A controllable wide-adaptability MOSFET turn-on gate drive circuit, the drive circuit is suitable for a power electronic device using a power MOSFET transistor, the power electronic device includes an electric energy converter and an inverter, the circuit is used to drive a power MOSFET to be controlled (08), characterized in that: The adjustable wide adaptability MOSFET turn-on gate drive circuit comprises: A first pre-charging module (01) comprises a first PMOS tube (MP1) and a second PMOS tube (MP2), wherein gate inputs thereof are respectively connected to a first turn-on enable signal (Vctrl1) and a second turn-on enable signal (Vctrl2), a source of the first PMOS tube (MP1) is connected to a power supply VDD, a drain of the second PMOS tube (MP2) is connected to a node net1, and a drain of the first PMOS tube (MP1) is connected to a source of the second PMOS tube (MP2); A second pre-charging module (02) comprises a third PMOS tube (MP3) and a fourth PMOS tube (MP4), wherein gate inputs thereof are respectively connected to a third turn-on enable signal (Vctrl3) and a second turn-on enable signal (Vctrl2), a source of the third PMOS tube (MP3) is connected to a power supply VDD, and a drain is connected to a node net4; a source of the fourth PMOS tube (MP4) is connected to the node net4, and a drain is connected to a ground (GND); A first charging module (04) comprises a first NMOS tube (MN1), a first resistor (R1), a second resistor (R2), a third resistor (R3), and a diode (D1); a gate input of the first NMOS tube (MN1) is connected to a fourth enable signal (Vctrl4); a drain of the first NMOS tube (MN1) is connected to a node net1 via the first resistor (R1); a source of the first NMOS tube (MN1) is connected to a node net6 and is connected to a node net3 via the third resistor (R3); a cathode of the diode (D1) is connected to a node net3; an anode of the diode (D1) is connected to a node net2 and is connected to a node net1 via the second resistor (R2); The second charging module (05) comprises a fifth PMOS tube (MP5), a second NMOS tube (MN2) and a fourth resistor (R4); the source of the fifth PMOS tube (MP5) is connected to a power supply VDD, the gate of the fifth PMOS tube is connected to a node net4, and the drain of the fifth PMOS tube is connected to the drain of the second NMOS tube (MN2); the gate of the second NMOS tube (MN2) is connected to a node net2, and the source of the second NMOS tube (MN2) is connected to an output terminal Vgate via a fourth resistor (R4); The bias module (03) comprises a third NMOS transistor (MN3) and a fifth resistor (R5), wherein the drain of the third NMOS transistor (MN3) is connected to the node net5 and connected to the node net3 via the fifth resistor (R5); the gate of the third NMOS transistor (MN3) is connected to the input bias signal Vbias; and the source of the third NMOS transistor (MN3) is connected to the ground (GND); A third charging module (06), comprising a fourth NMOS tube (MN4), wherein the drain of the fourth NMOS tube (MN4) is connected to the power supply VDD, the gate is connected to the node net5, and the source is connected to the output terminal Vgate; A parameter configuration module (07), comprising an adjustable sixth resistor (R6) and an adjustable first capacitor (C1), the sixth resistor (R6) and the third resistor (R3) in the first charging module (04) being connected to a node net6, and the sixth resistor (R6) being connected to a ground (GND) via the first capacitor (C1); The external gate resistor (09) is used to connect the gate of the external power MOSFET (08) to be controlled.

2. The adjustable wide adaptability MOSFET turn-on gate drive circuit according to claim 1, characterized in that: The first pre-charging module (01) and the first charging module (04) are connected to a node net1; the second pre-charging module (02) and the second charging module (05) are connected to a node net4; The input of the first pre-charging module (01) is a first enable signal (Vctrl1) and a second enable signal (Vctrl2); The input of the second pre-charging module (02) is a second enable signal (Vctrl2) and a third enable signal (Vctrl3); The input of the first charging module (04) is a fourth enable signal (Vctrl4), the first charging module (04) is connected to the first pre-charging module (01) at a node net1, connected to the second charging module (05) at a node net2 and a node net3, connected to the bias module (03) at a node net3, and connected to the output end of the parameter configuration module (03); The second energy charging module (05) is connected to the second pre-charging module (02) at a node net4, is connected to the first energy charging module (04) at a node net2 and a node net3, and is connected to the third energy charging module (06) at an output terminal (Vgate); The bias module (03) is connected to the first charging module (04) at a node net3, and is connected to the third charging module (06) at a node net5, and the input of the bias module (03) is a bias signal Vbias; The third energy charging module (06) is connected to the bias module (03) at a node net5, and is connected to the external gate resistor (09) via an output terminal (Vgate) of the second energy charging module (05); The output end of the parameter configuration module (07) is connected to the first charging module (04) at a node net6.

3. The driving method of a controllable wide-adaptability MOSFET turn-on gate driving circuit according to claim 2, characterized in that: The first pre-charging module (01) is used to increase the potentials of the node net1, the node net2 and the node net3 in the pre-opening stage according to the first opening enable signal (Vctrl1) and the second opening enable signal (Vctrl2); The second pre-charging module (02) is used to increase the potential of the node net4 in the pre-opening stage according to the third opening enable signal (Vctrl3) and in combination with the state of the first pre-charging module (01); The bias module (03) is used to establish a net5 node voltage affected by the parameter configuration module (07) according to the bias signal Vbias and in combination with the voltage information of the nodes net1, net2 and net3; The first charging module (04) is used to change the voltages of the nodes net1, net2, net3 and net6 during the opening process according to the fourth opening enable signal (Vctrl4) and the internal parameters of the parameter configuration module (07); The second charging module (05) is used to provide a charging current to the output terminal Vgate during the opening process according to the voltages of the nodes net2, net3 and net4; The third charging module (06) is used to change the voltage of the output terminal Vgate during the opening process according to the voltage of the node net5, and provide a charging current to the gate of the power MOSFET (08) to be controlled; The parameter configuration module (07) is used to adjust the voltage variation trend of the node net5 and the node net6 during the opening process, and finally influence the gate voltage trajectory of the controlled power MOSFET (08) through the output terminal Vgate during the opening process.

4. The driving method of a controllable wide adaptability MOSFET turn-on gate driving circuit according to claim 3, characterized in that: The values ​​of the sixth resistor (R6) and the first capacitor (C1) in the parameter configuration module (07) are configured according to the parasitic parameters of the power MOSFET (08) to be controlled; the specific expression method of the voltage waveform of the node net6 in the first charging module (04) is: During the turn-on process of the power MOSFET (08) to be controlled, when the gate voltage of the power MOSFET (08) to be controlled is lower than the threshold voltage (Vth), the voltage of the node net6 rises rapidly and linearly; During the turn-on process of the power MOSFET (08) to be controlled, when the gate voltage of the power MOSFET (08) to be controlled is higher than the threshold voltage (Vth), the voltage of the node net6 rises linearly and controllably.

5. The driving method of a controllable wide adaptability MOSFET turn-on gate driving circuit according to claim 3, characterized in that: During the turning-on process of the controlled power MOSFET (08), the gate voltage waveform generated by the voltage of the node net6 being affected by the resistance and capacitance values ​​of the sixth resistor (R6) and the first capacitor (C1) in the parameter configuration module (07) is specifically expressed as follows: When the capacitance value of the first capacitor (C1) remains unchanged, the greater the resistance value of the sixth resistor (R6), the higher the starting voltage of the linearly controllable rising phase of the gate voltage of the controlled power MOSFET (08) connected to the output terminal (Vgate) via the external gate resistor (09); When the resistance value of the sixth resistor (R6) remains unchanged, the larger the capacitance value of the first capacitor (C1), the smaller the slope of the gate voltage of the power MOSFET (08) to be controlled connected via the output terminal (Vgate) via the external gate resistor (09) in the stage where the gate voltage is higher than the threshold voltage (Vth), and vice versa.

6. The driving method of a controllable wide adaptability MOSFET turn-on gate driving circuit according to claim 3, characterized in that: During the turn-on process of the power MOSFET to be controlled (08), the gate voltage waveform of the power MOSFET to be controlled (08) follows the voltage waveform of the node net6 in the first charging module (04), and its specific expression method is: when the gate voltage of the power MOSFET to be controlled (08) is greater than the threshold voltage (Vth), the gate voltage of the power MOSFET to be controlled (08) follows the voltage of the node net6, and its rising slope is the same as the rising slope of the voltage of the node net6.

7. The driving method of a controllable wide adaptability MOSFET turn-on gate driving circuit according to claim 3, characterized in that: The specific expression method of the gate voltage waveform of the power MOSFET (08) to be controlled during the turn-on process is: When the gate voltage of the power MOSFET (08) to be controlled is lower than the threshold voltage (Vth), the gate voltage of the power MOSFET (08) to be controlled rises rapidly to reach the threshold voltage (Vth); When the gate voltage of the power MOSFET (08) to be controlled is greater than the threshold voltage (Vth) but less than the Miller platform (Vmiller), the gate voltage of the power MOSFET (08) to be controlled rises linearly and controllably; When the gate voltage of the power MOSFET (08) to be controlled is at the Miller platform (Vmiller), the gate voltage of the power MOSFET (08) to be controlled is maintained at the Miller platform (Vmiller) voltage; When the gate voltage of the power MOSFET (08) to be controlled is greater than the Miller platform (Vmiller), the gate voltage of the power MOSFET (08) to be controlled resumes a linear and controllable rise.

8. The driving method of a controllable wide adaptability MOSFET turn-on gate driving circuit according to claim 7, characterized in that: During the turning-on process of the power MOSFET to be controlled (08), the specific expression method of the drain-source current and drain-source voltage waveforms of the power MOSFET to be controlled (08) is as follows: When the resistance value of the sixth resistor (R6) remains unchanged, the larger the capacitance value of the first capacitor (C1), the smaller the slope of the drain-source current of the power MOSFET (08) to be controlled, and the smaller the absolute value of the slope of the drain-source voltage; When the capacitance value of the first capacitor (C1) remains unchanged, the larger the resistance value of the sixth resistor (R6), the smaller the slope of the drain-source current of the controlled power MOSFET (08), and the smaller the absolute value of the slope of the drain-source voltage.

9. A controllable wide adaptability MOSFET turn-on gate drive circuit and driving method according to any one of claims 1 to 8, characterized in that: During the opening process of the power MOSFET (08) to be controlled, the driving circuit does not need to introduce the drain-source side information of the power MOSFET (08) to be controlled, but only utilizes the change characteristics of the transconductance capacitance of the power MOSFET (08) to control the gate of the power MOSFET (08) to be controlled, and finally completes the control of the drain-source voltage and current trajectory of the power MOSFET (08) to be controlled.

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