An adjustable wide-adaptation MOSFET turn-on gate drive circuit and drive method

Abstract

A controllable wide-adaptation MOSFET turn-on gate drive circuit and drive method, which relates to the field of power electronics. In the design of this circuit, the drain-source side information of the power MOSFET to be controlled is not introduced. Only by finely controlling the gate voltage of the power MOSFET to be controlled, the regulation of the drain-source voltage and current trajectory of the power MOSFET to be controlled during the turn-on process is realized. This circuit matches the parasitic parameters of the power MOSFET to be controlled through parameter configuration to improve the applicability. During the turn-on process of the power MOSFET to be controlled, the voltage rising slope of the gate voltage in the stage higher than the threshold voltage is regulated, so as to realize the regulation of the drain-source voltage and current trajectory, and further regulate the electromagnetic noise generated by the drain-source current during the reverse recovery stage in the turn-on process according to the requirements of the power electronic device, solving the problems that the existing power MOSFET drive circuit is difficult to finely and continuously regulate the gate voltage during the turn-on process, unable to make the drain-source voltage and current meet both low electromagnetic interference and low loss during the turn-on process, and difficult to meet the high power density requirements of power electronic devices.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and particularly to an adjustable wide-adaptation MOSFET turn-on gate drive circuit and a drive method thereof. Background Art

[0002] During the turn-on process of a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), it is necessary to convert the turn-on digital signal into a turn-on analog signal suitable for the power MOSFET through gate drive and apply it to the gate of the power MOSFET to complete the turn-on operation. During the turn-on process of the power MOSFET, there is a contradiction between the electromagnetic interference caused by the rising current on the drain-source side and the turn-on loss. It is necessary to adjust the gate signal trajectory to change the drain-source side voltage and current trajectory to meet the requirements of power electronic devices.

[0003] Currently, the existing drive circuits can only adjust the power side voltage and current trajectory of the power MOSFET device during the turn-on process by adjusting the gate resistance, and cannot simultaneously meet the requirements of low electromagnetic interference and low loss during the turn-on process, making it difficult to meet the high power density requirements of power electronic devices. Summary of the Invention

[0004] The present invention is to solve the problem that the existing power MOSFET drive circuits cannot simultaneously meet the requirements of low electromagnetic interference and low loss during the turn-on process and are difficult to meet the high power density requirements of power electronic devices, and provides an adjustable wide-adaptation MOSFET turn-on gate drive circuit and a drive method thereof. Starting from the perspective of the turn-on mechanism of the power MOSFET, the present invention provides an adjustable wide-adaptation MOSFET turn-on gate drive circuit and a drive method thereof, plans the gate-source voltage trajectory during the turn-on process of the power MOSFET, and finely adjusts the drain-source side voltage and current trajectory during the turn-on process to achieve the purpose of low electromagnetic interference and low turn-on loss of the power MOSFET during the turn-on process.

[0005] Meanwhile, the adjustable wide-adaptation MOSFET turn-on gate drive circuit and the drive method proposed by the present invention can adjust the parameters according to the parasitic parameters of the power MOSFET to adapt to power MOSFETs with different parasitic parameters.

[0006] In addition, the adjustable wide-adaptation MOSFET turn-on gate drive circuit and the drive method proposed by the present invention can control the drain-source side voltage and current trajectory only by controlling the gate of the power MOSFET, without introducing high-voltage information on the drain-source side, reducing the insulation requirements and increasing the power density.

[0007] The technical solution adopted by the present invention is as follows:

[0008] A controllable wide - adaptation MOSFET turn - on gate drive circuit, which is applicable to power electronic devices using power MOSFET transistors. The power electronic devices include power converters and inverters. This circuit is used to drive the power MOSFET (08) to be controlled. The controllable wide - adaptation MOSFET turn - on gate drive circuit includes:

[0009] A first pre - charge module (01), including a first PMOS transistor (MP1) and a second PMOS transistor (MP2), whose gate inputs are respectively connected to a first turn - on enable signal (Vctrl1) and a second turn - on enable signal (Vctrl2). The source of the first PMOS transistor (MP1) is connected to the power supply VDD, the drain of the second PMOS transistor (MP2) is connected to the node net1, and the drain of the first PMOS transistor (MP1) is connected to the source of the second PMOS transistor (MP2);

[0010] A second pre - charge module (02), including a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), whose gate inputs are respectively connected to a third turn - on enable signal (Vctrl3) and a second turn - on enable signal (Vctrl2). The source of the third PMOS transistor (MP3) is connected to the power supply VDD, and the drain is connected to the node net4; the source of the fourth PMOS transistor (MP4) is connected to the node net4, and the drain is connected to the ground (GND);

[0011] A first energy - storage module (04), including a first NMOS transistor (MN1), a first resistor (R1), a second resistor (R2), a third resistor (R3), and a diode (D1); the gate input of the first NMOS transistor (MN1) is connected to a fourth turn - on enable signal (Vctrl4), the drain of the first NMOS transistor (MN1) is connected to the node net1 through the first resistor (R1), the source of the first NMOS transistor (MN1) is connected to the node net6 and is connected to the node net3 through the third resistor (R3); the cathode of the diode (D1) is connected to the node net3, the anode of the diode (D1) is connected to the node net2 and is connected to the node net1 through the second resistor (R2);

[0012] A second energy - storage module (05), including a fifth PMOS transistor (MP5), a second NMOS transistor (MN2), and a fourth resistor (R4); the source of the fifth PMOS transistor (MP5) is connected to the power supply VDD, the gate of the fifth PMOS transistor (MP5) is connected to the node net4, and the drain of the fifth PMOS transistor (MP5) is connected to the drain of the second NMOS transistor (MN2); the gate of the second NMOS transistor (MN2) is connected to the node net2, and the source of the second NMOS transistor (MN2) is connected to the output terminal Vgate through the fourth resistor (R4);

[0013] The bias module (03) includes a third NMOS transistor (MN3) and a fifth resistor (R5). The drain of the third NMOS transistor (MN3) is connected to node net5 and is connected to node net3 through the fifth resistor (R5). The gate of the third NMOS transistor (MN3) is connected to the input bias signal Vbias. The source of the third NMOS transistor (MN3) is connected to ground (GND).

[0014] The third charging module (06) includes a fourth NMOS transistor (MN4). The drain of the fourth NMOS transistor (MN4) is connected to the power supply VDD, the gate is connected to node net5, and the source is connected to the output terminal Vgate.

[0015] The parameter configuration module (07) includes an adjustable sixth resistor (R6) and an adjustable first capacitor (C1). The sixth resistor (R6) is connected to the third resistor (R3) in the first charging module (04) at node net6, and the sixth resistor (R6) is connected to ground (GND) through the first capacitor (C1).

[0016] The external gate resistor (09) is used to connect to the gate of the external power MOSFET (08) to be controlled.

[0017] Furthermore, the first pre-charging module (01) is connected to the first charging module (04) at node net1; the second pre-charging module (02) is connected to the second charging module (05) at node net4;

[0018] The inputs of the first pre-charging module (01) are the first turn-on enable signal (Vctrl1) and the second turn-on enable signal (Vctrl2);

[0019] The inputs of the second pre-charging module (02) are the second turn-on enable signal (Vctrl2) and the third turn-on enable signal (Vctrl3);

[0020] The input of the first charging module (04) is the fourth turn-on enable signal (Vctrl4). The first charging module (04) is connected to the first pre-charging module (01) at node net1, connected to the second charging module (05) at nodes net2 and net3, connected to the bias module (03) at node net3, and connected to the output terminal of the parameter configuration module (03);

[0021] The second charging module (05) is connected to the second pre-charging module (02) at node net4, connected to the first charging module (04) at nodes net2 and net3, and connected to the third charging module (06) at the output terminal (Vgate);

[0022] The bias module (03) is connected to the first charging module (04) at node net3 and to the third charging module (06) at node net5. The input of the bias module (03) is the bias signal Vbias;

[0023] The third charging module (06) is connected to the bias module (03) at node net5 and is connected to the second charging module (05) through the output terminal (Vgate) to the external gate resistor (09);

[0024] The output terminal of the parameter configuration module (07) is connected to the first charging module (04) at node net6.

[0025] Based on a driving method for an adjustable wide - adaptation MOSFET turn - on gate driving circuit, the method is as follows:

[0026] The first pre - charging module (01) is used to raise the potentials of nodes net1, net2, and net3 during the pre - turn - on stage according to the first turn - on enable signal (Vctrl1) and the second turn - on enable signal (Vctrl2);

[0027] The second pre - charging module (02) is used to raise the potential of node net4 during the pre - turn - on stage according to the third turn - on enable signal (Vctrl3) and in combination with the state of the first pre - charging module (01);

[0028] The bias module (03) is used to establish the voltage of node net5 affected by the parameter configuration module (07) according to the bias signal Vbias and in combination with the voltage information of nodes net1, net2, and net3;

[0029] The first charging module (04) is used to change the voltages of nodes net1, net2, net3, and net6 during the turn - on process according to the fourth turn - on enable signal (Vctrl4) and the internal parameters of the parameter configuration module (07);

[0030] The second charging module (05) is used to provide a charging current to the output terminal Vgate during the turn - on process according to the voltages of nodes net2, net3, and net4;

[0031] The third charging module (06) is used to change the voltage of the output terminal Vgate during the turn - on process according to the voltage of node net5 and provide a charging current to the gate of the power MOSFET to be controlled (08);

[0032] The parameter configuration module (07) is used to adjust the voltage change trends of nodes net5 and net6 during the turn-on process, and finally affect the gate voltage trajectory of the power MOSFET to be controlled (08) through the output terminal Vgate during the turn-on process.

[0033] Further, the values of the sixth resistor (R6) and the first capacitor (C1) in the parameter configuration module (07) are configured according to the parasitic parameters of the power MOSFET to be controlled (08); the specific manifestation method of the voltage waveform of node net6 in the first energy storage module (04) is as follows:

[0034] During the turn-on process of the power MOSFET to be controlled (08), when the gate voltage of the power MOSFET to be controlled (08) is lower than the threshold voltage (Vth), the voltage of node net6 rises rapidly and linearly;

[0035] During the turn-on process of the power MOSFET to be controlled (08), when the gate voltage of the power MOSFET to be controlled (08) is higher than the threshold voltage (Vth), the voltage of node net6 rises linearly and controllably.

[0036] Further, during the turn-on process of the power MOSFET to be controlled (08), the specific manifestation method of the gate voltage waveform affected by the resistance and capacitance values of the sixth resistor (R6) and the first capacitor (C1) in the parameter configuration module (07) is as follows:

[0037] When the capacitance value of the first capacitor (C1) remains unchanged, the larger the resistance value of the sixth resistor (R6), the higher the starting voltage of the linearly controllable rising stage of the gate voltage of the power MOSFET to be controlled (08) connected through the output terminal (Vgate) and the external gate resistor (09);

[0038] When the resistance value of the sixth resistor (R6) remains unchanged, the larger the capacitance value of the first capacitor (C1), the smaller the slope of the gate voltage of the power MOSFET to be controlled (08) connected through the output terminal (Vgate) and the external gate resistor (09) in the stage higher than the threshold voltage (Vth), and vice versa.

[0039] Further, during the turn-on process of the power MOSFET to be controlled (08), the gate voltage waveform of the power MOSFET to be controlled (08) follows the voltage waveform of node net6 in the first energy storage module (04), and its specific manifestation method is: when the gate voltage of the power MOSFET to be controlled (08) is greater than the threshold voltage (Vth), the rising slope of the gate voltage of the power MOSFET to be controlled (08) is the same as the rising slope of the voltage of node net6.

[0040] Further, the specific manifestation method of the gate voltage waveform of the power MOSFET (08) to be controlled during the turn-on process is as follows:

[0041] When the gate voltage of the power MOSFET (08) to be controlled is lower than the threshold voltage (Vth), the gate voltage of the power MOSFET (08) to be controlled rapidly reaches the threshold voltage (Vth);

[0042] When the gate voltage of the power MOSFET (08) to be controlled is greater than the threshold voltage (Vth) but less than the Miller plateau (Vmiller), the gate voltage of the power MOSFET (08) to be controlled linearly and controllably rises;

[0043] When the gate voltage of the power MOSFET (08) to be controlled is at the Miller plateau (Vmiller), the gate voltage of the power MOSFET (08) to be controlled remains at the Miller plateau (Vmiller) voltage;

[0044] When the gate voltage of the power MOSFET (08) to be controlled is greater than the Miller plateau (Vmiller), the gate voltage of the power MOSFET (08) to be controlled resumes linearly and controllably rising.

[0045] Further, during the turn-on process of the power MOSFET (08) to be controlled, the specific manifestation method of the drain-source current and drain-source voltage waveforms of the power MOSFET (08) to be controlled is as follows:

[0046] When the resistance value of the sixth resistor (R6) remains unchanged, the larger the capacitance value of the first capacitor (C1), the smaller the slope of the drain-source current of the power MOSFET (08) to be controlled, and the smaller the absolute value of the slope of the drain-source voltage;

[0047] When the capacitance value of the first capacitor (C1) remains unchanged, the larger the resistance value of the sixth resistor (R6), the smaller the slope of the drain-source current of the power MOSFET (08) to be controlled, and the smaller the absolute value of the slope of the drain-source voltage.

[0048] Further, during the turn-on process of the power MOSFET (08) to be controlled, the drive circuit does not need to introduce the drain-source side information of the power MOSFET (08) to be controlled. Only by utilizing the change characteristics of the transconductance capacitance of the power MOSFET (08) to be controlled, the gate of the power MOSFET (08) to be controlled is regulated, and finally the regulation of the drain-source voltage and current trajectories of the power MOSFET (08) to be controlled is completed.

[0049] Beneficial effects:

[0050] Compared with the prior art, the present invention has the following advantages:

[0051] 1. During the turn-on process of the power MOSFET to be controlled, finely regulate the drain-source voltage and current trajectory of the power MOSFET to be controlled, so that the power MOSFET has the characteristics of low electromagnetic interference and low turn-on loss during the turn-on process;

[0052] 2. Match the parasitic parameters of the power MOSFET to be controlled through the parameter configuration module to improve the universality of the turn-on drive circuit;

[0053] 3. Avoid the introduction of high-voltage information on the drain-source side of the power MOSFET to be controlled, reduce the insulation requirements, and improve the power density. Description of the Drawings

[0054] Figure 1 It is a schematic structural diagram of a controllable wide-adaptation MOSFET turn-on gate drive circuit;

[0055] Figure 2 It is a circuit diagram of a controllable wide-adaptation MOSFET turn-on gate drive circuit;

[0056] Figure 3 It is a waveform diagram of the voltage of node net6 of a controllable wide-adaptation MOSFET turn-on gate drive circuit;

[0057] Figure 4 It is a waveform diagram of the voltage of node net6 of a controllable wide-adaptation MOSFET turn-on gate drive circuit affected by the sixth resistor in the parameter configuration module;

[0058] Figure 5 It is a waveform diagram of the voltage of node net6 of a controllable wide-adaptation MOSFET turn-on gate drive circuit affected by the first capacitor in the parameter configuration module;

[0059] Figure 6 It is a waveform diagram of the voltage of node net6 of a controllable wide-adaptation MOSFET turn-on gate drive circuit and the voltage applied to the gate of the power MOSFET to be controlled;

[0060] Figure 7 It is a waveform diagram of the gate voltage of the power MOSFET to be controlled of a controllable wide-adaptation MOSFET turn-on gate drive circuit (including the voltage waveforms of node net6 and the gate of the power MOSFET to be controlled during the turn-on process);

[0061] Figure 8 It is a waveform diagram of the drain-source voltage and drain-source current of the power MOSFET to be controlled affected by the first capacitor in the parameter configuration module;

[0062] Figure 9 It is a waveform diagram of the drain-source voltage and drain-source current of the power MOSFET to be controlled affected by the sixth resistor in the parameter configuration module. Detailed Embodiment

[0063] Embodiment 1: Refer to Figures 1 to 9 to specifically describe this embodiment. The adjustable wide - adaptation MOSFET turn - on gate driving circuit and driving method described in this embodiment are applicable to power electronic devices using power MOSFETs. The power electronic devices include power converters and inverters. Figure 1 , 2 As shown, it is applicable to power electronic devices using power MOSFETs, and the power electronic devices include power converters and inverters.

[0064] The one includes a first pre - charge module, a second pre - charge module, a first energy - storage module, a second energy - storage module, a bias module, a third energy - storage module, a parameter configuration module, an external power MOSFET to be controlled, and an external gate resistor. Figure 2 As shown, where:

[0065] The first pre - charge module includes a first PMOS transistor MP1 and a second PMOS transistor MP2. Their gate inputs are respectively connected to a first turn - on enable signal Vctrl1 and a second turn - on enable signal Vctrl2. The source of the first PMOS transistor MP1 is connected to the power supply VDD, and the drain of the second PMOS transistor MP2 is connected to node net1.

[0066] The second pre - charge module includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4. Their gate inputs are respectively connected to a third turn - on enable signal Vctrl3 and a second turn - on enable signal Vctrl2. The source of the third PMOS transistor MP3 is connected to the power supply VDD, and the drain is connected to node net4. The source of the fourth PMOS transistor MP4 is connected to node net4, and the drain is connected to the ground GND.

[0067] The first energy - storage module includes a first NMOS transistor MN1, a first resistor R1, a second resistor R2, a third resistor R3, and a diode D1. The gate input of the first NMOS transistor (MN1) is connected to a fourth turn - on enable signal (Vctrl4). The drain of the first NMOS transistor MN1 is connected to node net1 through the first resistor R1. The source of the first NMOS transistor is connected to node net6 and is connected to node net3 through the third resistor R3. The cathode of the diode (D1) is connected to node net3, the anode of the diode is connected to node net2, and is connected to node net1 through the second resistor (R2).

[0068] The second energy - storage module includes a fifth PMOS transistor MP5, a second NMOS transistor MN2, and a fourth resistor R4. The source of the fifth PMOS transistor MP5 is connected to the power supply VDD. The gate of the fifth PMOS transistor is connected to node net4. The drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor MN2. The drain of the second NMOS transistor is connected to the drain of the fifth PMOS transistor. The gate of the second NMOS transistor is connected to node net2. The source of the second NMOS transistor is connected to the output terminal Vgate through the fourth resistor R4.

[0069] The bias module includes a third NMOS transistor MN3 and a fifth resistor R5. The drain of the third NMOS transistor is connected to node net5 and is connected to node net3 through the fifth resistor R5. The gate of the third NMOS transistor is connected to the input bias signal Vbias. The source of the third NMOS transistor is connected to the ground GND.

[0070] The third charging module includes a fourth NMOS transistor MN4. The drain of the fourth NMOS transistor is connected to the power supply VDD, the gate is connected to node net5, and the source is connected to the output Vgate.

[0071] The parameter configuration module includes an adjustable sixth resistor R6 and an adjustable first capacitor C1. The sixth resistor R6 is connected to the third resistor R3 in the first charging module O4 at node net6, and the sixth resistor is connected to the ground GND through the first capacitor C1.

[0072] The above-mentioned first pre-charging module and second pre-charging module are respectively connected to the first charging module and second charging module at node net1, node net2, and node net3. The inputs of the first pre-charging module are the first turn-on enable signal Vctrl1 and the second turn-on enable signal Vctrl2. The inputs of the second pre-charging module are the second turn-on enable signal Vctrl2 and the third turn-on enable signal Vctrl3. The input of the first charging module is the fourth turn-on enable signal Vctrl4, which is connected to the first pre-charging module at node net1, connected to the second charging module at node net2 and node net3, connected to the bias module at node net3, and connected to the output of the parameter configuration module. The second charging module is connected to the second pre-charging module at node net4, connected to the first charging module at node net2 and node net3, and connected to the third charging module at the output Vgate. The bias module is connected to the first charging module at node net3 and connected to the third charging module at node net5. The input of the bias module is the bias signal Vbias. The third charging module is connected to the bias module at node net5 and connected to the second charging module through the output Vgate to an external gate resistor. The output of the parameter configuration module is connected to the first charging module at node net6. The external power MOSFET to be controlled is connected to the output Vgate through an external gate resistor.

[0073] Embodiment 2: During the turn-on process of the power MOSFET to be controlled, the functions of the above-mentioned modules are specifically manifested as follows:

[0074] The first pre-charging module is used to raise the potentials of node net1, node net2, and node net3 in the pre-turn-on stage according to the first turn-on enable signal Vctrl1 and the second turn-on enable signal Vctrl2.

[0075] The second pre-charge module is used to raise the potential of node net4 during the pre-turn-on stage according to the third turn-on enable signal Vctrl3 and in combination with the state of the first pre-charge module;

[0076] The bias module is used to establish the voltage of node net5 affected by the parameter configuration module according to the bias signal Vbias and in combination with the voltage information of node net1, node net2, and node net3;

[0077] The first energy charging module is used to change the voltages of node net1, node net2, and node net3 during the turn-on process of the power MOSFET to be controlled according to the fourth turn-on enable signal Vctrl4 and the configuration parameters of the parameter configuration module;

[0078] The second energy charging module is used to provide a charging current to the output terminal Vgate during the turn-on process of the power MOSFET to be controlled according to the voltages of node net2, node net3, and node net4;

[0079] The third energy charging module is used to change the voltage of the output terminal Vgate during the turn-on process of the power MOSFET to be controlled according to the voltage of node net5 and provide a charging current to the gate of the power MOSFET to be controlled;

[0080] The parameter configuration module is used to adjust the voltage change trajectories of node net5 and node net6 during the turn-on process of the power MOSFET to be controlled, and finally affect the gate voltage trajectory of the power MOSFET to be controlled during the turn-on process.

[0081] For the adjustable wide-adaptation MOSFET turn-on gate drive circuit, the working principle among the modules is as follows:

[0082] During the turn-on process of the power MOSFET to be controlled, the first turn-on enable signal Vctrl1 and the second turn-on enable signal Vctrl2 in the first pre-charge module are pulled low, so that the first PMOS transistor MP1 and the second PMOS transistor MP2 establish channels to raise the potential of node net1;

[0083] The second pre-charge module is pulled low by the second turn-on enable signal Vctrl2 and the third turn-on enable signal Vctrl3, so that the third PMOS transistor MP3 and the fourth PMOS transistor MP4 establish channels to raise the potential of node net4;

[0084] The first charging module is affected by the fourth turn-on enable signal Vctrl4, driving the first NMOS transistor MN1 to establish a channel, enabling the node net1 to establish a first current path to the parameter configuration module through the first resistor R1 and the first NMOS transistor MN1, raising the potential of the node net6. Moreover, the rise of the potential of the node net6 is affected by the sixth resistor R6 and the first capacitor C1 in the parameter configuration module, and is also affected by the parasitic capacitance of the power MOSFET to be controlled;

[0085] Meanwhile, the node net1 establishes a second current path to the node net3 through the first resistor R1, the first NMOS transistor MN1, and the third resistor R3, raising the potential of the node net3. Moreover, the rise of the potential of the node net3 is affected by the sixth resistor R6 and the first capacitor C1 in the parameter configuration module, and is also affected by the parasitic capacitance of the power MOSFET to be controlled;

[0086] Meanwhile, the node net1 establishes a third current path to the node net3 through the second resistor R2 and the diode D1, raising the potential of the node net3. Moreover, the rise of the potential of the node net3 is affected by the sixth resistor R6 and the first capacitor C1 in the parameter configuration module, and is also affected by the parasitic capacitance of the power MOSFET to be controlled;

[0087] The bias voltage Vbias in the bias module maintains a constant voltage value, enabling the third NMOS transistor MN3 to be always in the on state. Thus, affected by the node net3 in the first charging module, the bias module rapidly raises the potential of the node net5 through the node net3 and the fifth resistor R5, enabling the fourth NMOS transistor MN4 in the third charging module to quickly establish a channel and obtain the current-carrying capacity;

[0088] The fifth PMOS transistor MP5 in the second charging module establishes a channel affected by the potential of the node net4 in the second pre-charging module, and the second NMOS transistor establishes a channel affected by the fourth turn-on enable signal Vctrl4. Thus, the second charging module establishes a fourth current path to the output terminal Vgate through the fifth PMOS transistor MP5, the second NMOS transistor MN2, and the fourth resistor R4; Further, the current-carrying capacity of the fourth current path is affected by the potential of the node net4 in the second pre-charging module and the potential of the node net2 in the first charging module;

[0089] The fourth NMOS transistor MN4 in the third charging module establishes a channel affected by the final potential of the node net5 in the bias module, establishing a fifth current path to the output terminal Vgate, and its current-carrying capacity is affected by the potential of the node net5. Specific Embodiment 3:

[0091] The values of the sixth resistor R6 and the first capacitor C1 in the parameter configuration module can be configured according to the parasitic parameters of the power MOSFET to be controlled. During the turn-on process of the power MOSFET to be controlled, the voltage waveform of node net6 is as follows: During the turn-on process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled is lower than the threshold voltage, the voltage of node net6 rises rapidly and linearly; during the turn-on process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled is higher than the threshold voltage, the voltage of node net6 rises linearly and controllably, as Figure 3 shown.

[0092] The resistance value of the sixth resistor R6 and the capacitance value of the first capacitor C1 in the parameter configuration module have a regulating effect on the voltage of node net6 and affect the voltage waveform of node net6 during the turn-on process of the power MOSFET to be controlled. The specific manifestations are as follows:

[0093] When the capacitance value of the first capacitor C1 remains unchanged, the larger the resistance value of the sixth resistor R6, the higher the starting voltage of the linearly controllable rising stage of the voltage of node net6 when the gate voltage of the power MOSFET to be controlled is higher than the threshold voltage, as Figure 4 shown; when the resistance value of the sixth resistor R6 remains unchanged, the larger the capacitance value of the first capacitor C1, the smaller the voltage slope of node net6 during the linearly controllable rising stage when the gate voltage of the power MOSFET to be controlled is higher than the threshold voltage Vth, as Figure 5 shown;

[0094] For the adjustable wide-adaptation MOSFET turn-on gate drive circuit, the voltage trajectory applied to the gate of the power MOSFET to be controlled follows the voltage trajectory of node net6. That is, when the gate voltage of the power MOSFET to be controlled is higher than the threshold voltage (Vth), its voltage rising slope is the same as that of node net6, as Figure 6 shown;

[0095] As Figure 7 shown, for the adjustable wide-adaptation MOSFET turn-on gate drive circuit, the voltage waveform applied to the gate of the power MOSFET to be controlled during the turn-on process of the power MOSFET to be controlled is as follows:

[0096] When the gate voltage of the power MOSFET to be controlled is lower than the threshold voltage Vth, the gate voltage of the power MOSFET to be controlled quickly reaches the threshold voltage;

[0097] When the gate voltage of the power MOSFET to be controlled is greater than the threshold voltage Vth but less than the Miller plateau Vmiller, the gate voltage of the power MOSFET to be controlled rises linearly and controllably;

[0098] When the gate voltage of the power MOSFET to be controlled is at the Miller plateau Vmiller, the gate voltage of the power MOSFET to be controlled remains at the Miller plateau (Vmiller) voltage;

[0099] When the gate voltage of the power MOSFET (08) to be controlled is greater than the Miller plateau (Vmiller), the gate voltage of the power MOSFET (08) to be controlled resumes a linearly controllable rise.

[0100] During the turn-on process of the power MOSFET to be controlled by the adjustable wide-adaptation MOSFET turn-on gate drive circuit, the drain-source current and drain-source voltage waveforms of the power MOSFET to be controlled are affected by the parameter configuration module, specifically manifested as:

[0101] When the resistance value of the sixth resistor (R6) remains unchanged, the larger the capacitance value of the first capacitor (C1), the smaller the slope of the drain-source current of the power MOSFET to be controlled and the smaller the absolute value of the slope of the drain-source voltage, as Figure 8 shown;

[0102] When the capacitance value of the first capacitor (C1) remains unchanged, the larger the resistance value of the sixth resistor (R6), the smaller the slope of the drain-source current of the power MOSFET to be controlled and the smaller the absolute value of the slope of the drain-source voltage, as Figure 9 shown; Specific Embodiment 4:

[0104] Starting from the perspective of the power MOSFET turn-on process mechanism, the present invention provides an adjustable wide-adaptation MOSFET turn-on gate drive circuit and a drive method. The adjustable wide-adaptation MOSFET turn-on gate drive circuit and the drive method adjust the voltage change trajectory of node net6 through the voltage characteristics of the RC circuit composed of the sixth resistor R6 and the first capacitor C1 in the parameter configuration module during the charging process, as Figure 3 、 4 、shown in Figure 5; further, through the adjustable wide-adaptation MOSFET turn-on gate drive circuit and the drive method, the gate voltage trajectory of the power MOSFET to be controlled follows the voltage trajectory of node net6, and the gate voltage trajectory of the power MOSFET to be controlled is planned by planning the voltage trajectory of node net6, as Figure 6 shown; through the adjustable wide-adaptation MOSFET turn-on gate drive circuit and the drive method, the planned voltage trajectory is achieved by controlling the gate voltage of the power MOSFET to be controlled during the turn-on process, as Figure 7 shown; thus, the adjustable wide-adaptation MOSFET turn-on gate drive circuit and the drive method achieve the regulation of the drain-source voltage and current trajectories through fine control of the gate voltage, and achieve fine regulation of the drain-source current overshoot, drain-source current slope, and drain-source voltage slope of the power MOSFET to be controlled during the turn-on process, as Figure 8, 9 as shown

[0105] Meanwhile, the adjustable wide - adaptation MOSFET turn - on gate drive circuit and drive method proposed by the present invention can adjust parameters according to the parasitic parameters of the power MOSFET through the parameter configuration module to adapt to power MOSFETs with different parasitic parameters.

[0106] In addition, the adjustable wide - adaptation MOSFET turn - on gate drive circuit and drive method proposed by the present invention do not introduce the drain - source side information of the power MOSFET to be controlled. By sensing the stage of the turn - on process of the power MOSFET to be controlled through the gate - source side characteristics of the power MOSFET to be controlled, and based on this, the drain - source side voltage and current trajectories of the power MOSFET to be controlled are regulated through gate - source side regulation, reducing the insulation requirements and circuit complexity and improving the power density. This drive circuit matches the parasitic parameters of the power MOSFET to be controlled through the parameter configuration module. During the turn - on process of the power MOSFET to be controlled, the voltage rise slope of the gate voltage in the stage greater than the threshold voltage (Vth) is regulated, so as to realize the regulation of the drain - source side voltage and current trajectories, and then regulate the electromagnetic noise generated by the overshoot of the drain - source current during the turn - on process according to the requirements of the power electronic device, and optimize between the electromagnetic noise and the turn - on loss.

[0107] This circuit solves the problems that the existing power MOSFET drive circuits are difficult to finely and continuously regulate the gate voltage during the turn - on process, cannot simultaneously meet low electromagnetic interference and low loss during the turn - on process, and are difficult to meet the high - power - density requirements of power electronic devices. This circuit does not introduce the drain - source side information of the power MOSFET to be controlled in design, and only realizes the regulation of the drain - source side voltage and current trajectories of the power MOSFET to be controlled by finely controlling the gate voltage of the power MOSFET to be controlled, reducing the insulation requirements and circuit complexity and improving the power density.

[0108] The present invention is illustrated by several specific embodiments. Those skilled in the art should understand that various transformations and equivalent substitutions can be made to the present invention without departing from the scope of the present invention. In addition, various modifications can be made to the present invention for specific situations or circumstances without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed, but should include all embodiments falling within the scope of the claims of the present invention.

Claims

1. A controllable wide-adaptability MOSFET turn-on gate drive circuit, the drive circuit is suitable for a power electronic device using a power MOSFET transistor, the power electronic device includes an electric energy converter and an inverter, the circuit is used to drive a power MOSFET to be controlled (08), characterized in that: The adjustable wide adaptability MOSFET turn-on gate drive circuit comprises: A first pre-charging module (01) comprises a first PMOS tube (MP1) and a second PMOS tube (MP2), wherein gate inputs thereof are respectively connected to a first turn-on enable signal (Vctrl1) and a second turn-on enable signal (Vctrl2), a source of the first PMOS tube (MP1) is connected to a power supply VDD, a drain of the second PMOS tube (MP2) is connected to a node net1, and a drain of the first PMOS tube (MP1) is connected to a source of the second PMOS tube (MP2); A second pre-charging module (02) comprises a third PMOS tube (MP3) and a fourth PMOS tube (MP4), wherein gate inputs thereof are respectively connected to a third turn-on enable signal (Vctrl3) and a second turn-on enable signal (Vctrl2); a source of the third PMOS tube (MP3) is connected to a power supply VDD, and a drain is connected to a node net4; a source of the fourth PMOS tube (MP4) is connected to the node net4, and a drain is connected to a ground (GND); A first charging module (04) comprises a first NMOS tube (MN1), a first resistor (R1), a second resistor (R2), a third resistor (R3), and a diode (D1); a gate input of the first NMOS tube (MN1) is connected to a fourth enable signal (Vctrl4); a drain of the first NMOS tube (MN1) is connected to a node net1 via the first resistor (R1); a source of the first NMOS tube (MN1) is connected to a node net6 and is connected to a node net3 via the third resistor (R3); a cathode of the diode (D1) is connected to a node net3, an anode of the diode (D1) is connected to a node net2, and is connected to a node net1 via the second resistor (R2); The second charging module (05) comprises a fifth PMOS tube (MP5), a second NMOS tube (MN2) and a fourth resistor (R4); the source of the fifth PMOS tube (MP5) is connected to a power supply VDD, the gate of the fifth PMOS tube is connected to a node net4, and the drain of the fifth PMOS tube is connected to a drain of the second NMOS tube (MN2); the gate of the second NMOS tube (MN2) is connected to a node net2, and the source of the second NMOS tube (MN2) is connected to an output terminal Vgate via a fourth resistor (R4); A bias module (03) comprises a third NMOS tube (MN3) and a fifth resistor (R5); the drain of the third NMOS tube (MN3) is connected to a node net5 and connected to a node net3 via the fifth resistor (R5); the gate of the third NMOS tube (MN3) is connected to an input bias signal Vbias; and the source of the third NMOS tube (MN3) is connected to a ground (GND); A third charging module (06) comprises a fourth NMOS tube (MN4), wherein the drain of the fourth NMOS tube (MN4) is connected to a power supply VDD, the gate is connected to a node net5, and the source is connected to an output terminal Vgate; A parameter configuration module (07), comprising an adjustable sixth resistor (R6) and an adjustable first capacitor (C1), the sixth resistor (R6) and the third resistor (R3) in the first charging module (04) being connected to a node net6, and the sixth resistor (R6) being connected to a ground (GND) via the first capacitor (C1); The external gate resistor (09) is used to connect the gate of the external power MOSFET (08) to be controlled.

2. The adjustable wide adaptability MOSFET turn-on gate drive circuit according to claim 1, characterized in that: The first pre-charging module (01) and the first charging module (04) are connected to a node net1; the second pre-charging module (02) and the second charging module (05) are connected to a node net4; The input of the first pre-charging module (01) is a first enable signal (Vctrl1) and a second enable signal (Vctrl2); The input of the second pre-charging module (02) is a second enable signal (Vctrl2) and a third enable signal (Vctrl3); The input of the first charging module (04) is a fourth enable signal (Vctrl4), the first charging module (04) is connected to the first pre-charging module (01) at a node net1, connected to the second charging module (05) at a node net2 and a node net3, connected to the bias module (03) at a node net3, and connected to the output end of the parameter configuration module (03); The second energy charging module (05) is connected to the second pre-charging module (02) at a node net4, is connected to the first energy charging module (04) at a node net2 and a node net3, and is connected to the third energy charging module (06) at an output terminal (Vgate); The bias module (03) is connected to the first charging module (04) at a node net3, and is connected to the third charging module (06) at a node net5, and the input of the bias module (03) is a bias signal Vbias; The third energy charging module (06) is connected to the bias module (03) at a node net5, and is connected to the external gate resistor (09) via an output terminal (Vgate) of the second energy charging module (05); The output end of the parameter configuration module (07) is connected to the first charging module (04) at a node net6.

3. The adjustable wide adaptability MOSFET turn-on gate drive circuit according to any one of claims 1 to 2, characterized in that: During the turning-on process of the power MOSFET (08) to be controlled, the driving circuit does not need to introduce information on the drain-source side of the power MOSFET (08) to be controlled, but only utilizes the change characteristics of the transconductance capacitance of the power MOSFET (08) to control only the gate of the power MOSFET (08) to be controlled, and finally completes the control of the drain-source voltage and current trajectory of the power MOSFET (08) to be controlled.

4. The driving method of a controllable wide adaptability MOSFET turn-on gate driving circuit according to claim 3, characterized in that: The first pre-charging module (01) is used to increase the potentials of the node net1, the node net2 and the node net3 in the pre-opening stage according to the first opening enable signal (Vctrl1) and the second opening enable signal (Vctrl2); The second pre-charging module (02) is used to increase the potential of the node net4 in the pre-opening phase according to the third opening enable signal (Vctrl3) and in combination with the state of the first pre-charging module (01); The bias module (03) is used to establish a net5 node voltage affected by the parameter configuration module (07) according to the bias signal Vbias and in combination with the voltage information of the nodes net1, net2 and net3; The first charging module (04) is used to change the voltages of the nodes net1, net2, net3 and net6 during the opening process according to the fourth opening enable signal (Vctrl4) and the internal parameters of the parameter configuration module (07); The second charging module (05) is used to provide a charging current to the output terminal Vgate during the opening process according to the voltages of the nodes net2, net3 and net4; The third charging module (06) is used to change the voltage of the output terminal Vgate during the opening process according to the voltage of the node net5, and provide a charging current to the gate of the power MOSFET (08) to be controlled; The parameter configuration module (07) is used to adjust the voltage variation trend of the node net5 and the node net6 during the opening process, and finally influence the gate voltage trajectory of the controlled power MOSFET (08) through the output terminal Vgate during the opening process.

5. The driving method of a controllable wide adaptability MOSFET turn-on gate driving circuit according to claim 4, characterized in that: The values ​​of the sixth resistor (R6) and the first capacitor (C1) in the parameter configuration module (07) are configured according to the parasitic parameters of the power MOSFET (08) to be controlled; the specific expression method of the voltage waveform of the node net6 in the first charging module (04) is: During the turn-on process of the power MOSFET to be controlled (08), when the gate voltage of the power MOSFET to be controlled (08) is lower than the threshold voltage (Vth), the voltage of the node net6 rises rapidly and linearly; During the turn-on process of the power MOSFET to be controlled (08), when the gate voltage of the power MOSFET to be controlled (08) is higher than the threshold voltage (Vth), the voltage of the node net6 rises linearly and controllably.

6. The driving method of a controllable wide-adaptability MOSFET turn-on gate driving circuit according to claim 4, characterized in that: During the turn-on process of the controlled power MOSFET (08), the gate voltage waveform generated by the voltage of the node net6 being affected by the resistance and capacitance values ​​of the sixth resistor (R6) and the first capacitor (C1) in the parameter configuration module (07) is specifically expressed as follows: When the capacitance value of the first capacitor (C1) remains unchanged, the greater the resistance value of the sixth resistor (R6), the higher the starting voltage of the linearly controllable rising phase of the gate voltage of the controlled power MOSFET (08) connected to the output terminal (Vgate) via the external gate resistor (09); When the resistance value of the sixth resistor (R6) remains unchanged, the greater the capacitance value of the first capacitor (C1), the smaller the slope of the gate voltage of the power MOSFET (08) to be controlled connected via the output terminal (Vgate) via the external gate resistor (09) in the stage where the gate voltage is higher than the threshold voltage (Vth), and vice versa.

7. The driving method of a controllable wide adaptability MOSFET turn-on gate driving circuit according to claim 4, characterized in that: During the turn-on process of the power MOSFET to be controlled (08), the gate voltage waveform of the power MOSFET to be controlled (08) follows the voltage waveform of the node net6 in the first charging module (04), and its specific expression method is: when the gate voltage of the power MOSFET to be controlled (08) is greater than the threshold voltage (Vth), the gate voltage of the power MOSFET to be controlled (08) follows the voltage of the node net6, and its rising slope is the same as the rising slope of the voltage of the node net6.

8. The driving method of a controllable wide adaptability MOSFET turn-on gate driving circuit according to claim 4, characterized in that: The specific expression method of the gate voltage waveform of the power MOSFET (08) to be controlled during the turn-on process is: When the gate voltage of the power MOSFET to be controlled (08) is lower than the threshold voltage (Vth), the gate voltage of the power MOSFET to be controlled (08) rises rapidly to reach the threshold voltage (Vth); When the gate voltage of the power MOSFET (08) to be controlled is greater than the threshold voltage (Vth) but less than the Miller platform (Vmiller), the gate voltage of the power MOSFET (08) to be controlled rises linearly and controllably; When the gate voltage of the power MOSFET to be controlled (08) is at the Miller platform (Vmiller), the gate voltage of the power MOSFET to be controlled (08) is maintained at the Miller platform (Vmiller) voltage; When the gate voltage of the power MOSFET (08) to be controlled is greater than the Miller platform (Vmiller), the gate voltage of the power MOSFET (08) to be controlled resumes a linear and controllable rise.

9. The driving method of a controllable wide-adaptability MOSFET turn-on gate driving circuit according to claim 8, characterized in that: During the turning-on process of the power MOSFET to be controlled (08), the specific expression method of the drain-source current and drain-source voltage waveforms of the power MOSFET to be controlled (08) is as follows: When the resistance value of the sixth resistor (R6) remains unchanged, the larger the capacitance value of the first capacitor (C1), the smaller the slope of the drain-source current of the power MOSFET (08) to be controlled, and the smaller the absolute value of the slope of the drain-source voltage; When the capacitance value of the first capacitor (C1) remains unchanged, the greater the resistance value of the sixth resistor (R6), the smaller the slope of the drain-source current of the power MOSFET (08) to be controlled, and the smaller the absolute value of the slope of the drain-source voltage.

10. A driving method for a controllable wide adaptability MOSFET turn-on gate drive circuit according to any one of claims 4 to 9, characterized in that: During the turning-on process of the power MOSFET (08) to be controlled, the driving circuit does not need to introduce information on the drain-source side of the power MOSFET (08) to be controlled, but only utilizes the change characteristics of the transconductance capacitance of the power MOSFET (08) to control only the gate of the power MOSFET (08) to be controlled, and finally completes the control of the drain-source voltage and current trajectory of the power MOSFET (08) to be controlled.

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