Low-delay cross-asynchronization method and circuit based on Chiplet interconnection direction

Abstract

The invention aims to provide a low-delay cross-asynchronization method and circuit based on a Chiplet interconnection direction. The method comprises the following steps: judging delay conditions of target operation and source operation; transmitting a delay signal to a destination operation and a source operation according to the delay condition; and the target operation and the source operation perform data writing and reading according to the delay signal. The absolute values of the write delay and the read delay are pre-evaluated according to the source clock frequency and the target clock frequency, the delay path in the source clock direction and the delay path in the target clock direction are designed through the delay cell, the sequence of starting the source clock operation and the target clock operation by the switch is controlled, it is guaranteed that write-ratio reading is started firstly, and therefore the function of data cross-clock domain is achieved. By accurately designing a delay path, cross-asynchronization can be realized only by a small number of delay cells, and the defect of large delay introduced by a traditional cross-asynchronization method can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a low-latency cross-asynchronous method and circuit based on chiplet interconnection direction. Background Art

[0002] The ‌Chiplet interconnection direction‌ refers to connecting multiple pre-manufactured chips (Chiplet) with specific functions together through advanced packaging technology to form a complete system. This technology is called chiplet interconnection technology. The core of the chiplet interconnection direction is to split the functions of a single SOC chip into multiple small chips, and then use advanced packaging technology (such as 2.5D / 3D / Fanout, etc.) to reassemble them into a large and complex system in one package, so as to reduce the total cost of the chip and improve the yield. At present, chiplet technology has been widely used in the field of computing power chips and has become the mainstream solution for computing power chips. International giants such as AMD, Intel and Nvidia are actively deploying chiplet technology and have launched related products. For example, AMD's Milan-X and A100 / H100, Intel Foveros, etc. all adopt chiplet solutions.

[0003] Multi-bit data cross-asynchronous transmission refers to the process of transmitting multi-bit data between different clock domains. In digital circuit design, different modules or components may run on different clock domains, which will cause timing problems during data transmission. In order to solve these problems, asynchronous FIFO (First In First Out) is usually used to implement cross-clock domain transmission of multi-bit data. Asynchronous FIFO uses read and write pointers to track the write and read positions of data. The write pointer moves in the write clock domain, and the read pointer moves in the read clock domain. When the write pointer and the read pointer are equal, it means that the FIFO is empty; when the write pointer exceeds the read pointer by one circle, it means that the FIFO is full. In this way, asynchronous FIFO is able to handle data transmission problems between different clock domains.

[0004] Traditionally, multi-bit data is asynchronously transmitted using Gray code. Addresses are transmitted between the source clock domain and the destination clock domain. During the transmission process, three beats are usually used to avoid metastable states. Combined with the beats of the source and destination clock domains, there is usually a delay of 5 beats. Figure 5The figure shows a general address cross-asynchronous transmission scenario. The method of using Gray code to achieve multi-bit cross-asynchronous transmission is relatively general and reliable, but for some specific application scenarios, there may be waste. For example, the following scenario: both the left and right sides are 100MHz, but the initial phase is different, which belongs to the scenario of same frequency but different phase. The clock deviation caused by the phase difference is only 1 clock cycle, but if Gray code is used, 5 clock cycles are required, and 4 cycles are wasted in the middle. For the application scenario of the same frequency but different phase, clock synchronization is also required. The actual difference between the two clock domains of the same frequency but different phase is at most one clock cycle, but if the traditional Gray code method is used, there will be a huge delay waste. Summary of the invention

[0005] The purpose of the present invention is to provide a low-latency cross-asynchronous method and circuit based on the chiplet interconnection direction. The method pre-evaluates the absolute values ​​of write delay and read delay according to the source clock frequency and the destination clock frequency, uses delay cells to design the delay path in the source clock direction and the delay path in the destination clock direction, and controls the order of the switch to start the source clock and the destination clock operation to ensure that writing starts before reading, thereby realizing the data cross-clock domain function. By accurately designing the delay path, cross-asynchronous can be achieved with only a small number of delay cells, which can greatly reduce the large delay disadvantage introduced by the traditional cross-asynchronous method.

[0006] A low-latency cross-asynchronous method based on chiplet interconnection direction, including: Determine the delay of the destination operation and the source operation; Delivering the delayed signal to the destination operation and the source operation according to the delay condition; The destination operation and the source operation write and read data according to the delay signal.

[0007] Preferably, before determining the delay of the destination operation and the source operation, the method further includes: A 1-bit enable signal is set, and the enable signal is used to control the start time of both the reading and writing sides.

[0008] Preferably, the determining of the delay of the destination operation and the source operation includes: A 2-bit delay selection signal is set, and the delay selection signal is used to determine whether the delay of the destination operation is greater than that of the source operation by a certain number of beats, and adjust the delay of the destination operation according to whether the delay of the destination operation is greater than that of the source operation by a certain number of beats.

[0009] Preferably, the setting of a 1-bit enable signal, wherein the enable signal is used to control the start time of both the reading and writing sides, includes: When the clocks of the destination operation and the source operation are stable, the enable signal is pulled high, and the enable signal is transmitted to the source operation and the destination operation respectively through different delay paths.

[0010] Preferably, the destination operation and the source operation write and read data according to the delay signal include: Setting the initial value of the delay selection signal according to the delay situation; If the delay difference is 1 beat, the value of the delay selection signal is set to 0; If the delay difference is 2 beats, the value of the delay selection signal is set to 1; If the delay difference is 3 beats, the value of the delay selection signal is set to 2.

[0011] A low-latency cross-asynchronous circuit based on the chiplet interconnection direction is applied to a low-latency cross-asynchronous method based on the chiplet interconnection direction, including: a precise delay circuit; The precise delay circuit is connected to the source clock domain and the destination clock domain, and is used to precisely control the enable delay lengths of the source clock domain and the destination clock domain, so that the delay length of the destination clock domain is greater than the delay length of the source clock domain.

[0012] Preferably, the precise delay circuit comprises: a plurality of delay units, a plurality of selectors and a plurality of latches; The output end of the delay unit is connected to the input end of the selector, and is used to delay the clock signal; The input end of the selector is connected to the latch and is used to output a delay signal; The latch is used to generate a control input code of the selector.

[0013] Preferably, each delay unit controls a 1-beat delay difference.

[0014] An electronic device includes: a chip, a processor and a memory, wherein the memory is used to store computer program code, the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a low-latency cross-asynchronous method based on the chiplet interconnection direction.

[0015] A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor of an electronic device, the processor implements a low-latency cross-asynchronous method based on a chiplet interconnection direction.

[0016] The beneficial effects of the present invention are: 1. The present invention ensures writing before reading by accurately designing the delay of the source clock and the destination clock domain, thereby realizing cross-asynchrony of the same-frequency but different-phase clocks; 2. The present invention can adapt to different cross-asynchronous application scenarios by introducing a delay difference threshold. The cross-asynchronous operation of different actual frequencies can also adopt this solution, as long as the source clock and the destination clock are the same source clock. The delay path of the source clock and the destination clock can be adjusted according to the proportional relationship between the source clock and the destination clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] Figure 1 This is a schematic diagram of a low-latency cross-asynchronous circuit structure based on chiplet interconnection direction of the present invention; Figure 2 This is a flow chart of a low-latency cross-asynchronous method based on chiplet interconnection direction of the present invention; Figure 3 It is a schematic diagram of the structure of the precise delay circuit of the present invention; Figure 4 A schematic diagram of the hardware structure of an electronic device of the present invention; Figure 5 It is a schematic diagram of a universal address cross-asynchronous transmission scenario of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0022] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0023] Traditionally, multi-bit data is asynchronously transmitted using Gray code. Addresses are transmitted between the source clock domain and the destination clock domain. During the transmission process, three beats are usually used to avoid metastable states. Combined with the beats of the source and destination clock domains, there is usually a delay of 5 beats. Figure 5 The figure shows a general address cross-asynchronous transmission scenario. The method of using Gray code to achieve multi-bit cross-asynchronous transmission is relatively general and reliable, but for some specific application scenarios, there may be waste. For example, the following scenario: both the left and right sides are 100MHz, but the initial phase is different, which belongs to the scenario of same frequency but different phase. The clock deviation caused by the phase difference is only 1 clock cycle, but if Gray code is used, 5 clock cycles are required, and 4 cycles are wasted in the middle. For the application scenario of the same frequency but different phase, clock synchronization is also required. The actual difference between the two clock domains of the same frequency but different phase is at most one clock cycle, but if the traditional Gray code method is used, there will be a huge delay waste.

[0024] The present invention ensures writing before reading by accurately designing the delay of the source clock and the destination clock domain, thereby realizing cross-asynchrony by clocks of the same frequency but different phases; the present invention can adapt to different cross-asynchronous application scenarios by introducing a delay difference threshold. The cross-asynchronous operation of different actual frequencies can also adopt this solution, as long as the source clock and the destination clock are the same source clock. The delay path of the source clock and the destination clock is adjusted according to the proportional relationship between the source clock and the destination clock.

[0025] Example 1 A low-latency cross-asynchronous method based on chiplet interconnection direction, reference Figure 2 , including the steps of: Step S100, determining the delay of the destination operation and the source operation; In the embodiment of the present invention, the source operation is write and the destination operation is read for example. In fact, the present invention is not limited to this operation. Any other cross-asynchronous scenarios that meet the same frequency and different phases can be applicable to the present device and method. It is only necessary to make corresponding adjustments to the specific operations. The ideas and principles are exactly the same. The destination operation refers to the location where the data is ultimately stored during the execution of computer instructions. The source operation refers to an operation in an application instruction whose content does not change with the execution of the instruction. The source operation is used to provide the data required for the operation. Judging the delay of the destination operation and the source operation is used to accurately adjust the delay.

[0026] Step S200, transmitting the delayed signal to the destination operation and the source operation according to the delay situation; A delayed signal refers to an artificial delay in the arrival time of a signal during signal transmission. By adjusting the delay time of the signal, different effects and applications can be achieved. The principle of a delayed signal is based on the delay characteristics of signal transmission and can be implemented by an analog circuit or a digital signal processor. In an embodiment of the present invention, the delay condition indicates how much greater the delay on the read side is than the delay on the write side. The delay conditions include: 1 beat, 2 beats, and 3 beats. The system with a delay difference of 1 beat has the best performance.

[0027] Step S300: The destination operation and the source operation write and read data according to the delay signal.

[0028] When the write-side clock samples the enable signal, the data is written. The write operation is performed after receiving the enable signal. The present invention makes the read and write clocks independent, the write clock controls the writing of data, and the read clock controls the reading of data. When the write-side clock samples the enable signal, it means that the data can be written safely, because the read clock has not been triggered at this time, and the data will not be overwritten or read incorrectly. In the FIFO (First-In-First-Out) storage structure, data is stored in the order of writing. If the clock is read first and then written, the newly written data may overwrite the old data, thereby losing information. Therefore, in order to ensure the integrity and sequence of the data, the clock must be written first and then read. Ensure data consistency. In a multi-tasking or parallel processing system, writing the clock first and then reading the clock can ensure that all data is the latest when reading data, avoiding conflicts and data inconsistencies caused by concurrent reading and writing. By controlling the order of the clocks, the integrity and consistency of the data can be guaranteed. Avoid read-write conflicts. In a synchronous FIFO, read and write operations must be triggered on the same clock edge, so that read-write conflicts can be avoided. If the read and write clocks are inconsistent, the read and write pointers may be misaligned, which may lead to data errors or loss. The present invention can simplify the design of the system by controlling the order of the read and write clocks. In an asynchronous FIFO, the read and write clocks are inconsistent, and the read and write operations are independent of each other, which can better adapt to different read and write requirements and improve the flexibility and reliability of the system.

[0029] When the read side clock samples the enable signal, the data is read out. During the data transmission process, the read side clock triggers the data reading operation after receiving the enable signal. This mechanism is usually used to ensure the accuracy and reliability of data transmission.

[0030] Preferably, before step S100, determining the delay of the destination operation and the source operation, the process further includes: Set a 1-bit enable signal, which is used to control the start time of both the read and write sides.

[0031] The Enable Signal is a control signal used to start or stop the operation of a function or device. In data transmission, the function of the Enable Signal is to tell the read side clock when to start reading data to ensure the synchronization and accuracy of data transmission. When the read side clock samples the Enable Signal, it triggers the data read operation. This mechanism ensures that data is read only when the Enable Signal is valid, thereby avoiding unnecessary read operations, reducing resource waste and potential errors. This mechanism is widely used in various communication and data transmission systems, especially in scenarios that require high reliability and synchronization. For example, in a communication system, the Enable Signal can ensure that data is read and transmitted only after receiving the correct control signal, thereby ensuring the integrity and synchronization of the data. A 1-bit Enable Signal refers to a signal whose value is 1 or 0. In an embodiment of the present invention, a 1-bit Enable Signal is used to control the start time of both the read and write sides. When the read side receives the Enable Signal, it starts to read the data, and when the write side receives the Enable Signal, it starts to write the data.

[0032] Preferably, step S100, determining the delay of the destination operation and the source operation includes: A 2-bit delay selection signal is set. The delay selection signal is used to determine whether the delay of the destination operation is a few beats greater than that of the source operation. The delay of the destination operation is adjusted according to whether the delay of the destination operation is a few beats greater than that of the source operation.

[0033] Delay signals are used to control the timing of signal occurrence, adjust the rate of signal transmission, and achieve specific functional requirements. In circuit design, delay signals can be used to control the delay of clock signals. Delay signals can also be used to adjust the transmission speed of signals to ensure the stability of signals during transmission. If the signal is transmitted too fast, it may cause signal distortion or loss; if the transmission is too slow, it will affect the response speed of the system. By setting the delay reasonably, the signal transmission speed and system performance can be effectively balanced.

[0034] ‌2-bits delay selection signal‌ usually refers to a signal with two delay options, which is used to control or select different delay paths. This signal is often used in digital circuit design to implement signal delay control to meet specific timing requirements or solve problems in signal transmission. The delay selection signal usually consists of two bits, each bit represents a delay option. By setting different combinations of these two bits, different delay paths can be selected to achieve control of signal delay. For example, 00, 01, 10, and 11 represent different delay settings, and the specific delay time depends on the circuit design.

[0035] Preferably, a 1-bit enable signal is set, and the enable signal is used to control the start time of both the reading and writing sides, including: When the clocks of the destination operation and the source operation are stable, the enable signal is pulled high, and the enable signal is transmitted to the source operation and the destination operation respectively through different delay paths.

[0036] The functions of enable signals in circuits include: Controlling data storage: In digital circuits, enable signals can control the storage of data. Data is written to or read from the memory only when the enable signal is true. Controlling timing: Enable signals can control timing to ensure that other signals are valid within a specified time period. For example, in a communication system, enable signals can control the time when data is sent and received. Controlling registers and state machines: In a microprocessor, enable signals are used to control the writing and reading of registers, and can also control the transfer of state machines.

[0037] In an embodiment of the present invention, the main function of the enable signal is to control the start time of both the read and write sides, ensuring that the write side starts first and the read side starts later, that is, ensuring that the source operation starts first and the destination operation starts later, and the time interval between the source operation and the destination operation is no more than 1 clock cycle.

[0038] Preferably, in step S300, the destination operation and the source operation write and read data according to the delay signal, including: Set the initial value of the delay selection signal according to the delay situation; If the delay difference is 1 beat, the value of the delay selection signal is set to 0; If the delay difference is 2 beats, the value of the delay selection signal is set to 1; If the delay difference is 3 beats, the value of the delay selection signal is set to 2.

[0039] Skew refers to the time difference between different signal paths during signal transmission. In circuit design, a large skew will cause the circuit timing to not meet the requirements, thus affecting the performance and stability of the product. Therefore, in the present invention, the delay difference between the write clock domain and the read clock domain is not large, at most three beats, so the clock signal needs to be accurately adjusted, which requires sampling of the precise delay circuit, and adjusting the delay selection signal according to the delay situation, among which a 1-beat delay difference has the best performance.

[0040] Example 2 A low-latency asynchronous circuit based on chiplet interconnection direction, reference Figure 1 ,applied to a low-latency cross-asynchronous method based on the chiplet interconnection direction,,including: precise delay circuit; The precise delay circuit is connected to the source clock domain and the destination clock domain, and is used to precisely control the enable delay lengths of the source clock domain and the destination clock domain, so that the delay length of the destination clock domain is greater than the delay length of the source clock domain.

[0041] A precision delay circuit is an electronic circuit that can delay the change of a signal within a specified time, thereby extending the duration of the signal. Precision delay circuits are used to control the delay time of a signal to ensure that the device operates at the set time interval. Common precision delay circuits include RC delay circuits, master-slave JK trigger delay circuits, counter delay circuits, monostable trigger delay circuits, digital logic delay circuits, and microprocessor delay circuits. These circuits achieve precise delay functions through different working principles. For example, the RC delay circuit controls the delay time of the output signal through a combination of capacitors and resistors.

[0042] Preferably, reference Figure 3 ,The precise delay circuit includes: a plurality of delay units, a plurality of selectors and a plurality of latches; The output end of the delay unit is connected to the input end of the selector to delay the clock signal; The input end of the selector is connected to the latch for outputting a delay signal; The latch is used to generate the control input code of the selector.

[0043] The methods for implementing signal time delay can be roughly divided into three categories: Software method: Using programming to implement delay, although it is simple, but in order to determine the delay time, it is necessary to calculate the instruction cycle, which may lead to inaccurate delay time and increase the workload beyond programming. Hardware method: Using triggers or registers and counters composed of triggers and control gates can achieve the required delay, but when more delay time is required, the circuit will become relatively large.

[0044] In the embodiment of the present invention, there are mainly three cases of delay difference. In the first case, the delay difference is 1 beat, in the second case, the delay difference is 2 beats, and in the third case, the delay difference is 3 beats. Therefore, in order to simplify the circuit design process and accurately control the delay, the present invention designs a precise delay circuit. In order to perform three kinds of delay control on the clock signal, the present invention designs a chain circuit, so that the delay time can be increased in sequence, and the last chain is a three-beat delay. In the embodiment of the present invention, the selector and the latch are both programmable integrated circuits. The selector corresponds to different signal inputs and outputs according to different control codes, thereby selecting different delayed output signals. The selector is used to select the required time delay, and the function of the latch is to generate the control input code of the selector, thereby controlling the output signal of the selector, and maintaining this signal until another signal is selected. The output code of the latch is determined by its precision input signal, which can be controlled and determined by the program. For example, if a one-beat delay is required in the circuit, the value of the delay selection signal is 0. When the latch receives the delay selection signal, the latch sends the first control code to the selector. Then, when the clock signal passes through the first delay unit, the selector directly selects the clock signal output and turns off the switch of the subsequent chain circuit. If a two-beat delay is required in the circuit, the value of the delay selection signal is 1. When the latch receives the delay selection signal, the latch sends the second control code to the selector. Then, when the clock signal passes through the first delay unit, the selector selects the clock signal to be output to the next delay unit and turns off the output switch. Then, when the clock signal passes through the second delay unit, the second selector selects to output the clock signal to the outside and turns off the switch of the subsequent chain circuit. If a 3-beat delay is required in the circuit, the value of the delay selection signal is 2. When the latch receives the delay selection signal, the latch sends the third control code to the selector. Then, when the clock signal passes through the first delay unit, the selector selects the clock signal to be output to the next delay unit and turns off the output switch. Then, when the clock signal passes through the second delay unit, the second selector selects the clock signal to be output to the next delay unit and turns off the output switch. Then the clock signal reaches the third delay unit and is finally output as a three-beat delay signal.

[0045] Preferably, each delay unit controls a 1-beat delay difference.

[0046] The main function of adjusting the delay circuit to a 1-beat delay difference is to ensure that the signal can be correctly sampled and processed when the clock edge arrives. In sequential logic, the 1-beat delay difference of the delay circuit means that the signal remains unchanged within one clock cycle before the rising edge of the clock arrives. This design can shield the burrs in the signal and ensure that the data collected when the clock edge arrives is stable, thereby improving the reliability of the data in the circuit. The precise delay circuit controls the time output of the signal by connecting certain circuit devices between the input and output or using delay elements. This design allows the signal to be delayed within a specified time period and eventually output from the delay element. The delay unit consists of an oscillator, a feedback element, an amplifier, and an output element. The time interval for the signal to pass through the element is extended by amplification and other means, and then continues to the next level of delay unit.

[0047] In order to facilitate the control of the delay difference and to make the circuit simpler, in an embodiment of the present invention, each delay unit is set to control a 1-beat delay difference, and the same delay difference is set. When an error occurs in the circuit, it is easier to determine which component has a problem, which facilitates maintenance. If the 1-beat delay, 2-beat delay and 3-beat delay in the circuit are not accurate, it means that an error has occurred in the first delay unit. If the 1-beat delay in the circuit is accurate, and the 2-beat delay and the 3-beat delay are not accurate, it means that an error has occurred in the second delay unit. If the 1-beat delay in the circuit is accurate, the 2-beat delay is accurate, but the 3-beat delay is accurate, it means that an error has occurred in the third delay unit. According to the above method, it is possible to accurately determine which delay unit in the circuit has an error through the delay situation for maintenance, and a fixed delay difference can make the circuit more stable and avoid inaccurate delays due to environmental interference and signal interference.

[0048] Example 3 An electronic device includes: a chip, a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a low-latency cross-asynchronous method based on the chiplet interconnection direction.

[0049] refer to Figure 4 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0050] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0051] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0052] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0053] Example 4 A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor implements a low-latency cross-asynchronous method based on a chiplet interconnection direction.

[0054] The present invention ensures writing before reading by accurately designing the delay of the source clock and the destination clock domain, thereby realizing cross-asynchrony by clocks of the same frequency but different phases; the present invention can adapt to different cross-asynchronous application scenarios by introducing a delay difference threshold. The cross-asynchronous operation of different actual frequencies can also adopt this solution, as long as the source clock and the destination clock are the same source clock. The delay path of the source clock and the destination clock is adjusted according to the proportional relationship between the source clock and the destination clock.

[0055] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A low-latency cross-asynchronous method based on chiplet interconnection direction, characterized in that: include: Determine the delay of the destination operation and the source operation; Delivering the delayed signal to the destination operation and the source operation according to the delay condition; The destination operation and the source operation write and read data according to the delay signal.

2. According to claim 1, a low-latency cross-asynchronous method based on chiplet interconnection direction is characterized in that: Before determining the delay of the destination operation and the source operation, the method further includes: A 1-bit enable signal is set, and the enable signal is used to control the start time of both the reading and writing sides.

3. According to claim 1, a low-latency cross-asynchronous method based on chiplet interconnection direction is characterized in that: The delay of determining the destination operation and the source operation includes: A 2-bit delay selection signal is set, and the delay selection signal is used to determine whether the delay of the destination operation is greater than that of the source operation by a certain number of beats, and adjust the delay of the destination operation according to whether the delay of the destination operation is greater than that of the source operation by a certain number of beats.

4. According to claim 2, a low-latency cross-asynchronous method based on chiplet interconnection direction is characterized in that: The setting of a 1-bit enable signal, wherein the enable signal is used to control the start time of both the reading and writing sides, includes: When the clocks of the destination operation and the source operation are stable, the enable signal is pulled high, and the enable signal is transmitted to the source operation and the destination operation respectively through different delay paths.

5. According to claim 3, a low-latency cross-asynchronous method based on chiplet interconnection direction is characterized in that: The destination operation and the source operation write and read data according to the delay signal, including: Setting the initial value of the delay selection signal according to the delay situation; If the delay difference is 1 beat, the value of the delay selection signal is set to 0; If the delay difference is 2 beats, the value of the delay selection signal is set to 1; If the delay difference is 3 beats, the value of the delay selection signal is set to 2.

6. A low-latency cross-asynchronous circuit based on chiplet interconnection direction, applied to a low-latency cross-asynchronous method based on chiplet interconnection direction according to any one of claims 1 to 5, characterized in that: include: Precision delay circuit; The precise delay circuit is connected to the source clock domain and the destination clock domain, and is used to precisely control the enable delay lengths of the source clock domain and the destination clock domain, so that the delay length of the destination clock domain is greater than the delay length of the source clock domain.

7. The low-latency asynchronous circuit based on chiplet interconnection direction according to claim 6, characterized in that: The precise delay circuit comprises: a plurality of delay units, a plurality of selectors and a plurality of latches; The output end of the delay unit is connected to the input end of the selector, and is used to delay the clock signal; The input end of the selector is connected to the latch and is used to output a delay signal; The latch is used to generate a control input code of the selector.

8. The low-latency asynchronous circuit based on chiplet interconnection direction according to claim 7, characterized in that: Each delay unit controls 1 beat of delay difference.

9. An electronic device, characterized in that: include: A chip, a processor, and a memory, wherein the memory is used to store a computer program code, wherein the computer program code includes a computer instruction, and when the chip executes the computer instruction, the electronic device executes a low-latency cross-asynchronous method based on a chiplet interconnection direction as claimed in any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor of an electronic device, the processor executes a low-latency cross-asynchronous method based on a chiplet interconnection direction according to any one of claims 1 to 5.

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