Ethernet packet sending and receiving method and device, storage medium and electronic equipment

Abstract

The invention discloses an Ethernet packet sending and receiving method and device, a storage medium and electronic equipment, and the method comprises the steps: analyzing a user instruction through a CPU control end, and if the user instruction is a packet receiving control instruction, printing the packet receiving control instruction, and storing the packet receiving control instruction in a local file to generate a control message; if the user instruction is a packet sending control instruction or a flow query instruction, directly generating a control message according to the packet sending control instruction or the flow query instruction; the CPU control end sends the generated control message to the FPGA control end for analysis; if the control message is a packet receiving control instruction, the message entering from an external Ethernet port is filtered according to a two-layer protocol type and then is sent to the CPU control end; if the instruction is a flow query instruction, the counted number of received and transmitted messages of the Ethernet interface is fed back to the CPU control end according to a communication protocol; and if the control command is a packet sending control command, feeding back a response message corresponding to the packet sending control command to the CPU control end. According to the invention, the problems of inconvenience in Ethernet packet sending and receiving and influence on the test effect in the prior art are solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of Ethernet, and in particular relates to an Ethernet packet sending and receiving method, device, storage medium and electronic equipment. Background Art

[0002] Ethernet packet sending and receiving tests can evaluate and verify the performance and functions of Ethernet networks, ensuring their stability and reliability in practical applications.

[0003] At present, in the development, testing and use of network equipment, it is often necessary to use test equipment to test the packet sending and receiving of the device under test. Common test equipment includes: professional network testers, computers with packet sending and receiving software installed, etc. Professional network testers are expensive, large in size and not easy to carry, while computers with packet sending and receiving software installed have low flexibility, and the operating system and software running on the computer will send miscellaneous packets in the background, affecting the test. Summary of the invention

[0004] To this end, the present invention provides an Ethernet packet sending and receiving method, device, storage medium and electronic device to solve the problem that the Ethernet packet sending and receiving inconvenience exists in the traditional technology, which affects the test effect.

[0005] In order to achieve the above object, the present invention provides the following technical solutions: In a first aspect, an Ethernet packet sending and receiving method is provided, comprising:

[0006] The CPU control terminal receives user commands input by the user through the USB to serial port;

[0007] The CPU control end parses the user instruction and determines the type of the user instruction:

[0008] a1) if the user instruction is a packet receiving control instruction, print the packet receiving control instruction and save it in a local file, and then generate a control message;

[0009] a2) if the user instruction is a packet control instruction or a flow query instruction, directly generating a control message according to the packet control instruction or the flow query instruction;

[0010] The CPU control end sends the generated control message to the FPGA control end, and the FPGA control end parses the control message:

[0011] b1) If the user instruction corresponding to the control message is a packet receiving control instruction, the FPGA control end filters the message coming from the external Ethernet port according to the layer 2 protocol type according to the control message protocol content and sends it to the CPU control end;

[0012] b2) If the user instruction corresponding to the control message is a flow query instruction, the FPGA control end feeds back the number of messages sent and received by the Ethernet interface to the CPU control end according to the communication protocol;

[0013] b3) If the user instruction corresponding to the control message is a packet sending control instruction, a response message corresponding to the packet sending control command is fed back to the CPU control end.

[0014] As a preferred solution of the Ethernet packet sending and receiving method, it also includes: resetting the CPU control end after powering on to initialize the operating parameters and network interface of the CPU control end;

[0015] The FPGA control end is powered on and reset to initialize the operating parameters and network interface of the FPGA control end.

[0016] As a preferred solution of the Ethernet packet sending and receiving method, it also includes: if the user instruction corresponding to the control message is a packet receiving control instruction, setting or clearing a layer 2 protocol type whitelist according to the control message protocol content.

[0017] As a preferred solution of the Ethernet packet sending and receiving method, if the user instruction corresponding to the control message is a packet sending control instruction, after feeding back the response message corresponding to the packet sending control command to the CPU control end, it also includes:

[0018] According to the content of the control message protocol, a network message is generated according to the protocol preset rules, and sent to the external Ethernet port according to the protocol preset bandwidth;

[0019] Determine whether the waiting message sending reaches the threshold specified by the control message protocol. If the waiting message sending reaches the threshold specified by the control message protocol, stop sending packets.

[0020] In a second aspect, an Ethernet packet sending and receiving device is provided, comprising:

[0021] User command input module, used for the CPU control end to receive user commands input by the user through the USB to serial port;

[0022] The first user instruction parsing module is used for the CPU control end to parse the user instruction and determine the type of the user instruction:

[0023] a1) if the user instruction is a packet receiving control instruction, print the packet receiving control instruction and save it in a local file, and then generate a control message;

[0024] a2) if the user instruction is a packet control instruction or a flow query instruction, directly generating a control message according to the packet control instruction or the flow query instruction;

[0025] A control message sending module is used for the CPU control end to send the generated control message to the FPGA control end;

[0026] The second user instruction parsing module is used for the FPGA control end to parse the control message:

[0027] b1) If the user instruction corresponding to the control message is a packet receiving control instruction, the FPGA control end filters the message coming from the external Ethernet port according to the layer 2 protocol type according to the control message protocol content and sends it to the CPU control end;

[0028] b2) If the user instruction corresponding to the control message is a flow query instruction, the FPGA control end feeds back the number of messages sent and received by the Ethernet interface to the CPU control end according to the communication protocol;

[0029] b3) If the user instruction corresponding to the control message is a packet sending control instruction, a response message corresponding to the packet sending control command is fed back to the CPU control end.

[0030] As a preferred solution of the Ethernet packet sending and receiving device, it also includes:

[0031] A CPU reset module, used to reset the CPU control end after powering on, so as to initialize the operating parameters and network interface of the CPU control end;

[0032] The FPGA reset module is used to reset the FPGA control end after powering on, so as to initialize the operating parameters and network interface of the FPGA control end.

[0033] As a preferred solution for the Ethernet packet sending and receiving device, the second user instruction parsing module is also used to set or clear the layer 2 protocol type whitelist according to the control message protocol content if the user instruction corresponding to the control message is a packet receiving control instruction.

[0034] As a preferred solution of the Ethernet packet sending and receiving device, it also includes:

[0035] The network message generation module is used to generate network messages according to the protocol content of the control message and the protocol preset rules, and send them to the external Ethernet port according to the protocol preset bandwidth;

[0036] The message sending waiting analysis module is used to determine whether the waiting message sending reaches the specified threshold of the control message protocol. If the waiting message sending reaches the specified threshold of the control message protocol, the packet sending is stopped.

[0037] In a third aspect, an electronic device is provided, comprising: a memory and a processor; the processor and the memory communicate with each other via a bus; the memory stores program instructions executable by the processor, and the processor calls the program instructions to execute an Ethernet packet sending and receiving method according to the first aspect or any possible implementation thereof.

[0038] In a fourth aspect, a non-transitory computer-readable storage medium is provided, wherein the computer-readable storage medium stores a program code for an Ethernet packet sending and receiving method, wherein the program code includes instructions for executing an Ethernet packet sending and receiving method according to the first aspect or any possible implementation thereof.

[0039] The beneficial effects of the present invention are as follows: by adopting the idea of ​​division of labor and cooperation between FPGA and CPU, it is possible to realize the functions of sending packets at a specified rate, capturing packets with a specified protocol, and traffic statistics of network messages of any content; by using CPU as a control end, sending control messages to FPGA, and FPGA then sending specified messages to an external Ethernet port, uploading messages of a specified type to CPU, and returning traffic statistics results of the Ethernet interface to CPU according to instructions in the control messages, it is possible to help testers to quickly and efficiently complete the packet sending and receiving test; the content of each byte of the sent message can be customized, and any byte of each sent message can also be sent according to a specified rule, which greatly improves the flexibility of packet sending; FPGA can be used as a channel, and CPU can realize intercommunication with the second and third layers of the tested end through FPGA as an independent network device in a network environment; the purity of data is ensured, and data that is not concerned with or not allowed to pass in the test is filtered; the FPGA hardware implementation method can achieve a forwarding delay of microseconds, and can realize and adapt to the bandwidth requirements of various external high-speed interfaces; relying on the parallel processing capability of FPGA, it is convenient to realize the simultaneous sending and receiving of multiple interfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the drawings required for the implementation methods or the prior art descriptions are briefly introduced below. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0041] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantial technical significance. Any structural modification, change in proportion or adjustment of size shall still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0042] Figure 1 The application scenario architecture of the Ethernet packet sending and receiving method provided by the embodiment of the present invention;

[0043] Figure 2 A schematic diagram of the processing flow of the CPU control end in the Ethernet packet sending and receiving method provided in an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of the processing flow of the FPGA control end in the Ethernet packet sending and receiving method provided in an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of the architecture of an Ethernet packet sending and receiving device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following is a description of the implementation of the present invention by specific embodiments. People familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] Example 1

[0048] See also Figure 1 The system architecture of the Ethernet packet sending and receiving method application scenario provided in the embodiment of the present invention is as follows:

[0049] A001: USB to serial port. Users use the USB to serial port to log in to the CPU and operate the CPU software.

[0050] A002: CPU control terminal, connected to A001 through the serial port to realize the user interface. It realizes the network connection with the FPGA control terminal A003 through the MAC controller to realize the control message sending to the FPGA control terminal.

[0051] A003: FPGA control end: realizes network connection with CPU control end A002 through MAC controller to realize control interface. It realizes external Ethernet communication through MAC controller and external PHY chip connection.

[0052] A004: PHY chip, realizing external Ethernet communication.

[0053] A005: Ethernet interface, interface for sending and receiving packets.

[0054] See also Figure 2 and Figure 3Based on the above application scenario, Embodiment 1 of the present invention provides an Ethernet packet sending and receiving method, comprising the following steps:

[0055] CPU control end processing flow:

[0056] S001: After the CPU control end is powered on, reset is completed, the operating parameters and network interface are initialized, and the FPGA control end A003 is configured. The next step is to go to S002;

[0057] S002: The CPU control end receives the user command input from the USB to serial port A001, and the next step goes to S003;

[0058] S003: The CPU control end parses the user instruction and determines the type of the user instruction. If the user instruction is a packet receiving control instruction, the process goes to step S004; otherwise, if it is a packet sending control instruction or a traffic query instruction, the process goes to step S005.

[0059] S004: Print the packet receiving control instruction and save it in a local file, and then generate a control message;

[0060] S005: directly generating a control message according to the packet sending control instruction or the traffic query instruction;

[0061] S006: Determine whether the CPU control end has received the feedback packet from the FPGA control end. If the CPU control end has received the feedback packet from the FPGA control end, go to step S002; if the CPU control end has not received the feedback packet from the FPGA control end, it is in a waiting state.

[0062] FPGA control end processing flow:

[0063] S101: After the FPGA control end is powered on, reset is completed, and the network interface of the FPGA control end is initialized, and the next step is to go to S102;

[0064] S102: The FPGA control end receives the control message sent by the CPU control end, and the next step goes to S103;

[0065] S103: The FPGA control end parses the control message sent by the CPU control end. If it is a flow query instruction, the next step goes to S104; otherwise, if it is a packet sending control instruction, the next step goes to S105; if it is a packet receiving control instruction, the next step goes to S108.

[0066] S104: The FPGA control end feeds back the number of messages received and sent by the Ethernet interface according to the communication protocol to the CPU control end, and the next step goes to S102;

[0067] S105: The FPGA control end feeds back the response message corresponding to the packet control instruction to the CPU control end, and the next step jumps to S106;

[0068] S106: The FPGA control end generates a network message according to the protocol content of the control message and the protocol preset rules, and sends it to the external Ethernet port according to the protocol preset bandwidth, and then jumps to S107;

[0069] S107: Determine whether the FPGA control end waits for the message to be sent to reach the specified threshold of the control message protocol. If the FPGA control end waits for the message to be sent to reach the specified threshold of the control message protocol, stop sending packets, and jump to S102 in the next step.

[0070] S108: The FPGA control end sets or clears the layer 2 protocol type whitelist according to the content of the control message protocol. All messages coming from the external Ethernet port will be filtered according to the layer 2 protocol type and sent to the CPU control end. The next step goes to S102.

[0071] The present invention realizes network packet sending and receiving based on the cooperation of FPGA and CPU, and adopts the idea of ​​division of labor and cooperation between FPGA and CPU. Among them, the CPU control end undertakes the processes such as initializing FPGA control end configuration, user interface implementation, and message encapsulation; the FPGA control end undertakes the functions such as message analysis, message generation, traffic statistics, and message sending.

[0072] Among them, CPU and FPGA are used as the control end, and the external interface is only USB interface and RJ45 interface, which can easily be made into a matchbox size, increasing ease of use and portability. The CPU performance requirements are very low, suitable for low-power scenarios. The USB interface is not only the control serial port access channel, but also the power supply interface.

[0073] Similar to the Ethernet interface, only by increasing the types of physical interfaces and protocol types, with the help of FPGA's convenient interface expansion and protocol simulation capabilities, common interfaces such as RS232, IIC, SPI, sgmii, aurura, lvds, and even custom interface types can be expanded. The implementation method is the same as below, providing test incentives and methods for various electronic communication equipment. The FPGA control end is implemented as an interface, connected in series between the CPU control end and the external interface. The data is forwarded using a custom protocol. All network protocols or other protocols are encapsulated / decapsulated by the FPGA control end and then isolated and forwarded, ensuring the purity of the data and filtering out data that the test does not care about or does not allow to pass.

[0074] Among them, the hardware implementation of the FPGA control end can achieve a forwarding delay of microseconds. It can realize and adapt to the bandwidth requirements of various external high-speed interfaces. When the application system contains multiple test interfaces, relying on the parallel processing capability of FPGA, it is convenient to realize the simultaneous transmission and reception of multiple interfaces.

[0075] In summary, the CPU control end of the present invention receives a user instruction input by a user through a USB to serial port; the CPU control end parses the user instruction and determines the type of the user instruction: a1) if the user instruction is a packet receiving control instruction, the packet receiving control instruction is printed and stored in a local file, and then a control message is generated; a2) if the user instruction is a packet sending control instruction or a flow query instruction, a control message is directly generated according to the packet sending control instruction or the flow query instruction; the CPU control end sends the generated control message to the FPGA control end, and the FPGA control end parses the control message: b1) if the user instruction corresponding to the control message is a packet receiving control instruction, the FPGA control end filters the message coming in from the external Ethernet port according to the layer 2 protocol type according to the control message protocol content and sends it to the CPU control end; b2) if the user instruction corresponding to the control message is a flow query instruction, the FPGA control end feeds back the counted number of messages sent and received by the Ethernet interface to the CPU control end according to the communication protocol; b3) if the user instruction corresponding to the control message is a packet sending control instruction, the response message corresponding to the packet sending control command is fed back to the CPU control end. If the user instruction corresponding to the control message is a packet receiving control instruction, set or clear the layer 2 protocol type whitelist according to the control message protocol content. Generate a network message according to the protocol preset rules based on the control message protocol content, and send it to the external Ethernet port according to the protocol preset bandwidth; determine whether the waiting message sending reaches the control message protocol specified threshold, and stop sending packets if the waiting message sending reaches the control message protocol specified threshold. The present invention adopts the idea of ​​division of labor and cooperation between FPGA and CPU, and can realize the functions of sending packets at a specified rate, capturing packets with a specified protocol, and traffic statistics of network messages of any content; the CPU is used as a control end to send a control message to the FPGA, and the FPGA then sends a specified message to an external Ethernet port, uploads a message of a specified type to the CPU, and returns the traffic statistics result of the Ethernet interface to the CPU according to the instruction in the control message, so as to help testers quickly and efficiently complete the packet sending and receiving test; the content of each byte of the sent message can be customized, and any byte of each sent message can be sent according to a specified rule, which greatly improves the flexibility of packet sending; the FPGA can be used as a channel, and the CPU can realize the intercommunication of the second layer and the third layer with the tested end through the FPGA as an independent network device in the network environment; the purity of the data is guaranteed, and the data that the test does not care about or is not allowed to pass is filtered; the FPGA hardware implementation method can achieve a forwarding delay of microseconds, and can realize and adapt to the bandwidth requirements of various external high-speed interfaces; relying on the parallel processing capability of the FPGA, it is convenient to realize the simultaneous sending and receiving of multiple interfaces.

[0076] It should be noted that the method of the embodiment of the present disclosure can be performed by a single device, such as a computer or a server. The method of the present embodiment can also be applied in a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present disclosure, and the multiple devices will interact with each other to complete the described method.

[0077] It should be noted that the above describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0078] Example 2

[0079] See also Figure 4 Embodiment 2 of the present invention provides an Ethernet packet sending and receiving device, comprising:

[0080] The user command input module 100 is used for the CPU control end to receive the user command input by the user through the USB to serial port;

[0081] The first user instruction parsing module 200 is used for the CPU control end to parse the user instruction and determine the type of the user instruction:

[0082] a1) if the user instruction is a packet receiving control instruction, print the packet receiving control instruction and save it in a local file, and then generate a control message;

[0083] a2) if the user instruction is a packet control instruction or a flow query instruction, directly generating a control message according to the packet control instruction or the flow query instruction;

[0084] A control message sending module 300 is used for the CPU control end to send the generated control message to the FPGA control end;

[0085] The second user instruction parsing module 400 is used for the FPGA control end to parse the control message:

[0086] b1) If the user instruction corresponding to the control message is a packet receiving control instruction, the FPGA control end filters the message coming from the external Ethernet port according to the layer 2 protocol type according to the control message protocol content and sends it to the CPU control end;

[0087] b2) If the user instruction corresponding to the control message is a flow query instruction, the FPGA control end feeds back the number of messages sent and received by the Ethernet interface to the CPU control end according to the communication protocol;

[0088] b3) If the user instruction corresponding to the control message is a packet sending control instruction, a response message corresponding to the packet sending control command is fed back to the CPU control end.

[0089] In this embodiment, it also includes:

[0090] A CPU reset module 500, used to reset the CPU control terminal after powering on, so as to initialize the operating parameters and network interface of the CPU control terminal;

[0091] The FPGA reset module 600 is used to reset the FPGA control end after powering on, so as to initialize the operating parameters and network interface of the FPGA control end.

[0092] In this embodiment, the second user instruction parsing module 400 is further used to set or clear a layer 2 protocol type whitelist according to the protocol content of the control message if the user instruction corresponding to the control message is a packet receiving control instruction.

[0093] In this embodiment, it also includes:

[0094] The network message generation module 700 is used to generate a network message according to the protocol content of the control message and the protocol preset rules, and send it to the external Ethernet port according to the protocol preset bandwidth;

[0095] The message sending waiting analysis module 800 is used to determine whether the waiting message sending reaches the threshold specified by the control message protocol, and stop sending packets if the waiting message sending reaches the threshold specified by the control message protocol.

[0096] It should be noted that the information interaction, execution process and other contents between the units of the above-mentioned device are based on the same concept as the method embodiment in Example 1 of the present application, and the technical effects they bring are the same as those of the method embodiment of the present application. For specific contents, please refer to the description in the method embodiment shown in the previous part of the present application, and will not be repeated here.

[0097] Example 3

[0098] Embodiment 3 of the present invention provides a non-transitory computer-readable storage medium, in which a program code of an Ethernet packet sending and receiving method is stored, and the program code includes instructions for executing an Ethernet packet sending and receiving method of embodiment 1 or any possible implementation thereof.

[0099] The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0100] Example 4

[0101] Embodiment 4 of the present invention provides an electronic device, including: a memory and a processor;

[0102] The processor and the memory communicate with each other via a bus; the memory stores program instructions that can be executed by the processor, and the processor calls the program instructions to execute an Ethernet packet sending and receiving method of embodiment 1 or any possible implementation thereof.

[0103] Specifically, the processor can be implemented by hardware or by software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc.; when implemented by software, the processor can be a general-purpose processor implemented by reading software codes stored in a memory. The memory can be integrated in the processor or can be located outside the processor and exist independently.

[0104] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital consumer customer line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center.

[0105] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0106] Although the present invention has been described in detail above by general description and specific embodiments, it is obvious to those skilled in the art that some modifications or improvements can be made to the present invention. Therefore, these modifications or improvements made without departing from the spirit of the present invention all belong to the scope of protection claimed by the present invention.

Claims

1. An Ethernet packet sending and receiving method, characterized in that: include: The CPU control terminal receives user commands input by the user through the USB to serial port; The CPU control end parses the user instruction and determines the type of the user instruction: a1) if the user instruction is a packet receiving control instruction, print the packet receiving control instruction and save it in a local file, and then generate a control message; a2) if the user instruction is a packet control instruction or a flow query instruction, directly generating a control message according to the packet control instruction or the flow query instruction; The CPU control end sends the generated control message to the FPGA control end, and the FPGA control end parses the control message: b1) If the user instruction corresponding to the control message is a packet receiving control instruction, the FPGA control end filters the message coming from the external Ethernet port according to the layer 2 protocol type according to the control message protocol content and sends it to the CPU control end; b2) If the user instruction corresponding to the control message is a flow query instruction, the FPGA control end feeds back the number of messages sent and received by the Ethernet interface to the CPU control end according to the communication protocol; b3) If the user instruction corresponding to the control message is a packet sending control instruction, a response message corresponding to the packet sending control command is fed back to the CPU control end.

2. The Ethernet packet sending and receiving method according to claim 1, characterized in that: The method further includes resetting the CPU control end after powering on to initialize the operating parameters and network interface of the CPU control end; The FPGA control end is powered on and reset to initialize the operating parameters and network interface of the FPGA control end.

3. The Ethernet packet sending and receiving method according to claim 1, characterized in that: Also includes: If the user instruction corresponding to the control message is a packet receiving control instruction, a layer 2 protocol type whitelist is set or cleared according to the control message protocol content.

4. The Ethernet packet sending and receiving method according to claim 1, characterized in that: If the user instruction corresponding to the control message is a packet sending control instruction, after feeding back a response message corresponding to the packet sending control command to the CPU control end, the method further includes: According to the content of the control message protocol, a network message is generated according to the protocol preset rules, and sent to the external Ethernet port according to the protocol preset bandwidth; Determine whether the waiting message sending reaches the threshold specified by the control message protocol. If the waiting message sending reaches the threshold specified by the control message protocol, stop sending packets.

5. An Ethernet packet sending and receiving device, characterized in that: include: User command input module, used for the CPU control end to receive user commands input by the user through the USB to serial port; The first user instruction parsing module is used for the CPU control end to parse the user instruction and determine the type of the user instruction: a1) if the user instruction is a packet receiving control instruction, print the packet receiving control instruction and save it in a local file, and then generate a control message; a2) if the user instruction is a packet control instruction or a flow query instruction, directly generating a control message according to the packet control instruction or the flow query instruction; A control message sending module is used for the CPU control end to send the generated control message to the FPGA control end; The second user instruction parsing module is used for the FPGA control end to parse the control message: b1) If the user instruction corresponding to the control message is a packet receiving control instruction, the FPGA control end filters the message coming from the external Ethernet port according to the layer 2 protocol type according to the control message protocol content and sends it to the CPU control end; b2) If the user instruction corresponding to the control message is a flow query instruction, the FPGA control end feeds back the number of messages sent and received by the Ethernet interface to the CPU control end according to the communication protocol; b3) If the user instruction corresponding to the control message is a packet sending control instruction, a response message corresponding to the packet sending control command is fed back to the CPU control end.

6. The Ethernet packet sending and receiving device according to claim 5, characterized in that: Also includes: A CPU reset module, used to reset the CPU control end after powering on, so as to initialize the operating parameters and network interface of the CPU control end; The FPGA reset module is used to reset the FPGA control end after powering on, so as to initialize the operating parameters and network interface of the FPGA control end.

7. The Ethernet packet sending and receiving device according to claim 5, characterized in that: The second user instruction parsing module is further configured to, if the user instruction corresponding to the control message is a packet receiving control instruction, set or clear a layer 2 protocol type whitelist according to the control message protocol content.

8. The Ethernet packet sending and receiving device according to claim 5, characterized in that: Also includes: The network message generation module is used to generate network messages according to the protocol content of the control message and the protocol preset rules, and send them to the external Ethernet port according to the protocol preset bandwidth; The message sending waiting analysis module is used to determine whether the waiting message sending reaches the specified threshold of the control message protocol. If the waiting message sending reaches the specified threshold of the control message protocol, the packet sending is stopped.

9. An electronic device, comprising: Memory and processor; The processor and the memory communicate with each other via a bus; The memory stores program instructions that can be executed by the processor, and is characterized in that the processor calls the program instructions to execute an Ethernet packet sending and receiving method as described in any one of claims 1 to 4.

10. A non-transitory computer-readable storage medium, characterized in that: The computer-readable storage medium stores a program code of an Ethernet packet sending and receiving method, and the program code includes instructions for executing the Ethernet packet sending and receiving method according to any one of claims 1 to 4.

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