Semiconductor manufacturing method, semiconductor and electronic equipment
By bonding capacitor nanosheets with gate-around transistor device layers in a silicon-germanium superlattice structure during semiconductor manufacturing, the challenges of capacitor size reduction and high aspect ratio etching have been solved, thereby increasing capacitor capacity and reducing memory cell size, and improving storage density.
Patent Information
- Application Number
- CN202411547184.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-03-11
AI Technical Summary
In semiconductor manufacturing, as DRAM manufacturing with critical dimensions smaller than 15nm becomes more complex, capacitor size is difficult to shrink, and high aspect ratio etching processes present significant challenges, limiting the increase in memory cell density.
By cyclically epitaxial silicon layers and sacrificial layers in the vertical direction, a capacitor nanosheet layer with a silicon-germanium superlattice structure is formed, and then bonded to a gate-around transistor device layer to create a capacitor with a horizontally stacked structure, utilizing vertical space and adjusting capacitance.
This technology enables the reduction of memory cell size while increasing capacitor capacity, effectively utilizes vertical space, solves the challenges of high aspect ratio etching processes, and improves storage density.
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Figure CN119603964A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor manufacturing method, a semiconductor and an electronic device. Background Art
[0002] like Figure 1 As shown in Figure 1, dynamic random access memory (DRAM), with the high integration of semiconductors and the evolution of Moore's Law to the level below 20nm, requires the active area to be arranged more densely. Figure 2 As shown in the figure, as the size of the memory cell gets smaller and smaller, especially in the DRAM manufacturing process with a critical size less than 15nm, it is very difficult to shrink the size of the capacitor due to the physical principle of the capacitor, and trench capacitors are usually used. In addition, in order to maintain the capacitance of the capacitor, the aspect ratio needs to be increased while reducing the feature size, but this brings great challenges to the high aspect ratio etching process.
[0003] In summary, it is necessary to provide a semiconductor manufacturing method, a semiconductor and an electronic device that can reduce the size of a capacitor. Summary of the invention
[0004] To solve the above problems, the present application proposes a semiconductor manufacturing method, a semiconductor and an electronic device.
[0005] In one aspect, the present application provides a method for manufacturing a semiconductor, comprising:
[0006] Cyclic epitaxial growth of silicon layers and sacrificial layers on a first wafer to obtain a capacitor nanosheet layer of a silicon-germanium superlattice structure; the capacitor nanosheet layer comprises a plurality of cyclically deposited silicon layers and a plurality of sacrificial layers;
[0007] Depositing a first dielectric layer on the capacitor nanosheet layer, and bonding the first dielectric layer to the all-around gate transistor device layer of the second wafer;
[0008] Depositing an oxide layer, a dummy gate layer and a hard mask layer in sequence on the capacitor nanosheet layer;
[0009] Forming a first spacer and an inner spacer at the oxide layer, the dummy gate layer, the hard mask layer and the capacitor nanosheet layer;
[0010] After removing the dummy gate layer and the multiple sacrificial layers, dielectric filling, metal filling and polishing are performed to obtain a capacitor device.
[0011] Preferably, after removing the plurality of sacrificial layers and the dummy gate layer, dielectric filling, metal filling and polishing are performed to obtain a capacitor device, the method further comprises:
[0012] depositing a second dielectric layer on the polished capacitor device;
[0013] Perform photolithography and etching on the second dielectric layer and the inner sidewall to obtain a plurality of through holes; one of the through holes is connected to the plurality of silicon layers and a through hole of the ring-gate transistor device layer;
[0014] The plurality of through holes are filled.
[0015] Preferably, the cyclic epitaxial growth of the silicon layer and the sacrificial layer on the first wafer to obtain the capacitor nanosheet layer of the silicon-germanium superlattice structure comprises:
[0016] depositing a silicon layer on the first wafer;
[0017] Depositing a sacrificial layer on the silicon layer; wherein the material of the sacrificial layer includes silicon germanium and / or germanium tin;
[0018] If the number of the sacrificial layers is less than the preset number of layers, a silicon layer is deposited on the sacrificial layer, and the step of depositing a silicon germanium layer on the silicon layer is continued until the number of the sacrificial layers is equal to the preset number of layers, thereby obtaining the capacitor nanosheet layer of the silicon germanium superlattice structure.
[0019] Preferably, the step of sequentially depositing an oxide layer, a dummy gate layer and a hard mask layer on the capacitor nanosheet layer comprises:
[0020] Depositing the oxide layer on the topmost silicon layer among the plurality of silicon layers in the capacitor nanosheet layer;
[0021] depositing the dummy gate layer on the oxide layer;
[0022] The hard mask layer is deposited on the dummy gate layer.
[0023] Preferably, forming a first sidewall spacer and an inner sidewall spacer at the oxide layer, the dummy gate layer, the hard mask layer and the capacitor nanosheet layer comprises:
[0024] Etching the oxide layer, the dummy gate layer and the hard mask layer;
[0025] Forming a first spacer outside the oxide layer and the dummy gate layer;
[0026] Etching the capacitor nanosheet layer so that the width of the silicon layer in the capacitor nanosheet layer is greater than that of the sacrificial layer;
[0027] An inner sidewall is formed outside the sacrificial layer.
[0028] Preferably, after removing the dummy gate layer and the plurality of sacrificial layers, dielectric filling, metal filling and polishing are performed, and before obtaining the capacitor device, the method further comprises:
[0029] Depositing an interlayer dielectric on the capacitor nanosheet layer and the dummy gate layer;
[0030] Polishing the hard mask to expose the dummy gate layer;
[0031] Etching the dummy gate layer and the oxide layer to form a to-be-filled area on the last silicon layer in the capacitor nanosheet layer;
[0032] The plurality of sacrificial layers are released, so that a plurality of gaps to be filled are provided between the plurality of silicon layers.
[0033] Preferably, after removing the dummy gate layer and the plurality of sacrificial layers, dielectric filling, metal filling and polishing are performed to obtain a capacitor device, comprising:
[0034] Filling the to-be-filled area and the plurality of to-be-filled gaps with dielectric material and metal material to form a third dielectric layer and a metal layer; the third dielectric layer surrounds the metal layer;
[0035] The metal layer and the second dielectric layer on the first sidewall are polished to expose the first sidewall, thereby obtaining the capacitor device.
[0036] In a second aspect, the present application provides a semiconductor, comprising: a gate-all-around transistor device layer and a capacitor device;
[0037] The capacitor device comprises a capacitor nanosheet layer of a silicon germanium superlattice structure;
[0038] The capacitor nanosheet layer includes a first sidewall and an inner sidewall, and a plurality of silicon layers and a plurality of sacrificial layers stacked in a circular manner;
[0039] The sacrificial layer includes a dielectric and a metal.
[0040] Preferably, the capacitor device is connected to the all-around gate transistor device in the all-around gate transistor device layer through a through hole in the capacitor device layer.
[0041] In a third aspect, the present application proposes an electronic device comprising the semiconductor described in any one of the second aspects.
[0042] The advantage of the present application is that by cyclically growing an epitaxial silicon layer and a sacrificial layer in the vertical direction and making a capacitor layer by bonding, a periodically adjustable capacitor with a horizontal stacking structure can be obtained, thereby making more efficient use of the vertical space, reducing the size of the capacitor, increasing the capacitor capacity, and at the same time reducing the size of the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] By reading the detailed description of the preferred embodiment below, various other advantages and benefits will become clear to those of ordinary skill in the art. The accompanying drawings are only used for the purpose of illustrating the preferred embodiment and are not to be considered as limiting the present application. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0044] Figure 1 is a schematic diagram of a standardized comparison of existing DRAMs at different nanotechnology nodes;
[0045] Figure 2 is a schematic diagram of the cell capacitance of an existing DRAM technology node;
[0046] Figure 3 It is a schematic diagram of the physical structure of a conventional DRAM;
[0047] Figure 4 It is a schematic diagram of the trench capacitor structure adopted by the conventional DRAM technology solution;
[0048] Figure 5 It is a schematic diagram of the trend of unit transistor technology;
[0049] Figure 6 It is a schematic diagram of the structure of the capacitor of 4F2 DRAM;
[0050] Figure 7 is a schematic diagram of the existing VSDRAM architecture;
[0051] Figure 8 is a schematic diagram of a semiconductor manufacturing method provided by the present application;
[0052] Fig. 9 It is a schematic diagram of a capacitor device layer and a gate-all-around transistor device layer of a semiconductor manufacturing method provided by the present application;
[0053] Fig.10 It is a schematic diagram of a cyclic epitaxial silicon layer and a sacrificial layer in a semiconductor manufacturing method provided by the present application;
[0054] Fig.11 It is a schematic diagram of an oxide layer, a dummy gate layer and a hard mask layer of a semiconductor manufacturing method provided by the present application;
[0055] Fig.12 It is a schematic diagram of a first sidewall and an inner sidewall of a semiconductor manufacturing method provided by the present application;
[0056] Fig.13 It is a schematic diagram of a first spacer layer of a semiconductor manufacturing method provided by the present application;
[0057] Fig.14It is a schematic diagram of a first end and a second end of a semiconductor manufacturing method provided by the present application;
[0058] Fig.15 It is a schematic diagram of an embedded cavity structure of a semiconductor manufacturing method provided by the present application;
[0059] Fig.16 It is a schematic diagram of an inner wall insulating dielectric layer of a semiconductor manufacturing method provided by the present application;
[0060] Fig.17 It is a schematic diagram of a gap to be filled and an area to be filled in a semiconductor manufacturing method provided by the present application;
[0061] Fig.18 It is a schematic diagram of dielectric filling and metal filling of a semiconductor manufacturing method provided by the present application;
[0062] Fig.19 It is a schematic diagram of a third dielectric layer and a metal layer in a semiconductor manufacturing method provided by the present application;
[0063] Fig. 20 It is a schematic diagram of a first dielectric layer of a semiconductor manufacturing method provided by the present application;
[0064] Fig.21 It is a schematic diagram of bonding of a semiconductor manufacturing method provided by the present application;
[0065] Fig. 22 It is a schematic diagram of a gate transistor device layer of a semiconductor manufacturing method provided by the present application;
[0066] Fig.23 It is a schematic diagram of a wrap-around gate transistor in a semiconductor manufacturing method provided by the present application;
[0067] Fig.24 It is a schematic diagram of a semiconductor provided by the present application. DETAILED DESCRIPTION
[0068] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0069] like Figure 3As shown, the physical structure of conventional DRAM adopts a one transistor one capacitor (1T1C) structure, that is, a transistor is connected in series with a capacitor to form a memory structure. Figure 4 As shown, conventional technical solutions generally adopt a trench capacitor structure, which has a large trench depth-to-width ratio. Figure 5 As shown, after the 6F2 architecture was commercialized, the 4F2 architecture (such as Figure 6 ) architecture and VSDRAM architecture (as shown Figure 7 The VSDRAM architecture requires precise control of the high aspect ratio silicon germanium selective etching process, but the large planar space it occupies limits the further increase in storage unit density. Although the 4F2 architecture has obvious storage density advantages based on full utilization of vertical space, it faces huge challenges in terms of process, such as the need for high-quality and high-uniformity thin silicon channels, precise control of the verticality of the channel and capacitor, and control of the floating body effect. These are all issues that need to be addressed.
[0070] The embodiments of the present application obtain a periodically adjustable capacitor with a horizontal stacking structure by cyclically stacking silicon layers and sacrificial layers in the vertical direction, which can increase the capacitor capacity while improving the utilization of the vertical space and avoid the huge problems faced by trench capacitors in aspect ratio technology. The structure of the capacitor device of the embodiments of the present application can make full use of the advantages of the vertical space, and by stacking nanosheets with adjustable number of layers and depositing HK (high K) dielectric layers at the same time, it can also be used to realize a stacked capacitor structure with adjustable capacitance storage density.
[0071] In a first aspect, the embodiments of the present application provide a method for manufacturing a semiconductor, such as Figure 8 As shown, including:
[0072] S101, cyclically epitaxially growing a silicon layer 230 and a sacrificial layer 210 on a first wafer 1, to obtain a capacitor nanosheet layer 200 of a silicon-germanium superlattice structure; the capacitor nanosheet layer includes a plurality of cyclically deposited silicon layers 230 and a plurality of sacrificial layers 210;
[0073] S102, depositing a first dielectric layer 100 on the capacitor nanosheet layer 200, and bonding the first dielectric layer 100 to the all-around gate transistor device layer 10 of the second wafer 2;
[0074] S103, depositing an oxide layer 310, a dummy gate layer 320 and a hard mask layer 330 in sequence on the capacitor nanosheet layer 200;
[0075] S104 , forming a first spacer 340 and an inner spacer 350 on the oxide layer 310 , the dummy gate layer 320 , the hard mask layer 330 and the capacitor nanosheet layer 200 ;
[0076] S105 , after removing the dummy gate layer 320 and the plurality of sacrificial layers 210 , dielectric filling, metal filling and polishing are performed to obtain the capacitor device 21 .
[0077] The embodiment of the present application cycles the epitaxial silicon layer 230 and the sacrificial layer 210 in the vertical direction, and uses a bonding method to make a capacitor layer on the ring-gate transistor device layer 10, and realizes a manufacturing method of a three-dimensional stacked DRAM with controllable capacitor capacity by controlling the number of stacked silicon layers 230, so that the physical structure of the formed capacitor can more effectively utilize the vertical space, while increasing the capacitor capacity, it can also reduce the size of the storage unit, and realize the three-dimensional integration of dynamic random access memory. The high-K material is wrapped in a superlattice of a stacked structure to form a parallel capacitor device with adjustable cycle period, and the capacitance can be controlled by adjusting the cycle period of the superlattice (capacitor nanosheet layer 200).
[0078] like Fig. 9 As shown, after removing multiple sacrificial layers 210 and dummy gate layers 320, dielectric filling, metal filling and polishing are performed to obtain a capacitor device, and the method further includes: depositing a second dielectric layer 300 on the polished capacitor device; performing photolithography and etching outside the second dielectric layer 300 and the inner sidewall 350 to obtain multiple through holes 30; one of the through holes 30 is connected to multiple silicon layers 230 and a through hole 30 of the ring-gate transistor device layer 10; and filling the multiple through holes 30.
[0079] Polishing includes: chemical mechanical polishing (CMP).
[0080] like Fig.10 As shown, a silicon layer 230 and a sacrificial layer 210 are cyclically epitaxially grown on a first wafer 1 to obtain a capacitor nanosheet layer 200 with a silicon-germanium superlattice structure, including: depositing a silicon layer 230 on the first wafer 1; depositing a sacrificial layer 210 on the silicon layer 230; wherein the material of the sacrificial layer 210 includes silicon-germanium and / or germanium-tin; if the number of sacrificial layers 210 is less than a preset number of layers, depositing a silicon layer 230 on the sacrificial layer 210, and continuing to perform the step of depositing a silicon-germanium layer on the silicon layer 230 until the number of sacrificial layers 210 is equal to the preset number of layers, thereby obtaining a capacitor nanosheet layer 200 with a silicon-germanium superlattice structure.
[0081] Among them, the silicon-germanium superlattice structure includes: a superlattice structure of silicon and silicon-germanium, a superlattice structure of silicon and germanium-tin, and can also be a superlattice structure of silicon-germanium with different concentrations, such as a superlattice structure of Si0.9Ge0.1 or Si0.7Ge0.3. The single-cycle structure, that is, the total thickness of a sacrificial layer 210 and a silicon layer 230 is generally greater than or equal to 10nm, and less than or equal to 30nm. Among them, the thickness of the sacrificial layer 210 and the silicon layer 230 can be different, such as silicon layer 230 (Si) 18nm / sacrificial layer 210 (such as SiGe) 12nm, etc. The period of the cyclic structure is adjustable, and can generally be extended from 2 cycles to 40 cycles, or even more than 40 cycles. Therefore, the preset number of layers can be determined according to the preset period, that is, the number of cycles.
[0082] like Fig.11 As shown, an oxide layer 310, a dummy gate layer 320 and a hard mask layer 330 are sequentially deposited on the capacitor nanosheet layer 200, including: depositing an oxide layer 310 on the topmost silicon layer 230 among the multiple silicon layers 230 in the capacitor nanosheet layer 200; depositing a dummy gate layer 320 on the oxide layer 310; and depositing a hard mask layer 330 on the dummy gate layer 320.
[0083] like Fig.12 As shown, a first sidewall 340 and an inner sidewall 350 are formed at the oxide layer 310, the dummy gate layer 320, the hard mask layer 330 and the capacitor nanosheet layer 200, including: etching the oxide layer 310, the dummy gate layer 320 and the hard mask layer 330; forming the first sidewall 340 outside the oxide layer 310 and the dummy gate layer 320; etching the capacitor nanosheet layer 200 so that the width of the silicon layer 230 in the capacitor nanosheet layer 200 is greater than the sacrificial layer 210; and forming the inner sidewall 350 outside the sacrificial layer 210.
[0084] Among them, the removal of the dummy gate layer 320 can be done by dry etching or wet etching. Since the etching gas or solution is selective to amorphous silicon (a-Si), other materials will not be etched or will be etched very little. The sacrificial layer 210 in the capacitor nanosheet layer 200 can be released by dry etching or wet etching, so that the etching gas or solution is selective to the material of the sacrificial layer 210, such as the dielectric of the silicon germanium layer, so that other materials will not be etched or will be etched very little during the etching process, so that multiple gaps to be filled are formed between the silicon layers 230. The material of the dummy gate layer 320 includes amorphous silicon (a-Si).
[0085] like Fig.11 As shown, the oxide layer 310 , the dummy gate layer 320 and the hard mask layer 330 are etched, including: defining the capacitor region by photolithography; and etching out lines by dry etching and stopping on the silicon layer 230 .
[0086] like Fig.13and Fig.14 As shown, a first sidewall spacer 340 is formed outside the oxide layer 310 and the dummy gate layer 320, including: depositing a dielectric material for forming a first sidewall spacer 360, such as silicon nitride (SiN), on the etched oxide layer 310, the dummy gate layer 320 and the hard mask layer 330 to form the first sidewall spacer 360; etching the first sidewall spacer 360 to form the first sidewall spacer 340 outside the oxide layer 310 and the dummy gate layer 320.
[0087] like Fig.14 and Fig.15 As shown, the capacitor nanosheet layer 200 is etched so that the width of the silicon layer 230 in the capacitor nanosheet layer 200 is greater than the sacrificial layer 210, including: selectively etching back (or dry etching, wet etching) the first end 211 and the second end 212 of each sacrificial layer 210 of the capacitor nanosheet layer 200 to form a plurality of embedded cavity structures 213 at the original positions of the first end 211 and the second end 212, so that the opposite side walls of the stacked structure of the sacrificial layer 210 and the silicon layer 230 after the back etching have a plurality of teeth of the nanosheet (for example, rectangular teeth or square teeth), wherein the depth of the plurality of embedded cavity structures 213 is the same as the thickness of the first sidewall 340.
[0088] like Fig.16 Shown and Fig.12 As shown, an inner sidewall 350 is formed on the outside of the sacrificial layer 210, including: depositing an inner sidewall insulating dielectric layer 370 on the top surface and part of the sidewall of the oxide layer 310, in the first sidewall 340, in the embedded cavity structure 213, and on multiple teeth; and etching the inner sidewall insulating dielectric layer 370 to remove the inner sidewall insulating dielectric layer 370 on the top surface and part of the sidewall of the oxide layer 310, the inner sidewall insulating dielectric layer 370 on the top surface and sidewall of the first sidewall 340, and the inner sidewall insulating dielectric layer 370 on multiple teeth, while retaining the first end 211 and the second end 212 of the inner sidewall insulating dielectric layer 370 in the multiple embedded cavity structures 213 of the sacrificial layer 210 to form the inner sidewall 350.
[0089] like Fig.17 As shown, after removing the dummy gate layer 320 and multiple sacrificial layers 210, dielectric filling, metal filling and polishing are performed to obtain the capacitor device 21, and the method also includes: depositing an interlayer dielectric 240 on the capacitor nanosheet layer 200 and the dummy gate layer 320; polishing the hard mask to expose the dummy gate layer 320; etching the dummy gate layer 320 and the oxide layer 310 to form a to-be-filled area 312 on the last silicon layer 230 in the capacitor nanosheet layer 200; releasing multiple sacrificial layers 210 to have multiple to-be-filled gaps 214 between the multiple silicon layers 230.
[0090] like Fig.18 and Fig.19 As shown, after removing the dummy gate layer 320 and the multiple sacrificial layers 210, dielectric filling, metal filling and polishing are performed to obtain a capacitor device 21, including: filling dielectric materials and metal materials in the to-be-filled area 312 and the multiple to-be-filled gaps 214 to form a third dielectric layer 215 and a metal layer 216; the third dielectric layer 215 surrounds the metal layer 216; polishing the metal layer 216 and the third dielectric layer 215 on the first sidewall 340 to expose the first sidewall 340, thereby obtaining the capacitor device 21.
[0091] like Fig. 20 and Fig.21 As shown, a first dielectric layer 100 is deposited on the capacitor nanosheet layer 200, and the first dielectric layer 100 is bonded to the ring-gate transistor device layer 10 of the second wafer 2, including: bonding the first dielectric layer 100 to the top of the ring-gate transistor device layer 10 of the second wafer 2, wherein the substrate of the second wafer 2 is the bottom (substrate) of the overall wafer after bonding.
[0092] Before depositing the oxide layer 310, the dummy gate layer 320 and the hard mask layer 330 in sequence on the capacitor nanosheet layer 200, the method further includes: thinning the substrate of the first wafer 1 to expose the topmost sacrificial layer 210 among the multiple sacrificial layers 210 in the capacitor nanosheet layer 200; etching the topmost sacrificial layer 210 to expose the topmost silicon layer 230 among the multiple silicon layers 230 in the capacitor nanosheet layer 200.
[0093] The ring-gate dielectric material of the capacitor (the material of the third dielectric layer 215) includes hafnium oxide; it can also be replaced with other oxide dielectric materials, such as zirconium oxide, silicon oxide, aluminum oxide, hafnium oxynitride, etc.; it can also include a stacked combination of different oxide dielectric materials, that is, using multiple materials to form multiple different stacks as the third dielectric layer 215. The ring-gate dielectric material of the capacitor can be grown by multiple methods, including atomic layer deposition (ALD), physical vapor deposition (PVD), etc.
[0094] like Fig. 22As shown, before depositing the first dielectric layer 100 on the all-around gate transistor device layer 10, the method further includes: preparing the all-around gate transistor device layer 10 including the all-around gate transistor device 11. The method of making the all-around gate transistor device layer 10 can use the existing preparation method, such as periodically epitaxially growing silicon / silicon germanium stacks on a semiconductor substrate to form multiple epitaxial stacks; defining the fin region and gate region of the all-around gate transistor device 11; performing source and drain epitaxy; removing the dummy gate, filling the high-K dielectric layer metal gate (HKMG); filling the inter-layer dielectric layer (ILD) dielectric; defining the through hole 30, etc.
[0095] like Fig.23 As shown, the gate-all-around (GAA) transistor (ring-gate transistor) adopts a gate-all-around nanosheet structure and is the preferred transistor for advanced logic process nodes. It has stacked multi-layer nanosheets.
[0096] Second, as Fig.24 As shown, according to an embodiment of the present application, a semiconductor is also proposed, comprising: a gate-all-around transistor device layer 10 and a capacitor device 21;
[0097] The capacitor device 21 includes a capacitor nanosheet layer 200 of a silicon germanium superlattice structure;
[0098] The capacitor nanosheet layer 200 includes a first sidewall 340 and an inner sidewall 350 , and a plurality of silicon layers 230 and a plurality of sacrificial layers 210 stacked in a cyclic manner;
[0099] The sacrificial layer 210 includes a dielectric and a metal.
[0100] Since the sacrificial layer will be etched, dielectric material and metal material are filled in the region formed after the sacrificial layer is etched, so the sacrificial layer includes dielectric and metal. The filled dielectric material forms the third dielectric layer 215, and the filled metal material forms the metal layer 216. The third dielectric layer 215 surrounds the metal layer 216.
[0101] The capacitor device 21 is connected to the gate-all-around transistor device 11 in the gate-all-around transistor device layer 10 through the through-hole 30 in the capacitor device layer 20 .
[0102] The capacitor device layer 20 includes a capacitor device 21 and a plurality of through holes 30 .
[0103] In a third aspect, according to an implementation of the present application, an electronic device is also proposed, comprising a semiconductor as described in any one of the second aspects.
[0104] In the implementation of the present application, a capacitor with a controllable superlattice structure is bonded on the wafer where the ring-gate transistor device layer 10 is located, and the capacitor manufacturing and device interconnection of the ring-gate structure are performed, thereby realizing the physical structure and full-process manufacturing method of a three-dimensional stacked GAA DRAM with controllable capacitor capacity. By cyclically growing the epitaxial silicon layer 230 and the sacrificial layer 210 in the vertical direction, and making the capacitor layer by bonding, a capacitor with a periodic adjustable horizontal stacking structure can be obtained, so that the vertical space can be more effectively utilized and the capacitor capacity can be increased. In addition, the capacitor structure of the implementation of the present application can further reduce the device arrangement period on the basis of effectively utilizing the vertical space, thereby effectively reducing the size of the storage unit, shrinking the size of the semiconductor while shrinking the size of the capacitor, thereby improving the performance of the storage device and realizing large-capacity GAA DRAM integration.
[0105] The above is only a preferred specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A method for manufacturing a semiconductor, characterized in that: include: Cyclic epitaxial silicon layer and sacrificial layer on the first wafer to obtain a capacitor nanosheet layer with a silicon-germanium superlattice structure; The capacitor nanosheet layer includes a plurality of silicon layers and a plurality of sacrificial layers deposited cyclically; Depositing a first dielectric layer on the capacitor nanosheet layer, and bonding the first dielectric layer to the all-around gate transistor device layer of the second wafer; Depositing an oxide layer, a dummy gate layer and a hard mask layer in sequence on the capacitor nanosheet layer; Forming a first spacer and an inner spacer at the oxide layer, the dummy gate layer, the hard mask layer and the capacitor nanosheet layer; After removing the dummy gate layer and the multiple sacrificial layers, dielectric filling, metal filling and polishing are performed to obtain a capacitor device.
2. The method according to claim 1, characterized in that After removing the plurality of sacrificial layers and the dummy gate layer, dielectric filling, metal filling and polishing are performed to obtain a capacitor device, the method further comprises: depositing a second dielectric layer on the polished capacitor device; Perform photolithography and etching on the second dielectric layer and the inner sidewall to obtain a plurality of through holes; one of the through holes is connected to the plurality of silicon layers and a through hole of the ring-gate transistor device layer; The plurality of through holes are filled.
3. The method according to claim 1, characterized in that The method of cyclically epitaxially growing a silicon layer and a sacrificial layer on the first wafer to obtain a capacitor nanosheet layer of a silicon-germanium superlattice structure comprises: depositing a silicon layer on the first wafer; Depositing a sacrificial layer on the silicon layer; wherein the material of the sacrificial layer includes silicon germanium and / or germanium tin; If the number of the sacrificial layers is less than the preset number of layers, a silicon layer is deposited on the sacrificial layer, and the step of depositing a silicon germanium layer on the silicon layer is continued until the number of the sacrificial layers is equal to the preset number of layers, thereby obtaining the capacitor nanosheet layer of the silicon germanium superlattice structure.
4. The method according to claim 1, characterized in that The step of sequentially depositing an oxide layer, a dummy gate layer and a hard mask layer on the capacitor nanosheet layer comprises: Depositing the oxide layer on the topmost silicon layer among the plurality of silicon layers in the capacitor nanosheet layer; depositing the dummy gate layer on the oxide layer; The hard mask layer is deposited on the dummy gate layer.
5. The method according to claim 1, characterized in that The step of forming a first sidewall spacer and an inner sidewall spacer at the oxide layer, the dummy gate layer, the hard mask layer and the capacitor nanosheet layer comprises: Etching the oxide layer, the dummy gate layer and the hard mask layer; Forming a first spacer outside the oxide layer and the dummy gate layer; Etching the capacitor nanosheet layer so that the width of the silicon layer in the capacitor nanosheet layer is greater than that of the sacrificial layer; An inner sidewall is formed outside the sacrificial layer.
6. The method according to claim 1, characterized in that After removing the dummy gate layer and the plurality of sacrificial layers, dielectric filling, metal filling and polishing are performed to obtain the capacitor device, and the method further includes: Depositing an interlayer dielectric on the capacitor nanosheet layer and the dummy gate layer; Polishing the hard mask to expose the dummy gate layer; Etching the dummy gate layer and the oxide layer to form a to-be-filled area on the last silicon layer in the capacitor nanosheet layer; The plurality of sacrificial layers are released, so that a plurality of gaps to be filled are provided between the plurality of silicon layers.
7. The method according to claim 6, characterized in that After removing the dummy gate layer and the plurality of sacrificial layers, dielectric filling, metal filling and polishing are performed to obtain a capacitor device, including: Filling the to-be-filled area and the plurality of to-be-filled gaps with dielectric material and metal material to form a third dielectric layer and a metal layer; the third dielectric layer surrounds the metal layer; The metal layer and the second dielectric layer on the first sidewall are polished to expose the first sidewall, thereby obtaining the capacitor device.
8. A semiconductor, characterized in that: include: Gate-all-around transistor device layer and capacitor device; The capacitor device comprises a capacitor nanosheet layer of a silicon germanium superlattice structure; The capacitor nanosheet layer includes a first sidewall and an inner sidewall, and a plurality of silicon layers and a plurality of sacrificial layers stacked in a circular manner; The sacrificial layer includes a dielectric and a metal.
9. The semiconductor device according to claim 8, wherein: The capacitor device is connected to the all-around gate transistor device in the all-around gate transistor device layer through a through hole in the capacitor device layer.
10. An electronic device, characterized in that: Comprising a semiconductor as claimed in claim 8 or 9.