Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to prevent a storage function of a channel structure of an array region from being influenced by electric leakage of the channel structure of a connection region and improve the yield of the semiconductor structure. The semiconductor structure provided by the embodiment of the invention comprises a first channel structure located in an array region, a second channel structure located in a connection region, a first insulating isolation layer covering a stack structure, and a semiconductor layer located on the first insulating isolation layer, the first semiconductor column penetrates through the first insulating isolation layer to be connected with the semiconductor layer, the second semiconductor column is located in the first insulating isolation layer, and the first insulating isolation layer can prevent the semiconductor layer from being directly connected with the grid line layer at the second channel structure, so that the storage function of the first channel structure is prevented from being influenced by electric leakage of the second channel structure; and the yield of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] As the feature size of the memory cell approaches the process lower limit, the planar process and manufacturing technology become challenging and costly, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases the storage density by arranging the memory cells three-dimensionally on the substrate.

[0003] The semiconductor structure includes multiple channel structures interconnected by semiconductor layers. The channel structure located in the connection area is easily damaged, causing the gate line layer located in the connection area to be directly connected to the semiconductor layer, resulting in leakage in the connection area, which in turn affects the storage function of the channel structure located in the array area and reduces the yield rate of the semiconductor structure. Summary of the invention

[0004] Embodiments of the present invention provide a semiconductor structure and a method for manufacturing the same, a storage system, and an electronic device, which are intended to prevent leakage of a channel structure in a connection area from affecting the storage function of a channel structure in an array area, thereby improving the yield of the semiconductor structure.

[0005] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0006] On the one hand, the semiconductor structure provided by the embodiment of the present application includes a stacking structure, a channel structure, a first insulating isolation layer and a semiconductor layer, the stacking structure includes an array area and a connection area, the array area and the connection area are adjacent to each other, the channel structure includes a first channel structure and a second channel structure, the first channel structure and the second channel structure both pass through the stacking structure, the first channel structure is located in the array area, and the second channel structure is located in the connection area, the first channel structure includes a first semiconductor column; the second channel structure includes a second semiconductor column, the first insulating isolation layer covers the stacking structure, one end of the first semiconductor column away from the stacking structure passes through the first insulating isolation layer, and one end of the second semiconductor column away from the stacking structure is located in the first insulating isolation layer, and the semiconductor layer is connected to a portion of the first semiconductor column located on the side of the first insulating isolation layer away from the stacking structure.

[0007] The semiconductor structure provided in the embodiment of the present application includes a stacking structure and a channel structure passing through the stacking structure, the stacking structure includes an array area and a connection area, the channel structure includes a first channel structure located in the array area and a second channel structure located in the connection area, the semiconductor structure also includes a first insulating isolation layer covering the stacking structure, and a semiconductor layer located on the side of the first insulating isolation layer away from the stacking structure, the first semiconductor column of the first channel structure passes through the first insulating isolation layer and is connected to the semiconductor layer, the second semiconductor column of the second channel structure is located in the first insulating isolation layer, so that the first insulating isolation layer can fill the hole formed at the position of the second dielectric layer, that is, the first insulating isolation layer can prevent the semiconductor layer from being directly connected to the gate line layer at the second channel structure, thereby avoiding the leakage of the second channel structure affecting the storage function of the first channel structure, and improving the yield rate of the semiconductor structure.

[0008] In some embodiments, a projection of the semiconductor layer onto the stacked structure covers the first insulating isolation layer.

[0009] Through the above arrangement, compared with the case where the semiconductor layer covers the array region of the stacked structure, in the process of forming the semiconductor layer, there is no need to limit the position where the semiconductor layer is formed, thereby simplifying the process of forming the semiconductor layer.

[0010] In some embodiments, the semiconductor structure further includes: an insulating cover layer and a first conductive column, wherein the insulating cover layer covers the semiconductor layer, the first conductive column penetrates the insulating cover layer, and the first conductive column is connected to the semiconductor layer.

[0011] Through the above arrangement, the insulating capping layer covers the semiconductor layer to form a flat surface, and a contact pad is formed at one end of the insulating cover layer away from the stacking structure, which is convenient for connecting the semiconductor layer with the peripheral circuit. The semiconductor structure also includes a first conductive column, which penetrates the insulating cover layer, one end of the first conductive column extends to the semiconductor layer and is connected to the semiconductor layer, and the other end of the first conductive column is connected to the contact pad, which is convenient for connecting the semiconductor layer with the peripheral circuit.

[0012] In some embodiments, the first conductive pillar is connected to a portion of the semiconductor layer located in the array region.

[0013] Through the above configuration, the length of the first conductive column can be shortened, thereby reducing the resistance of the first conductive column.

[0014] In some embodiments, the semiconductor structure further includes an isolation structure, and the isolation structure penetrates the array region; the first conductive pillar is connected to the semiconductor layer corresponding to the isolation structure.

[0015] Through the above arrangement, the isolation structure can support the stacked structure to improve the stability of the semiconductor structure. The first conductive column is connected to the semiconductor layer corresponding to the isolation structure, which increases the connection area between the first conductive column and the semiconductor layer and improves the stability of the connection between the first conductive column and the semiconductor layer.

[0016] In some embodiments, the isolation structure includes a filling column and a second insulating isolation layer covering the filling column, and one end of the filling column facing away from the stacking structure is connected to the semiconductor layer.

[0017] Through the above arrangement, the filling column runs through the stacking structure, and the end of the filling column away from the stacking structure passes through the first insulating isolation layer. The part of the filling column located on the side of the first insulating isolation layer away from the stacking structure is located in the semiconductor layer and connected to the semiconductor layer to improve the stability of the semiconductor layer.

[0018] In some embodiments, the semiconductor structure further includes a second conductive column, the second conductive column penetrates the semiconductor layer, and a third insulating isolation layer is disposed between the second conductive column and the semiconductor layer.

[0019] Through the above arrangement, the third insulating isolation layer can achieve insulation between the second conductive column and the semiconductor layer.

[0020] In some embodiments, the semiconductor structure further includes a connection structure, the connection structure penetrates the stack structure, and the connection structure is located in the connection region, and the second conductive column is connected to the connection structure.

[0021] Through the above arrangement, one end of the second conductive column passes through the semiconductor layer and is connected to the connection structure, and the other end of the second conductive column is connected to the contact pad, which facilitates the connection between the semiconductor layer and the peripheral circuit.

[0022] In some embodiments, the first channel structure further includes a first dielectric layer located between the first semiconductor column and the stacked structure; the second channel structure further includes a second dielectric layer located between the second semiconductor column and the stacked structure.

[0023] Through the above arrangement, the first dielectric layer can form a transistor with the gate line layer in the stacked structure, and the second dielectric layer can form a transistor with the gate line layer in the stacked structure to realize the storage function of the channel structure.

[0024] On the other hand, an embodiment of the present application further provides a method for preparing a semiconductor structure, comprising:

[0025] A stacking structure is formed, the stacking structure includes an array area and a connection area, the array area and the connection area are arranged adjacent to each other; a first channel structure and a second channel structure penetrating the stacking structure are arranged on the stacking structure, the first channel structure is located in the array area, and the second channel structure is located in the connection area; the first channel structure includes a first semiconductor column and a first dielectric layer wrapping the first semiconductor column; the second channel structure includes a second semiconductor column and a second dielectric layer wrapping the second semiconductor column;

[0026] removing a portion of the first dielectric layer of the first channel structure away from one end of the stack structure and a portion of the second dielectric layer of the second channel structure away from one end of the stack structure;

[0027] An intermediate insulating isolation layer is formed on the stack structure, and a portion of the intermediate insulating isolation layer is removed to form a first insulating isolation layer, wherein an end of the first semiconductor column away from the stack structure is located on a side of the first insulating isolation layer away from the stack structure;

[0028] A semiconductor layer is formed on the first insulating isolation layer, and the semiconductor layer covers an end of the first semiconductor column away from the stack structure.

[0029] In some embodiments, forming an intermediate insulating isolation layer on the stacked structure, removing a portion of the intermediate insulating isolation layer to form a first insulating isolation layer, and positioning an end of the first semiconductor column away from the stacked structure on a side of the first insulating isolation layer away from the stacked structure comprises:

[0030] forming an intermediate insulating isolation layer on the stacked structure, wherein the intermediate insulating isolation layer covers the array region and the connection region;

[0031] forming a mask plate on the intermediate insulating isolation layer, wherein the mask plate covers the connection area;

[0032] A portion of the middle insulating isolation layer located in the array region is removed so that an end of the first semiconductor column away from the stack structure is located on a side of the first insulating isolation layer away from the stack structure.

[0033] Through the above arrangement, the intermediate insulating isolation layer covers the first semiconductor column located in the array area, and covers the second semiconductor column located in the connection area to cover the leakage of the second channel structure. The formed mask plate covers the connection area. Since the mask plate only covers the connection area, the intermediate insulating isolation layer located in the connection area will not be removed. After removing part of the intermediate insulating isolation layer located in the array area, the remaining part of the intermediate insulating isolation layer serves as the first insulating isolation layer, so that the end of the first semiconductor column away from the stacking structure is located on the side of the first insulating isolation layer away from the stacking structure, which facilitates the connection between the first semiconductor columns.

[0034] In some embodiments, forming a semiconductor layer on the first insulating isolation layer, wherein the semiconductor layer covers an end of the first semiconductor column away from the stacked structure, comprises:

[0035] After removing a portion of the intermediate insulating isolation layer located in the array region, a semiconductor layer is formed in the array region.

[0036] Through the above arrangement, the material for forming the semiconductor layer is reduced while multiple first channel structures can be connected to each other.

[0037] In some embodiments, forming a semiconductor layer on the first insulating isolation layer, wherein the semiconductor layer covers an end of the first semiconductor column away from the stacked structure, comprises:

[0038] After removing part of the intermediate insulating isolation layer located in the array area, the mask plate is removed;

[0039] A semiconductor layer is formed, wherein the semiconductor layer covers the array region and the connection region.

[0040] Through the above arrangement, the semiconductor layer covers the array area and the connection area. The end of a portion of the first semiconductor column away from the stacking structure is located on the side of the first insulating isolation layer away from the stacking structure, so in the process of forming the semiconductor layer, a portion of the first semiconductor column is located in the semiconductor layer, and the first semiconductor column and the semiconductor layer can both include single crystal silicon or polycrystalline silicon, thereby realizing the connection between the first semiconductor column and the semiconductor layer.

[0041] In some embodiments, after forming the semiconductor layer, the semiconductor structure manufacturing method further includes:

[0042] An insulating cover layer is formed on the semiconductor layer, and a first conductive hole is formed on the insulating cover layer, wherein the bottom of the first conductive hole is located on the semiconductor layer;

[0043] A first conductive column is formed in the first conductive hole, and the first conductive column is connected to the semiconductor layer.

[0044] Through the above arrangement, one end of the first conductive column extends to the semiconductor layer and is connected to the semiconductor layer, and the other end of the first conductive column is connected to the contact pad, which facilitates the connection between the semiconductor layer and the peripheral circuit.

[0045] In some embodiments, forming the stacked structure further comprises:

[0046] forming an isolation structure on the array region;

[0047] Forming a first conductive hole on the insulating cover layer includes: forming a first conductive hole on the insulating cover layer corresponding to the isolation structure.

[0048] Through the above-mentioned arrangement, through the above-mentioned arrangement, the first conductive column formed in the first conductive hole can be connected to the semiconductor layer corresponding to the isolation structure. Compared with the connection between the first conductive column and the semiconductor layer corresponding to the first semiconductor column, the diameter of the filling column is larger than the diameter of the first semiconductor column. Therefore, the connection between the first conductive column and the semiconductor layer corresponding to the isolation structure can increase the connection area between the first conductive column and the semiconductor layer, and improve the stability of the connection between the first conductive column and the semiconductor layer.

[0049] In some embodiments, the isolation structure includes a filling column and a second insulating isolation layer covering the filling column;

[0050] Before forming the semiconductor layer on the stacked structure, the method further includes: removing a portion of the second insulating isolation layer to expose an end of the filling column away from the stacked structure and a side wall close to the end of the filling column away from the stacked structure;

[0051] The forming of the semiconductor layer on the stack structure further includes: the semiconductor layer also covers an end of the filling column away from the stack structure and a side wall close to an end of the filling column away from the stack structure.

[0052] Through the above arrangement, part of the filling column is located in the semiconductor layer and connected to the semiconductor layer, so as to improve the stability of the semiconductor layer.

[0053] In some embodiments, after forming the semiconductor layer, the method further includes:

[0054] forming a second conductive hole on the connection area;

[0055] A second conductive column is formed in the second conductive hole, and a third insulating isolation layer is formed between the second conductive column and the semiconductor layer.

[0056] Through the above arrangement, the second conductive hole penetrates the insulating cover layer and the semiconductor layer to the connection structure, so that the second conductive column formed in the second conductive hole can be connected to the connection structure. The third insulating isolation layer can achieve insulation between the second conductive column and the semiconductor layer, one end of the second conductive column passes through the semiconductor layer and is connected to the connection structure, and the other end of the second conductive column is connected to the contact pad, which facilitates the connection between the semiconductor layer and the peripheral circuit.

[0057] On the other hand, an embodiment of the present application further provides a storage system, including a semiconductor structure and a controller, wherein the semiconductor structure is the semiconductor structure as described above; the controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0058] On the other hand, an embodiment of the present application further provides an electronic device, comprising the above storage system.

[0059] It can be understood that the beneficial effects that can be achieved by the semiconductor structure preparation method, storage system and electronic device provided by the above embodiments of the present application can refer to the beneficial effects of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the present invention, the following briefly introduces the drawings required to be used in some embodiments of the present invention. Obviously, the drawings described below are only drawings of some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present invention, the actual process of the method, the actual timing of the signal, etc.

[0061] Figure 1 A schematic diagram of a three-dimensional structure of a three-dimensional memory in some embodiments of the present invention;

[0062] Figure 2 A cross-sectional view of a three-dimensional memory in some embodiments of the present invention;

[0063] Figure 3 for Figure 1 A cross-sectional view of a memory cell string in the three-dimensional memory along the section line AA' shown;

[0064] Figure 4 is an equivalent circuit diagram of a memory cell string in some embodiments of the present invention;

[0065] Figure 5 Schematic cross-sectional view of a semiconductor structure in some embodiments of the present invention;

[0066] Figure 6 A flowchart of a method for preparing a semiconductor structure in some embodiments of the present invention;

[0067] Fig. 7A A schematic diagram of the structure after the substrate is removed in the method provided in an embodiment of the present invention;

[0068] Figure 7B A schematic diagram of the structure after a portion of the first dielectric layer and a portion of the second dielectric layer are removed in the method provided in an embodiment of the present invention;

[0069] Figure 7C A schematic diagram of the structure after an intermediate insulating isolation layer is formed in the method provided in an embodiment of the present invention;

[0070] Fig.7D A schematic diagram of the structure after a mask plate is formed in the method provided in an embodiment of the present invention;

[0071] Fig. 7EA schematic diagram of the structure after a portion of the intermediate insulating isolation layer is removed in the method provided in an embodiment of the present invention;

[0072] Figure 7F Schematic diagram of the structure after the semiconductor layer is formed in the method provided in the embodiment of the present invention Figure 1 ;

[0073] Figure 7G Schematic diagram of the structure after the semiconductor layer is formed in the method provided in the embodiment of the present invention Figure 2 ;

[0074] Figure 7H A schematic diagram of the structure after removing the mask plate in the method provided in an embodiment of the present invention;

[0075] Fig.7I Schematic diagram of the structure after the semiconductor layer is formed in the method provided in the embodiment of the present invention Figure 2 ;

[0076] Figure 7J A schematic diagram of the structure after an insulating covering layer is formed in the method provided in an embodiment of the present invention;

[0077] Figure 7K A schematic diagram of the structure after the first conductive pillar and the second conductive pillar are formed in the method provided in an embodiment of the present invention;

[0078] Figure 8 is a block diagram of a storage system according to some embodiments;

[0079] Fig. 9 is a block diagram of a storage system according to some other embodiments. DETAILED DESCRIPTION

[0080] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments provided by the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0081] In the description of the present invention, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0082] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present invention. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0083] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, unless otherwise specified, "plurality" means two or more.

[0084] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments invented here are not necessarily limited to the contents of this document.

[0085] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0086] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0087] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0088] In the context of the present invention, the meaning of "on", "above", and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" not only means "above" or "over" something, but also includes the meaning of "above" or "over" something without intervening features or layers in between (i.e., directly on something).

[0089] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0090] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0091] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0092] Please refer to Figure 1 and Figure 2 , the three-dimensional memory 10 extends in the XY plane, the first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (for example, the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the XY plane.

[0093] As used in the present invention, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate or source layer of the semiconductor device in a third direction Z when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concept is applied to describe spatial relationships throughout the present invention.

[0094] In order to more clearly illustrate the structure of the device, Figure 2 In the figure, a view of the array area CA and a view of the connection area SS are shown. The view of the array area CA is based on the left coordinate system, and the view of the connection area SS is based on the right coordinate system, that is, the view of the array area CA shows the cross-sectional structure along the Y direction, and the view of the connection area SS shows the cross-sectional structure along the X direction.

[0095] Reference Figure 1 and Figure 2 Some embodiments of the present invention provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The three-dimensional memory 10 may also include a peripheral device 100 coupled to the semiconductor structure 200. The semiconductor structure 200 includes a source layer SL, and the peripheral device 100 may be disposed on a side of the semiconductor structure 200 away from the source layer SL.

[0096] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0097] The semiconductor structure 200 may include memory cell transistor strings (referred to herein as “channel structures”) 40 arranged in an array. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 40 .

[0098] In some embodiments, please refer to Figure 3 and Figure 4 The memory cell string 40 may include a plurality of transistors T, a transistor T (eg Figure 4 The transistors T1 to T6 in the figure can be set as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor T (for example, each transistor T) can be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241. The gate line G is configured to control the conduction state of the transistor.

[0099] Understandably, Figure 1 to Figure 4The number of transistors is only illustrative, and the storage cell string of the three-dimensional memory provided by the embodiment of the present invention may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0100] In some embodiments, along the third direction Z, the gate line located at the bottom among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 40. The gate line located at the top among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 40. The gate line located in the middle among the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. Data writing, reading, and erasing of corresponding memory cells (for example, transistors T) in the memory cell string 40 can be completed through the word lines WL.

[0101] Continue to refer to Figure 1 and Figure 2 In some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 40. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 40, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 40.

[0102] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292, the contacts may include, for example, a bit line contact BL-CNT coupled to the bit line BL, and a drain select gate contact SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, for example, a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 291 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable materials.

[0103] The peripheral device 100 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0104] In some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120.

[0105] The material of the substrate 110 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0106] The peripheral interconnection layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnection layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled through contacts. The material of the second interconnect conductor layer 132 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0107] The peripheral interconnect layer 130 may be coupled to the array interconnect layer 290, so that the semiconductor structure 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuit in the peripheral device 100 may be coupled to the memory cell string in the semiconductor structure 200 to achieve transmission of electrical signals between the peripheral circuit and the memory cell string. In some possible implementations, a bonding interface 50 may be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, and the peripheral interconnect layer 130 and the array interconnect layer 290 may be bonded and coupled to each other through the bonding interface 50.

[0108] Please refer to Figure 5 The semiconductor structure 200 provided in the embodiment of the present invention may include a stacked structure 300, and one side of the stacked structure 300 is used to couple with the wafer layer 280. The wafer layer 280 includes a peripheral circuit wafer, which may also be called a complementary metal oxide semiconductor (CMOS) wafer. The CMOS wafer includes a peripheral circuit for signal transmission to the storage unit. The stacked structure 300 includes an array area CA and a connection area SS, and the array area CA and the connection area SS are adjacently arranged.

[0109] In the above implementation, the stacked structure 300 includes a plurality of dielectric layers 310 and a plurality of gate line layers 320 alternately stacked. In some embodiments, the dielectric layer 310 may include an insulating material, for example, at least one of silicon oxide and silicon oxynitride. The gate line layer 320 may include a conductive material, for example, at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide. A protective layer may also be provided between the dielectric layer 310 and the gate line layer 320, and the protective layer covers the gate line layer 320. The material of the protective layer may include a material with a high dielectric constant, for example, aluminum oxide (Al2O3), hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), silicon oxynitride (SiO x N y )wait.

[0110] Continue to refer to Figure 5 The semiconductor structure 200 may further include a first insulating isolation layer 610, which is located on a side of the stacking structure 300 away from the wafer layer 280 and covers the connection area SS of the stacking structure 300; the first insulating isolation layer 610 may include an insulating material, for example, at least one of silicon oxide and silicon oxynitride.

[0111] Continue to refer to Figure 5 The semiconductor structure 200 may further include a semiconductor layer 620, which is located on a side of the stack structure 300 away from the wafer layer 280 and covers the array area CA of the stack structure 300. The semiconductor layer 620 may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0112] Continue to refer to Figure 5The semiconductor structure 200 may further include a channel structure 500, the channel structure 500 including a first channel structure 510 located in the array area CA and a second channel structure 520 located in the connection area SS, wherein both the first channel structure 510 and the second channel structure 520 penetrate the stack structure and extend toward a side of the stack structure 300 away from the wafer layer 280. In the implementation mode in which the semiconductor structure 200 includes a first insulating isolation layer 610 and a semiconductor layer 620, an end of the first channel structure 510 away from the stack structure 300 is connected to the semiconductor layer 620; an end of the second channel structure 520 away from the stack structure 300 is located in the first insulating isolation layer 610, and the first insulating isolation layer 610 wraps a portion of the second channel structure 520 extending out of the stack structure 300.

[0113] In the above implementation, the first channel structure 510 includes a first semiconductor column 511 and a first dielectric layer 512, wherein the first semiconductor column 511 passes through the stacking structure 300, and one end of the first semiconductor column 511 away from the stacking structure 300 is located in the semiconductor layer 620 and connected to the semiconductor layer 620; the first dielectric layer 512 is located between the first semiconductor column 511 and the stacking structure 300, and the first dielectric layer 512 can form a transistor T with the gate line layer 320 in the stacking structure 300 to realize the storage function of the channel structure 500.

[0114] Continue to refer to Figure 5 The second channel structure 520 includes a second semiconductor column 521 and a second dielectric layer 522, wherein the second semiconductor column 521 passes through the stack structure 300, and one end of the second semiconductor column 521 away from the stack structure 300 is located in the first insulating isolation layer 610, and the first insulating isolation layer 610 wraps the portion of the second semiconductor column 521 extending out of the stack structure 300; the second dielectric layer 522 is located between the second semiconductor column 521 and the stack structure 300, and the second dielectric layer 522 can form a transistor T with the gate line layer 320 in the stack structure 300 to realize the storage function of the channel structure 500.

[0115] Reference Figure 5 and Fig. 7A In the process of forming the semiconductor structure 200, after removing the substrate, the end of the second channel structure 520 away from the wafer layer 280 is prone to wear. In the process of removing the first intermediate layer 750, the second dielectric layer 522 in the second channel structure 520 will be removed at the same time, so that a hole is formed at the position of the second dielectric layer 522 to expose the gate line layer 320 used to form the transistor T with the second dielectric layer 522. In the process of forming the semiconductor layer 620, the semiconductor layer 620 can be directly connected to the gate line layer 320 through the hole at the position of the second dielectric layer 522, so that leakage occurs in the second channel structure 520.

[0116] The semiconductor structure 200 provided in the embodiment of the present application includes a stacked structure 300 and a channel structure 500 penetrating the stacked structure 300, the stacked structure 300 includes an array area CA and a connection area SS, the channel structure 500 includes a first channel structure 510 located in the array area CA and a second channel structure 520 located in the connection area SS, the semiconductor structure 200 also includes a first insulating isolation layer 610 covering the stacked structure 300, and a semiconductor layer 620 located on a side of the first insulating isolation layer 610 away from the stacked structure 300, and the first channel structure 510 has a first channel structure 510 disposed in the array area CA. The first semiconductor column 511 passes through the first insulating isolation layer 610 to connect with the semiconductor layer 620, and the second semiconductor column 521 of the second channel structure 520 is located in the first insulating isolation layer 610, so that the first insulating isolation layer 610 can fill the hole formed at the position of the second dielectric layer 522, that is, the first insulating isolation layer 610 can prevent the semiconductor layer 620 from being directly connected to the gate line layer 320 at the second channel structure 520, thereby avoiding the leakage of the second channel structure 520 affecting the storage function of the first channel structure 510, thereby improving the yield rate of the semiconductor structure 200.

[0117] In the above implementation, the first semiconductor pillar 511 and the second semiconductor pillar 521 may include at least one of polycrystalline silicon or single crystal silicon.

[0118] In the above implementation, the first semiconductor column 511 may be a solid column or a hollow column. When the first semiconductor column 511 is a hollow column, the first semiconductor column 511 may further include a support portion, and the support portion may be located inside the first semiconductor column 511, that is, the first semiconductor column 511 surrounds the support portion, and the support portion may provide support for the channel structure 500. The support portion may include an insulating material, such as silicon oxide. It should be noted that the structure of the second semiconductor column 521 is similar to that of the first semiconductor column.

[0119] Continue to refer to Figure 5In the implementation method in which the semiconductor structure 200 includes a first insulating isolation layer 610, the first insulating isolation layer 610 can cover the entire stack structure 300, that is, the first insulating isolation layer 610 can cover the connection area SS and the array area CA of the stack structure 300; and the semiconductor layer 620 is located on the side of the first insulating isolation layer 610 away from the stack structure 300, and the semiconductor layer 620 can also cover the entire or part of the stack structure 300. For example, the semiconductor layer 620 can only cover the array area CA of the stack structure 300; or the semiconductor layer 620 can cover the connection area SS and the array area CA of the stack structure 300, that is, the projection of the semiconductor layer 620 onto the stack structure 300 covers the first insulating isolation layer 610. Compared with the embodiment in which the semiconductor layer 620 only covers the array area CA of the stack structure 300, the embodiment in which the semiconductor layer 620 covers the entire stack structure 300 simplifies the process of forming the semiconductor layer 620.

[0120] In the above implementation, one end of the first semiconductor column 511 away from the wafer layer 280 passes through the first insulating isolation layer 610 , and a portion of the first semiconductor column 511 located on a side of the first insulating isolation layer 610 away from the stacked structure 300 is connected to the semiconductor layer 620 .

[0121] Continue to refer to Figure 5 In the embodiment of the present application, the semiconductor structure 200 further includes a connection structure 400, the connection structure 400 is located in the connection area SS, and the connection structure 400 is located on the side of the channel structure 500 away from the array area CA, and the connection structure 400 penetrates the stack structure 300. The connection structure 400 may include a through array contact (Through Array Contact, TAC), and a through array barrier structure (Through Array Barrier, TAB) is provided between the TAC and the gate line layer in the stack structure, and the TAB is used to achieve insulation between the TAC and the gate line layer 320 in the stack structure 300, and the TAC is used to electrically connect the stack structure with the peripheral circuit.

[0122] Continue to refer to Figure 5 In the above implementation, the first dielectric layer 512 may include a blocking layer, a storage layer and a tunneling layer, which are arranged sequentially in the direction from the first semiconductor column 511 to the stacked structure 300, wherein the tunneling layer covers the side wall of the first semiconductor column 511, the storage layer is located between the tunneling layer and the blocking layer, and the blocking layer is located between the storage layer and the stacked structure 300.

[0123] It should be noted that the structure of the second dielectric layer 522 is similar to that of the first dielectric layer 512 , and the second dielectric layer 522 may include a blocking layer, a storage layer and a tunneling layer, which are arranged sequentially in a direction from the second semiconductor column 521 to the stacked structure 300 .

[0124] Exemplarily, the barrier layer may include at least one of silicon oxide and metal oxide; the storage layer may include at least one of silicon nitride and silicon oxynitride; and the tunneling layer may include at least one of silicon oxide and metal oxide.

[0125] Continue to refer to Figure 5 In the embodiment of the present application, the semiconductor structure 200 may further include an insulating cover layer 710, the insulating capping layer covers the semiconductor layer 620 to form a flat surface, and a contact pad 720 is formed at one end of the insulating cover layer 710 away from the stacking structure 300, so as to facilitate the connection between the semiconductor layer 620 and the peripheral circuit. The semiconductor structure 200 also includes a first conductive column 730, the first conductive column 730 penetrates the insulating cover layer 710, one end of the first conductive column 730 extends to the semiconductor layer 620 and is connected to the semiconductor layer 620, and the other end of the first conductive column 730 is connected to the contact pad 720, so as to facilitate the connection between the semiconductor layer 620 and the peripheral circuit.

[0126] In the above implementation, the first conductive pillar 730 is located in the array area CA and is connected to a portion of the semiconductor layer 620 located in the array area CA. The above configuration can shorten the length of the current from the first conductive pillar 730 to the first semiconductor pillar 511, thereby reducing resistance.

[0127] Continue to refer to Figure 5 In the embodiment of the present application, the semiconductor structure 200 may further include an isolation structure 800. A plurality of isolation structures 800 may be provided. The plurality of isolation structures 800 may penetrate the connection area SS, may penetrate the array area CA, or may be arranged at intervals in the connection area SS and the array area CA. The isolation structure 800 may support the stacking structure 300 to improve the stability of the semiconductor structure 200.

[0128] In the above embodiment, the isolation structure 800 includes a filling column 810 and a second insulating isolation layer 820. The filling column 810 can support the semiconductor structure 200. The filling column 810 can include at least one of metal (e.g., tungsten, copper, aluminum, etc.), metal silicide, metal nitride, and doped polysilicon. The second insulating isolation layer 820 is disposed between the filling column 810 and the sidewall of the stacked structure 300. The second insulating isolation layer 820 can include at least one of silicon oxide and metal oxide. The filling column 810 runs through the stacked structure 300, and one end of the filling column 810 away from the stacked structure 300 passes through the first insulating isolation layer 610. The portion of the filling column 810 located on the side of the first insulating isolation layer 610 away from the stacked structure 300 is located in the semiconductor layer 620 and connected to the semiconductor layer 620 to improve the stability of the semiconductor layer 620.

[0129] Continue to refer to Figure 5 In the implementation manner in which the semiconductor structure 200 includes the first conductive column 730, the diameter of the first semiconductor column 511 is smaller than the diameter of the filling column 810, and the top area of ​​the isolation structure 800 is larger, and the area of ​​the semiconductor layer 620 corresponding to the isolation structure 800 is large. The first conductive column 730 is connected to the semiconductor layer 620 corresponding to the isolation structure 800, which increases the connection area between the first conductive column 730 and the semiconductor layer 620 and improves the stability of the connection between the first conductive column 730 and the semiconductor layer 620.

[0130] Continue to refer to Figure 5 In the embodiment of the present application, the semiconductor structure 200 may further include a second conductive pillar 740, the second conductive pillar 740 passes through the insulating cover layer 710 and the semiconductor layer 620, a third insulating isolation layer 770 is arranged between the second conductive pillar 740 and the semiconductor layer 620, the third insulating isolation layer 770 can achieve insulation between the second conductive pillar 740 and the semiconductor layer 620, one end of the second conductive pillar 740 passes through the semiconductor layer 620 and is connected to the connection structure 400, and the other end of the second conductive pillar 740 is connected to the contact pad 720, so as to facilitate the connection between the semiconductor layer 620 and the peripheral circuit.

[0131] The present invention also provides a method for preparing a semiconductor structure. Figure 6 The preparation method may include steps S100-S400:

[0132] S100: forming a stacking structure, the stacking structure comprising an array region and a connection region, the array region and the connection region being arranged adjacent to each other; a first channel structure and a second channel structure penetrating the stacking structure are arranged on the stacking structure, the first channel structure is located in the array region, and the second channel structure is located in the connection region; the first channel structure comprises a first semiconductor column and a first dielectric layer wrapping the first semiconductor column; the second channel structure comprises a second semiconductor column and a second dielectric layer wrapping the second semiconductor column.

[0133] Please refer to Fig. 7A In step S100, forming the stack structure 300 may include:

[0134] A plurality of dielectric layers 310 and a plurality of sacrificial layers are alternately stacked on the substrate by a thin film deposition process to form a stacked structure.

[0135] The thin film deposition process may include a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and electroplating processes.

[0136] “Alternate stacking” means that after a dielectric layer 310 is formed on the substrate, a sacrificial layer is formed on the dielectric layer 310 , and then another dielectric layer 310 is formed on the sacrificial layer, and then the above steps are repeated.

[0137] After the stacked structure is formed, a channel hole is also formed on the stacked structure. The channel hole can be formed in the array area CA or in the connection area SS. The channel hole can be formed by etching. The etched channel hole extends into the substrate to ensure that the channel structure 500 formed in the channel hole can pass through the initial stacked structure 300.

[0138] In the process of forming the first channel structure 510 in the channel hole located in the array area CA, a first dielectric layer 512 is formed on the hole wall of the channel hole, and a first semiconductor column 511 is formed on the first dielectric layer 512, and the first semiconductor column 511 surrounds the hole. Then, a support portion is filled in the hole. The support portion can support the channel structure 500 and improve the stability of the channel structure 500. Similarly, in the process of forming the second channel structure 520 in the channel hole located in the connection area SS, a second dielectric layer 522 is formed on the hole wall of the channel hole, and a second semiconductor column 521 is formed on the second dielectric layer 522.

[0139] After forming the channel structure 500, a plurality of gate gaps may be formed on the stacked structure, wherein some gate gaps are located in the array area CA and some gate gaps are located in the connection area SS. The gate gaps penetrate the alternately stacked multiple dielectric layers 310 and multiple sacrificial layers and extend into the substrate.

[0140] The sacrificial layer is replaced with a gate line layer 320 through the gate gap to form a stacked structure 300 .

[0141] After the stack structure 300 is formed, an isolation structure 800 is formed in the gate gap. Since the gate gap penetrates the alternately stacked multiple dielectric layers 310 and multiple sacrificial layers and extends into the substrate, one end of the isolation structure 800 is located in the substrate.

[0142] After forming the stack structure 300 , the process may further include forming a connection structure 400 in the stack structure 300 , wherein the connection structure 400 penetrates the stack structure 300 .

[0143] After the stack structure 300 is formed, the stack structure 300 may be coupled to the wafer layer 280 , such that the substrate is located on top and the stack structure 300 is located between the substrate and the wafer layer 280 .

[0144] Continue to refer to Fig. 7A After forming the stack structure 300, a portion of the substrate is removed, and the remaining portion of the substrate is used as the first intermediate layer 750 to expose one end of the first channel structure extending into the substrate and one end of the second channel structure extending into the substrate. At the same time, one end of the isolation structure extending into the substrate is exposed.

[0145] After removing the substrate, the method provided in the embodiment of the present application may further include:

[0146] S200: removing a portion of the first dielectric layer of the first channel structure away from one end of the stack structure and a portion of the second dielectric layer of the second channel structure away from one end of the stack structure.

[0147] In step S200, a portion of the first dielectric layer 512 and a portion of the second dielectric layer 522 may be removed by etching. Fig. 7A and Figure 7B The etching direction is parallel to the stack structure 300. In some embodiments, the etching may include ONO RM to sequentially remove oxide, nitride, and oxide.

[0148] Exemplarily, etching may include:

[0149] The first step of removing oxide can remove the first intermediate layer 750, a portion of the blocking layer in the first dielectric layer 512, and a portion of the blocking layer in the second dielectric layer 522. In the implementation in which the semiconductor structure 200 includes an isolation structure 800, the first step of removing oxide can also remove a portion of the second insulating isolation layer 820 to expose an end of the filling column 810 away from the stacked structure 300 and a sidewall near an end of the filling column 810 away from the stacked structure 300.

[0150] The second step of removing the nitride can remove a portion of the storage layer in the first dielectric layer 512 and a portion of the storage layer in the second dielectric layer 522 .

[0151] The third step of removing oxide can remove a portion of the tunneling layer in the first dielectric layer 512 and a portion of the tunneling layer in the second dielectric layer 522 .

[0152] After removing part of the first dielectric layer 512 and part of the second dielectric layer 522, part of the first semiconductor pillar 511 and part of the second semiconductor pillar 521 are exposed on a side of the stacked structure 300 away from the wafer layer 280. The method provided in the embodiment of the present application may further include:

[0153] S300: forming an intermediate insulating isolation layer on the stack structure, removing a portion of the intermediate insulating isolation layer to form a first insulating isolation layer, and an end of the first semiconductor column away from the stack structure is located on a side of the first insulating isolation layer away from the stack structure.

[0154] Please refer to Figure 7C In step S300, the process may include: forming an intermediate insulating isolation layer 611 on the stacked structure 300, wherein the intermediate insulating isolation layer 611 covers the array area CA and the connection area SS. After the intermediate insulating isolation layer 611 is formed, the intermediate insulating isolation layer 611 covers the first semiconductor pillar 511 located in the array area CA and covers the second semiconductor pillar 521 located in the connection area SS to cover the leakage of the second channel structure 520.

[0155] Please refer to Fig.7D After forming the intermediate insulating isolation layer 611, a mask plate 760 may be formed on the intermediate insulating isolation layer 611, and the formed mask plate 760 covers the connection region SS.

[0156] Please refer to Fig. 7EAfter forming the mask plate 760, part of the intermediate insulating isolation layer 611 is removed. Since the mask plate 760 only covers the connection area SS, the intermediate insulating isolation layer 611 located in the connection area SS will not be removed. After removing part of the intermediate insulating isolation layer located in the array area, the remaining part of the intermediate insulating isolation layer 611 serves as the first insulating isolation layer 610, so that the end of the first semiconductor column 511 away from the stack structure 300 is located on the side of the first insulating isolation layer 610 away from the stack structure 300, which facilitates the connection between the first semiconductor columns 511.

[0157] S400: forming a semiconductor layer on the first insulating isolation layer, wherein the semiconductor layer covers an end of the first semiconductor column away from the stack structure.

[0158] Please refer to Figure 7F In some embodiments, after removing part of the intermediate insulating isolation layer 611 located in the array area CA, the semiconductor layer 620 can be formed only in the array area CA. Through the above configuration, the material for forming the semiconductor layer 620 is reduced while multiple first channel structures 510 can be connected to each other.

[0159] Please refer to Figure 7G In the above implementation, an insulating cover layer 710 is formed on the semiconductor layer 620, and a first conductive hole is formed on the insulating cover layer 710, wherein the bottom of the first conductive hole is located on the semiconductor layer;

[0160] A first conductive column 730 is formed in the first conductive hole, and the first conductive column 730 is connected to the semiconductor layer 620 .

[0161] A second conductive hole is formed on the connection region; the second conductive hole penetrates the insulating cover layer 710 and the semiconductor layer 620 to the connection structure 400 , so that the second conductive column 740 formed in the second conductive hole can be connected to the connection structure 400 .

[0162] Please refer to Figure 7H In some other embodiments, after removing a portion of the intermediate insulating isolation layer 611 located in the array area CA, the mask plate 760 may be removed first to expose the first insulating isolation layer 610 .

[0163] Please refer to Fig.7I, a semiconductor layer 620 is formed on the first insulating isolation layer 610, and the semiconductor layer 620 covers the array area CA and the connection area SS. Since one end of a portion of the first semiconductor column 511 away from the stacked structure 300 is located on a side of the first insulating isolation layer 610 away from the stacked structure 300, during the process of forming the semiconductor layer 620, a portion of the first semiconductor column 511 is located in the semiconductor layer 620, and both the first semiconductor column 511 and the semiconductor layer 620 may include single crystal silicon or polycrystalline silicon, thereby achieving connection between the first semiconductor column 511 and the semiconductor layer 620.

[0164] Compared with the implementation method of forming the semiconductor layer 620 only in the array area CA, the implementation method of forming the semiconductor layer 620 in both the array area CA and the connection area SS after removing the mask plate 760 does not need to limit the formation position of the semiconductor layer 620, thereby simplifying the steps of forming the semiconductor layer 620.

[0165] In the implementation manner in which the semiconductor structure 200 includes the isolation structure 800, forming the semiconductor layer 620 on the first insulating isolation layer 610 further includes that the formed semiconductor layer 620 also covers an end of the filling column 810 away from the stacked structure 300 and a sidewall close to an end of the filling column 810 away from the stacked structure 300. Part of the filling column 810 is located in the semiconductor layer 620 and connected to the semiconductor layer 620 to improve the stability of the semiconductor layer 620.

[0166] The semiconductor structure 200 prepared according to the semiconductor structure preparation method provided in the embodiment of the present application includes a stacked structure 300 and a channel structure 500 penetrating the stacked structure 300, the stacked structure 300 includes an array area CA and a connection area SS, the channel structure 500 includes a first channel structure 510 located in the array area CA and a second channel structure 520 located in the connection area SS, the semiconductor structure 200 also includes a first insulating isolation layer 610 covering the stacked structure 300, and a semiconductor layer 620 located on a side of the first insulating isolation layer 610 away from the stacked structure 300, the first channel structure 510 includes a first channel structure 510 located in the array area CA and a second channel structure 520 located in the connection area SS, The first semiconductor column 511 of the channel structure 510 passes through the first insulating isolation layer 610 to connect with the semiconductor layer 620, and the second semiconductor column 521 of the second channel structure 520 is located in the first insulating isolation layer 610, so that the first insulating isolation layer 610 can fill the hole formed at the position of the second dielectric layer 522, that is, the first insulating isolation layer 610 can prevent the semiconductor layer 620 from being directly connected to the gate line layer 320 at the second channel structure 520, thereby avoiding the leakage of the second channel structure 520 affecting the storage function of the first channel structure 510, thereby improving the yield rate of the semiconductor structure 200.

[0167] After forming the semiconductor layer 620, the semiconductor structure manufacturing method further includes:

[0168] Please refer to Figure 7J and Figure 7K , forming an insulating cover layer 710 on the semiconductor layer 620, and forming a first conductive hole on the insulating cover layer 710, wherein the bottom of the first conductive hole is located on the semiconductor layer;

[0169] A first conductive column 730 is formed in the first conductive hole, and the first conductive column 730 is connected to the semiconductor layer 620 .

[0170] Through the above arrangement, one end of the first conductive column 730 extends to and is connected to the semiconductor layer 620 , and the other end of the first conductive column 730 is connected to the contact pad 720 , thereby facilitating the connection between the semiconductor layer 620 and the peripheral circuit.

[0171] Continue to refer to Figure 7K In the implementation mode in which the semiconductor structure 200 includes the isolation structure 800, the step of forming the first conductive hole on the insulating cover layer 710 may include: forming the first conductive hole on the insulating cover layer 710 corresponding to the isolation structure 800. Through the above arrangement, the first conductive column 730 formed in the first conductive hole can be connected to the semiconductor layer 620 corresponding to the isolation structure 800. Compared with the connection between the first conductive column 730 and the semiconductor layer 620 corresponding to the first semiconductor column 511, the diameter of the filling column 810 is larger than the diameter of the first semiconductor column 511, so the connection between the first conductive column 730 and the semiconductor layer 620 corresponding to the isolation structure 800 can increase the connection area between the first conductive column 730 and the semiconductor layer 620, and improve the stability of the connection between the first conductive column 730 and the semiconductor layer 620.

[0172] Continue to refer to Figure 7K The method for preparing the semiconductor structure provided in the embodiment of the present application may further include:

[0173] A second conductive hole is formed on the connection region; the second conductive hole penetrates the insulating cover layer 710 and the semiconductor layer 620 to the connection structure 400 , so that the second conductive column 740 formed in the second conductive hole can be connected to the connection structure 400 .

[0174] A second conductive column 740 is formed in the second conductive hole, and a third insulating isolation layer 770 is formed between the second conductive column 740 and the semiconductor layer 620 .

[0175] Through the above-mentioned setting, the third insulating isolation layer 770 can realize the insulation between the second conductive column 740 and the semiconductor layer 620. One end of the second conductive column 740 passes through the semiconductor layer 620 and is connected to the connection structure 400. The other end of the second conductive column 740 is connected to the contact pad 720, which facilitates the connection between the semiconductor layer 620 and the peripheral circuit.

[0176] Please refer to Figure 8 and Fig. 9 Some embodiments of the present invention further provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10, wherein the three-dimensional memory 10 may include the semiconductor structure 200 as described above, and the controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0177] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0178] In some embodiments, reference Figure 8 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0179] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0180] In other embodiments, reference Fig. 9 The storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0181] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0182] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0183] In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes regarding data read from or written to the three-dimensional memory 10.

[0184] Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0185] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0186] Some embodiments of the present invention further provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0187] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0188] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A stacking structure, the stacking structure comprising an array region and a connection region, the array region and the connection region being arranged adjacent to each other; A channel structure, the channel structure comprising a first channel structure and a second channel structure, the first channel structure and the second channel structure both penetrate the stacked structure, the first channel structure is located in the array region, the second channel structure is located in the connection region, the first channel structure comprises a first semiconductor column, and the second channel structure comprises a second semiconductor column; a first insulating isolation layer, wherein the first insulating isolation layer covers the stack structure, an end of the first semiconductor column away from the stack structure passes through the first insulating isolation layer, and an end of the second semiconductor column away from the stack structure is located in the first insulating isolation layer; A semiconductor layer is connected to a portion of the first semiconductor column located on a side of the first insulating isolation layer away from the stacked structure.

2. The semiconductor structure according to claim 1, characterized in that: A projection of the semiconductor layer onto the stacked structure covers the first insulating isolation layer.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The semiconductor structure further comprises: an insulating cover layer, the insulating cover layer covers the semiconductor layer; A first conductive column, wherein the first conductive column penetrates the insulating cover layer and is connected to the semiconductor layer.

4. The semiconductor structure according to claim 3, characterized in that: The first conductive pillar is connected to a portion of the semiconductor layer located in the array region.

5. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further includes an isolation structure, and the isolation structure penetrates the array region; the first conductive pillar is connected to the semiconductor layer corresponding to the isolation structure.

6. The semiconductor structure according to claim 1 or 2, characterized in that: The isolation structure includes a filling column and a second insulating isolation layer covering the filling column, and one end of the filling column away from the stacking structure is connected to the semiconductor layer.

7. The semiconductor structure according to claim 1 or 2, characterized in that: The semiconductor structure further includes a second conductive column, the second conductive column penetrates the semiconductor layer, and a third insulating isolation layer is disposed between the second conductive column and the semiconductor layer.

8. The semiconductor structure according to claim 7, characterized in that: The semiconductor structure further includes a connection structure, wherein the connection structure penetrates the stack structure and is located in the connection region, and the second conductive column is connected to the connection structure.

9. The semiconductor structure according to claim 1 or 2, characterized in that: The first channel structure further includes a first dielectric layer, which is located between the first semiconductor column and the stacked structure; the second channel structure further includes a second dielectric layer, which is located between the second semiconductor column and the stacked structure.

10. A method for preparing a semiconductor structure, characterized in that: include: forming a stacking structure, wherein the stacking structure comprises an array region and a connection region, wherein the array region and the connection region are adjacently arranged; The stacked structure is provided with a first channel structure and a second channel structure penetrating the stacked structure, the first channel structure is located in the array region, and the second channel structure is located in the connection region; the first channel structure includes a first semiconductor column and a first dielectric layer wrapping the first semiconductor column; the second channel structure includes a second semiconductor column and a second dielectric layer wrapping the second semiconductor column; removing a portion of the first dielectric layer of the first channel structure away from one end of the stack structure and a portion of the second dielectric layer of the second channel structure away from one end of the stack structure; forming an intermediate insulating isolation layer on the stacked structure, removing a portion of the intermediate insulating isolation layer to form a first insulating isolation layer, and an end of the first semiconductor column away from the stacked structure is located on a side of the first insulating isolation layer away from the stacked structure; A semiconductor layer is formed on the first insulating isolation layer, wherein the semiconductor layer covers an end of the first semiconductor column away from the stack structure.

11. The method according to claim 10, characterized in that The step of forming an intermediate insulating isolation layer on the stacked structure, removing a portion of the intermediate insulating isolation layer to form a first insulating isolation layer, and locating an end of the first semiconductor column away from the stacked structure on a side of the first insulating isolation layer away from the stacked structure comprises: forming an intermediate insulating isolation layer on the stacked structure, wherein the intermediate insulating isolation layer covers the array region and the connection region; forming a mask plate on the intermediate insulating isolation layer, wherein the mask plate covers the connection area; A portion of the intermediate insulating isolation layer located in the array region is removed so that an end of the first semiconductor column away from the stack structure is located on a side of the first insulating isolation layer away from the stack structure.

12. The method according to claim 11, characterized in that The step of forming a semiconductor layer on the first insulating isolation layer, wherein the semiconductor layer covers an end of the first semiconductor column away from the stacked structure, comprises: After removing the portion of the intermediate insulating isolation layer located in the array region, the semiconductor layer is formed in the array region.

13. The method according to claim 11, characterized in that The step of forming a semiconductor layer on the first insulating isolation layer, wherein the semiconductor layer covers an end of the first semiconductor column away from the stacked structure, comprises: After removing the portion of the intermediate insulating isolation layer located in the array area, removing the mask plate; The semiconductor layer is formed, and the semiconductor layer covers the array region and the connection region.

14. The method according to any one of claims 10 to 13, characterized in that: After forming the semiconductor layer, the semiconductor structure manufacturing method further includes: forming an insulating covering layer on the semiconductor layer, and forming a first conductive hole on the insulating covering layer, wherein the bottom of the first conductive hole is located on the semiconductor layer; A first conductive column is formed in the first conductive hole, and the first conductive column is connected to the semiconductor layer.

15. The method according to claim 14, characterized in that Forming a stacked structure also includes: forming an isolation structure on the array region; Forming a first conductive hole on the insulating cover layer includes: forming a first conductive hole on the insulating cover layer corresponding to the isolation structure.

16. The method according to claim 15, characterized in that The isolation structure includes a filling column and a second insulating isolation layer covering the filling column; Before forming a semiconductor layer on the stacked structure, the method further includes: removing a portion of the second insulating isolation layer to expose an end of the filling column away from the stacked structure and a side wall close to an end of the filling column away from the stacked structure; The forming of the semiconductor layer on the stacked structure further includes: the semiconductor layer also covers an end of the filling column away from the stacked structure and a side wall close to an end of the filling column away from the stacked structure.

17. The method according to any one of claims 10 to 13, characterized in that: After forming the semiconductor layer, the method further comprises: forming a second conductive hole on the connection area; A second conductive column is formed in the second conductive hole, and a third insulating isolation layer is formed between the second conductive hole and the hole wall of the second conductive hole.

18. A storage system, characterized in that: include: The semiconductor structure according to any one of claims 1 to 9; A controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

19. An electronic device, characterized in that: Comprising the storage system as claimed in claim 18.

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