Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to save process time and simplify preparation steps. The semiconductor structure comprises a first dielectric layer, a stacking structure, a first channel layer located in the first dielectric layer, a second channel layer penetrating through the stacking structure, a connecting line located in the first dielectric layer and a top selection gate connected to the connecting line, wherein the first dielectric layer and the stacking structure are arranged in a stacked mode. The stacked structure comprises a plurality of second dielectric layers and a plurality of gate layers, and the second dielectric layers and the gate layers are arranged in an overlapping manner. The top selection gate is located on the side, close to the stacking structure, of the connecting line, and the first channel layer surrounds the top selection gate. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] As the feature size of the memory cell approaches the process lower limit, the planar process and manufacturing technology become challenging and costly, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases the storage density by arranging the memory cells three-dimensionally on the substrate.

[0003] In a three-dimensional memory, the three-dimensional memory can be divided into multiple memory blocks by setting a partitioned top selective gate (TSG) and a top select gate cut (TSG cut). Partition control is implemented to increase the number of effective channel holes (CH) and the storage density of the three-dimensional memory.

[0004] However, the process of preparing the top selection gate cut line is difficult and complicated. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, a storage system, and an electronic device, aiming to save process time and simplify the manufacturing steps.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a semiconductor structure is provided. The semiconductor structure includes a first dielectric layer and a stacked structure, a first channel layer located in the first dielectric layer, a second channel layer penetrating the stacked structure, a connecting line located in the first dielectric layer, and a top selection gate connected to the connecting line. The stacked structure includes a plurality of second dielectric layers and a plurality of gate layers, and the second dielectric layers and the gate layers are overlapped. The top selection gate is located on a side of the connecting line close to the stacked structure, and the first channel layer surrounds the top selection gate.

[0008] In the semiconductor structure provided by the above-mentioned embodiment of the present disclosure, the first channel layer surrounds the top selection gate (the top selection gate is located in the first channel layer), and the top selection gate is connected by a connecting wire to realize separate control of the top selection gate. In addition, since the top selection gate is located on the side of the connecting wire close to the stacked structure, that is, the top selection gate and the connecting wire are arranged along the thickness direction of the stacked structure, the size of the semiconductor structure in the direction perpendicular to the thickness direction of the stacked structure and perpendicular to the extension direction of the connecting wire is reduced. In the semiconductor structure provided by the embodiment of the present application, the first channel layer and the second channel layer are connected, which avoids the influence of dry etching plasma damage on the channel, thereby improving the channel performance.

[0009] In some embodiments, along the first direction, the connecting line passes through the first channel layer; a first dimension of the connecting line located between adjacent top selection gates in the second direction is smaller than a second dimension of the top selection gate in the second direction; the first direction is an extension direction of the connecting line, the second direction is perpendicular to the first direction, and a plane formed by the first direction and the second direction is parallel to the plane where the stacking structure is located.

[0010] In some embodiments, the ratio of the first size to the second size ranges from 0.5 to 1.

[0011] In some embodiments, the semiconductor structure includes a plurality of first channel layers; the plurality of first channel layers are arranged into at least two channel rows, and the first channel layers in the channel rows are arranged at intervals along the extension direction of the connecting line; the at least two channel rows include adjacent first channel rows and second channel rows; along the second direction, a plurality of top selection gates are distributed on both sides of the connecting line, and the second direction is a direction perpendicular to the extension direction of the connecting line; the top selection gates distributed on one side of the connecting line are located in the first channel layer in the first channel row; the top selection gates distributed on the other side of the connecting line are located in the first channel layer in the second channel row.

[0012] In some embodiments, the first channel layers in the first channel row and the first channel layers in the second channel row are alternately arranged.

[0013] In some embodiments, the first channel layer includes a first portion and a second portion, the first portion is a portion of the first channel layer covered by the connection line, and the second portion is a portion of the first channel layer other than the first portion.

[0014] In some embodiments, along a direction perpendicular to the extending direction of the connection line, a ratio of a size of the first portion to a size of the second portion ranges from 0.25 to 1.

[0015] In some embodiments, an end of the second portion away from the stacking structure exceeds the connecting line.

[0016] In some embodiments, the semiconductor structure includes a plurality of connection lines, and the plurality of connection lines are spaced apart from each other, so that the semiconductor structure can be partitioned by the plurality of connection lines.

[0017] In some embodiments, the first channel layer is disposed between the top select gate and the first dielectric layer.

[0018] In some embodiments, the semiconductor structure further includes a gate oxide layer, wherein the gate oxide layer is located between the first channel layer and the top select gate.

[0019] In some embodiments, the semiconductor structure further includes a third dielectric layer and a bit line contact structure located in the third dielectric layer; the third dielectric layer is located on a side of the first dielectric layer away from the stacking structure, and the bit line contact structure is connected to the first channel layer.

[0020] In some embodiments, the bit line contact structure penetrates the third dielectric layer and is connected to the second portion of the first channel layer.

[0021] In some embodiments, the connection line and the bit line contact structure are isolated by a fourth dielectric layer.

[0022] In some embodiments, the first channel layer and the second channel layer are close to each other and have the same size at both ends.

[0023] In some embodiments, the first channel layer extends to a side of the top select gate close to the stack structure.

[0024] In some embodiments, along a direction perpendicular to a thickness direction of the stacked structure, a maximum dimension of the first channel layer is greater than a maximum dimension of the second channel layer.

[0025] In some embodiments, the semiconductor structure further includes a third dielectric layer and a top selection gate contact structure located in the third dielectric layer; the third dielectric layer is located on a side of the first dielectric layer away from the stacking structure, and the top selection gate contact structure is connected to the connection line.

[0026] In some embodiments, the semiconductor structure further includes a bit line contact structure; the bit line contact structure is located in the third dielectric layer and connected to the first channel layer; and the material of the top selection gate contact structure is the same as that of the bit line contact structure.

[0027] On the other hand, a method for preparing a semiconductor structure is provided, comprising: providing a first dielectric layer and a stacking structure arranged in a stacked manner; the stacking structure comprises a plurality of second dielectric layers and a plurality of gate layers, the second dielectric layers and the gate layers being arranged in an overlapping manner; the first dielectric layer comprises a first channel structure, and the stacking structure comprises a second channel structure; the first channel structure penetrates the first dielectric layer, the first channel structure comprises a first channel layer and a first channel dielectric located in the first channel layer; the second channel structure penetrates the stacking structure, the second channel structure comprises a second channel layer and a second channel dielectric located in the second channel layer; the first channel layer is connected to the second channel layer; a connecting groove is provided on a surface of the first dielectric layer away from the stacking structure; along the thickness direction of the stacking structure, the connecting groove overlaps with a portion of the first channel structure; at least a portion of the first channel dielectric is removed; and a conductive structure is formed in the connecting groove, the conductive structure comprising: a top selection gate filled in the first channel layer, and a connecting line connected to the top selection gate.

[0028] The method for preparing a semiconductor structure provided by the above-mentioned embodiment of the present disclosure forms a top selection gate in the first channel layer, and forms the top selection gate and a connecting line connecting the top selection gate in the same process step, thereby saving preparation process steps, simplifying the process flow, and reducing preparation costs. At the same time, since a conductor structure is filled in the connecting groove to form a top selection gate and a connecting line connected to the top selection gate, and the pattern shape of the connecting line can be defined by the shape of the connecting groove, that is, it can be formed without using a photolithography process, thus saving the mask layer required for preparation, and also reducing the influence of the alignment accuracy of the patterns between different layers during the photolithography process, thereby increasing the process window. In addition, in the method for preparing a semiconductor structure provided by the embodiment of the present application, the first channel layer and the second channel layer are connected, thereby avoiding the influence of dry etching plasma damage on the channel, thereby improving the channel performance.

[0029] In some embodiments, a connecting groove is opened, including: along a first direction, the connecting groove passes through a first channel layer; the first direction is an extension direction of the connecting groove; along a second direction, a size of the connecting groove is smaller than a size of the first channel layer; the second direction is perpendicular to the first direction, and a plane formed by the first direction and the second direction is parallel to a plane where the stacking structure is located.

[0030] In some embodiments, the first dielectric layer includes multiple first channel layers; the multiple first channel layers are arranged into at least two channel rows; the at least two channel rows include adjacent first channel rows and second channel rows; a connecting groove is opened, including: along a first direction, the connecting groove passes through the first channel row and the second channel row; the first direction is the extension direction of the connecting groove.

[0031] In some embodiments, a first dielectric layer and a stacking structure are provided in a stacked arrangement, including: forming an initial stacking structure, the initial stacking structure including a plurality of second dielectric layers and a plurality of sacrificial gate layers, the second dielectric layers and the sacrificial gate layers being arranged in an overlapping manner; forming a first dielectric layer on the initial stacking structure; opening a first channel hole penetrating the first dielectric layer and the initial stacking structure; forming a first channel structure and a second channel structure in the first channel hole; removing the sacrificial gate layer and replacing the sacrificial gate layer with a gate layer.

[0032] In some embodiments, forming a first channel structure and a second channel structure includes: forming a channel layer covering a first channel hole; forming a channel dielectric filled in the channel layer; wherein the channel layer located in the first dielectric layer serves as the first channel layer, and the channel layer located in the initial stacking structure serves as the second channel layer, the channel dielectric located in the first dielectric layer serves as the first channel dielectric, and the channel dielectric located in the initial stacking structure serves as the second channel dielectric; the first channel dielectric and the first channel layer constitute a first channel structure, and the second channel dielectric and the second channel layer constitute a second channel structure.

[0033] In some embodiments, forming a first channel structure and a second channel structure includes: forming a channel layer covering a first channel hole; forming a channel dielectric filled in the channel layer; removing the channel layer and the channel dielectric located in the first dielectric layer to form a second channel hole; using the remaining channel layer as a second channel layer and the remaining channel dielectric as a second channel dielectric; forming a first channel layer covering a bottom and sidewalls of the second channel hole; filling the first channel dielectric in the first channel layer; wherein the first channel dielectric and the first channel layer constitute a first channel structure, and the second channel dielectric and the second channel layer constitute a second channel structure.

[0034] In some embodiments, after forming the top selection gate and the connection line, the preparation method further includes: forming a bit line contact structure, wherein the bit line contact structure is connected to the first channel layer.

[0035] In some embodiments, a bit line contact structure is formed, including: forming a third dielectric layer covering the first dielectric layer away from the surface of the stacked structure, the third dielectric layer also covering the top selection gate and the connecting line; etching the surface of the third dielectric layer away from the first dielectric layer to form a first contact hole, the first contact hole exposing the channel layer; and forming a bit line contact structure in the first contact hole.

[0036] In some embodiments, after forming the top selection gate and the connection line, the preparation method further includes: forming a top selection gate contact structure, and connecting the top selection gate contact structure to the connection line.

[0037] In some embodiments, a top selection gate contact structure is formed, including: forming a third dielectric layer covering the first dielectric layer away from the surface of the stacked structure, the third dielectric layer also covering the top selection gate and the connecting line; etching the surface of the third dielectric layer away from the first dielectric layer to form a second contact hole, the second contact hole exposing the connecting line; and forming a top selection gate contact structure in the second contact hole.

[0038] In some embodiments, the preparation method further includes: forming a bit line contact structure, the bit line contact structure is located in the third dielectric layer and connected to the first channel layer; and the top selection gate contact structure and the bit line contact structure are formed in the same process step.

[0039] In yet another aspect, a storage system is provided, comprising: the semiconductor structure as described above, and a controller coupled to the semiconductor structure to control the semiconductor structure to store data.

[0040] On the other hand, an electronic device is provided, comprising the storage system as described above.

[0041] It can be understood that the beneficial effects that can be achieved by the storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0043] Figure 1A A block diagram of a storage system provided in an embodiment of the present application;

[0044] Figure 1B A structural block diagram of a memory card provided in an embodiment of the present application;

[0045] Figure 1C A structural block diagram of another memory card provided in an embodiment of the present application;

[0046] Figure 2A A schematic diagram of the three-dimensional structure of a three-dimensional memory provided in an embodiment of the present application;

[0047] Figure 2B A cross-sectional view of a three-dimensional memory provided in an embodiment of the present application;

[0048] Figure 3A A schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0049] Figure 3B A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0050] Figure 4A A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0051] Figure 4B for Figure 4A A cross-sectional view along direction A1A2;

[0052] Figure 5 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present application;

[0053] Figure 6A-6K A schematic diagram of a process of preparing a semiconductor structure provided in an embodiment of the present application;

[0054] Figure 7A-7E A schematic diagram of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0055] Figure 8 A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0056] Figure 9A-9B A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0057] Figures 10A-10D A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0058] Figures 11A-11D A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0059] Fig. 12A A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0060] Fig. 12B A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0061] Fig. 12C A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0062] Fig.12D A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0063] Fig.13A A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0064] Fig. 13B for Fig.13A A cross-sectional view along direction B1B2;

[0065] Fig. 13C A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0066] Fig.13D A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0067] Fig.14 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0068] Fig.15 A schematic flow chart of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0069] Figure 16A-16C A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0070] Figure 17A-17B A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0071] Fig.18 A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0072] Figure 19A-Figure 19C A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0073] Figures 20A-20D A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0074] Fig.21A A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0075] Fig.21B A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0076] Fig. 21C A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0077] Fig.21D A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0078] Fig.21EA schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0079] Fig. 22 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0080] Fig.23 A schematic flow chart of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0081] Figure 24A-24F A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0082] Fig.25 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0083] Fig.26 A schematic flow chart of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0084] Figure 27A-Figure 27D A schematic diagram of a process of another method for preparing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0085] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0086] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0087] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0088] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0089] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0090] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0091] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0092] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0093] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0094] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0095] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0096] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0097] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0098] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0099] The embodiment of the present application provides an electronic device, which may be a mobile phone, a mobile phone, a desktop computer, a tablet computer, a laptop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device (such as a smart watch, a smart bracelet, smart glasses, etc.), a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, a server, or any other suitable electronic device having a storage device. The embodiment of the present application does not specifically limit the specific form of the above-mentioned electronic device, and it may be any electronic device having a storage device. In some embodiments, the electronic device may include a printed circuit board in addition to a storage device. The printed circuit board is coupled to the storage device and integrated into the electronic device.

[0100] The storage device may be a universal flash storage (UFS) package or an embedded Multi Media Card (eMMC) package, wherein the storage system may be integrated into various types of storage devices.

[0101] An example of a storage system structure is as follows: Figure 1A As shown, the storage system 1 mainly includes one or more memory devices 2 and a memory controller 3, and the memory controller 3 is coupled to the memory device 2 to control the storage data of the memory device 2. Among them, the storage system 1 can be integrated into a variety of memory cards such as a personal computer memory card international association (PCMCIA or PC), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD), a universal flash storage (UFS) and a solid state drive (SSD). The embodiment of the present application does not limit the number of memory devices 2 included in the storage system 1, and it can be reasonably set according to actual conditions.

[0102] The memory controller 3 is configured to operate in a low duty cycle environment, which may include, for example, an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0103] Alternatively, the memory controller 3 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablet computers, laptop computers, and enterprise storage arrays.

[0104] Alternatively, the memory controller 3 is configured to manage data stored in the memory device 2 and communicate with an external device (e.g., a host) according to a specific communication protocol. The communication protocol includes at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-E protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small drive interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a FireWire protocol.

[0105] The memory controller 3 may also be configured to control the operation of the memory device 2, such as read, erase, and program operations. In some embodiments, the memory controller 3 may also be configured to manage various functions regarding data stored or to be stored in the memory device 2, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the memory controller 3 may also be configured to process error correction codes regarding data read from the memory device 2 or written to the memory device 2. The memory controller 3 may also perform any other suitable functions, such as formatting the memory device 2.

[0106] In some embodiments, Figure 1A As shown, the storage system 1 includes a host 4. For example, the host 4 is coupled to a memory controller 3.

[0107] Exemplarily, the storage system 1 may be integrated into the above-mentioned electronic device. The host 4 may be a processor of the electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 4 may be configured to send or receive data to and from the memory device 2.

[0108] The memory controller 3 is coupled to the memory device 2 and the host 4, and is configured to control the memory device 2. The memory controller 3 can manage data stored in the memory device 2 and communicate with the host 4. In some embodiments, the memory controller 3 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 3 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card 28 (embedded multi-media-card, eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The memory controller 3 can be configured to control the operation of the memory device 2, such as read, erase, and program operations. In some embodiments, the memory controller 3 is configured to control an array of memory cells through a first peripheral circuit and a second peripheral circuit. The memory controller 3 may also be configured to manage various functions related to data stored in or to be stored in the memory device 2, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 3 is further configured to process error correction codes (ECC) related to data read from or written to the memory device 2. Any other appropriate functions may also be performed by the memory controller 3, such as formatting the memory device 2. The memory controller 3 may communicate with an external device (e.g., a host 4) according to a specific communication protocol.For example, the memory controller 3 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, high-speed PCI (PCI-express, PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0109] The memory controller 3 and one or more memory devices 2 can be integrated into various types of memory devices, for example, included in the same package (such as a universal Flash storage (UFS) package or an eMMC package). That is, the memory system 1 can be implemented and packaged into different types of final electronic devices.

[0110] In some embodiments, Figure 1B As shown, the memory controller 3 and the single memory device 2 may be integrated into the memory card 11. The memory card 11 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 11 may further include a processor that connects the memory card 11 to a host (e.g., Figure 1A A memory card connector 5 coupled to a host 4).

[0111] In some embodiments, Figure 1C As shown, the memory controller 3 and the plurality of memory devices 2 may be integrated into the SSD 12. The SSD 12 may further include a method for connecting the SSD 12 to a host (eg, Figure 1A In some embodiments, the storage capacity and / or operating speed of the SSD 12 is higher than the storage capacity and / or operating speed of the memory card 11.

[0112] As an example, a memory device 2 is also shown. Figure 2A and Figure 2B As shown, taking three-dimensional memory as an example, Figure 2A A schematic diagram of the three-dimensional structure of a three-dimensional memory provided in an embodiment of the present application, Figure 2B A cross-sectional view of a three-dimensional memory.

[0113] It should be noted that in Figure 2A and Figure 2B In the embodiment, the three-dimensional memory extends in the XY plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the source layer SL is located: the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the source layer SL is located, that is, perpendicular to the XY plane.

[0114] As used in the present disclosure, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate or source layer of the semiconductor device in a third direction Z when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concept is applied throughout the present disclosure to describe spatial relationships.

[0115] In order to more clearly illustrate the structure of the device, Figure 2B In the figure, a view of the array area CA and a view of the step area SS are shown. The view of the array area CA is based on the left coordinate system, and the view of the step area SS is based on the left coordinate system, that is, the view of the array area CA shows the cross-sectional structure along the Y direction, and the view of the step area SS shows the cross-sectional structure along the X direction.

[0116] See also Figure 2A and Figure 2B Some embodiments of the present disclosure provide a memory device 2. The memory device 2 may include an array device 30. The memory device 2 may also include a source layer SL coupled to the array device 30, and a peripheral device 20 coupled to the array device 30. The peripheral device 20 may be disposed on a side of the array device 30 away from the source layer SL.

[0117] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0118] The array device 30 may include array-arranged memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings) 31. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 31.

[0119] Continue to see Figure 2A and Figure 2B In some embodiments, the array device 30 may further include an array interconnect layer 40. The array interconnect layer 40 may be coupled to the memory cell string 31. The array interconnect layer 40 may include a drain terminal (i.e., a bit line BL) of the memory cell string 31, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 31.

[0120] The array interconnect layer 40 may include one or more first interlayer insulating layers 42, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 42, the contacts may include, for example, a bit line contact BL-CNT coupled to the bit line BL, and a drain select gate contact SGD-CNT coupled to the drain select gate SGD (also referred to as a top select gate). The array interconnect layer 40 may also include one or more first interconnect conductor layers 41. The first interconnect conductor layer 41 may include a plurality of connection lines, for example, a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 41 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 42 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials.

[0121] The peripheral device 20 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0122] Specifically, in some embodiments, the peripheral device 20 may include a substrate 21, a transistor 22 disposed on the substrate 21, and a peripheral interconnect layer 23 disposed on the substrate 21. The peripheral circuit may include the transistor 22.

[0123] The material of the substrate 21 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0124] The peripheral interconnection layer 23 is coupled to the transistor 22 to transmit electrical signals between the transistor 22 and the peripheral interconnection layer 23. The peripheral interconnection layer 23 may include one or more second interlayer insulating layers 231, and may also include one or more second interconnect conductor layers 232. Different second interconnect conductor layers 232 may be coupled through contacts. The material of the second interconnect conductor layer 232 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 231 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0125] The peripheral interconnect layer 23 can be coupled to the array interconnect layer 40, so that the array device 30 and the peripheral device 20 can be coupled. Specifically, since the peripheral interconnect layer 23 is coupled to the array interconnect layer 40, the peripheral circuit in the peripheral device 20 can be coupled to the storage cell string in the array device 30 to achieve the transmission of electrical signals between the peripheral circuit and the storage cell string. In some possible implementations, a bonding interface 500 can be provided between the peripheral interconnect layer 23 and the array interconnect layer 40, and the peripheral interconnect layer 23 and the array interconnect layer 40 can be bonded and coupled to each other through the bonding interface 500.

[0126] The present application also provides a semiconductor structure. It is explained here that the semiconductor structure can be the above-mentioned three-dimensional memory. Alternatively, the semiconductor structure can also be a part of the above-mentioned three-dimensional memory, for example, it can include the array device 30 in the above-mentioned embodiment. The present application does not limit this, and it can be reasonably set according to actual conditions.

[0127] like Figure 3A As shown, the semiconductor structure 10 includes a stacked structure 100, a channel structure 600, and a top selective gate cut (TSG Cut) CUT.

[0128] The stack structure 100 includes a plurality of second dielectric layers and a plurality of gate layers which are sequentially overlapped. The channel structure 600 penetrates the stack structure 100 .

[0129] Exemplarily, at least one gate layer close to the surface of the stacked structure 100 serves as a top selective gate (TSG) electrode layer, and each channel structure 600 can form at least one field effect transistor (or also referred to as a top selective transistor) at a position corresponding to the top selective gate layer.

[0130] The gate layers except the top selection gate layer in the stacked structure 100 can be used as control gates, and the position of the channel structure 600 corresponding to each control gate can form a memory cell.

[0131] In some embodiments, the semiconductor structure 10 further includes at least one top selection gate cut line CUT, which is used to divide the memory cell string 31 into multiple regions. Exemplarily, the top selection gate 410 of each region can be controlled separately to realize the storage function of a single memory cell.

[0132] The top selection gate cut line CUT passes through the top selection gate TSG and the dielectric layer adjacent thereto to divide the top selection gate into zones, so that the top selection gate TSG in each zone can be driven separately. Figure 3A As shown, the top selection gate cut line CUT may be disposed between adjacent channel structures 600. However, the embodiment is not limited thereto.

[0133] like Figure 3B As shown, the semiconductor structure 10 further includes a top selective gate channel hole (TSG CH) connected to the channel structure 600 .

[0134] In some embodiments, the semiconductor structure 10 may further include a drain select gate contact SGD-CNT which is electrically connected to the top select gate TSG for signal transmission with an external control circuit, thereby driving the top select gate of each region in the memory cell string 31 respectively.

[0135] However, different masks need to be used in the process steps of preparing the top selection gate cut line CUT, the top selection gate channel CH and the drain selection gate contact SGD-CNT, and they need to be implemented in different process steps during preparation, resulting in a long preparation process flow.

[0136] Based on this, in order to save process time and simplify the preparation steps, an embodiment of the present application also provides a semiconductor structure.

[0137] Four specific embodiments are provided below to illustrate the semiconductor structure.

[0138] Embodiment 1

[0139] like Figure 4A Shown and Figure 4B As shown, Figure 4B for Figure 4A A cross-sectional view along A1A2. The semiconductor structure 10 includes a first dielectric layer 110, a stacked structure 100, a first channel layer 310, a second channel layer 320, a top selection gate 410, and a connecting line 420. The first dielectric layer 110 and the stacked structure 100 are stacked. The stacked structure 100 includes a plurality of second dielectric layers 120 and a plurality of gate layers 210, and the second dielectric layers 120 and the gate layers 210 are overlapped. The first channel layer 310 is located in the first dielectric layer 110. The second channel layer 320 runs through the stacked structure 100, and the first channel layer 310 is connected to the second channel layer 320. The connecting line 420 is located in the first dielectric layer 110. The top selection gate 410 is located on a side of the connecting line 420 close to the stacked structure 100, and is connected to the connecting line 420 (for example, the connecting line 420 and the top selection gate 410 form an integral structure). Among them, the first channel layer 310 also surrounds the top selection gate 410.

[0140] like Figure 5 As shown, the embodiment of the present application also provides a method for preparing a semiconductor structure, comprising:

[0141] S11 , providing a first dielectric layer 110 and a stacked structure 100 .

[0142] The stacked structure 100 includes a plurality of second dielectric layers 120 and a plurality of gate layers 210 , and the second dielectric layers 120 and the gate layers 210 are arranged in an overlapping manner.

[0143] The first dielectric layer 110 includes a first channel structure, and the first channel structure penetrates the first dielectric layer 110. The first channel structure includes a first channel layer 310 and a first channel dielectric located in the first channel layer 310.

[0144] The stack structure 100 includes a second channel structure, which runs through the stack structure 100 . The second channel structure includes a second channel layer 320 and a second channel medium located in the second channel layer 320 . The first channel layer 310 is connected to the second channel layer 320 .

[0145] In some embodiments, step S11 includes:

[0146] S111, such as Fig. 6A As shown, an initial stacking structure 200 is formed.

[0147] The initial stacked structure 200 includes a plurality of second dielectric layers 120 and a plurality of sacrificial gate layers 220 .

[0148] The embodiment of the present application does not limit the number of the second dielectric layer 120 and the sacrificial gate layer 220. The second dielectric layer 120 and the sacrificial gate layer 220 are overlapped. The initial stacking structure 200 may include multiple pairs of second dielectric layers 120 and sacrificial gate layers 220, and the number of pairs can be selected according to various application scenarios. For example, the number of pairs can be 32, 64, 96, 128, 160, 192, 224, 256 or more.

[0149] The sacrificial gate layer 220 is used to form the gate layer 210 after being removed later.

[0150] For example, the material of the second dielectric layer 120 may include silicon oxide, silicon nitride or silicon oxynitride, etc. The material of the sacrificial gate layer 220 may include silicon nitride, for example. This embodiment of the application does not limit this, and it can be reasonably set according to actual conditions.

[0151] It is explained here that the material of the second dielectric layer 120 is different from the material of the sacrificial gate layer 220, and the material of the second dielectric layer 120 and the material of the sacrificial gate layer 220 have an etching selectivity ratio. In this way, when the sacrificial gate layer 220 is subsequently removed to form the gate layer 210, only the sacrificial gate layer 220 can be removed, while other materials (such as the material of the second dielectric layer 120) are retained.

[0152] In the embodiment of the present application, the outermost film layer of the initial stacking structure 200 is not limited. That is, the outermost film layer of the initial stacking structure 200 may be the second dielectric layer 120 . Alternatively, the outermost film layer of the initial stacking structure 200 may also be the sacrificial gate layer 220 .

[0153] In some embodiments, the initial stacked structure 200 is also formed on the substrate ( Fig. 6A The material of the substrate may include, for example, a semiconductor material, such as silicon (single crystal silicon, polycrystalline silicon or amorphous silicon), germanium (single crystal germanium), silicon germanium, silicon carbide, glass, gallium nitride, gallium arsenide, glass, SOI (silicon on insulator), GOI (germanium on insulator) or other suitable III-V compound substrates, and the substrate may also be P-type doped or N-type doped.

[0154] S112, such as Figure 6B As shown, a first dielectric layer 110 is formed on the initial stack structure 200 .

[0155] That is to say, Figure 6B As shown, the first dielectric layer 110 is formed on the initial stacked structure 200 .

[0156] The material of the first dielectric layer 110 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride, etc. The material of the first dielectric layer 110 and the material of the second dielectric layer 120 may be the same or different, which is not limited in the present embodiment.

[0157] Exemplarily, in step S111 , the outermost film layer of the initial stack structure 200 is the sacrificial gate layer 220 , and the first dielectric layer 110 is formed on the outermost sacrificial gate layer 220 of the initial stack structure 200 .

[0158] Alternatively, illustratively, if the outermost film layer of the initial stacking structure 200 in step S111 is the second dielectric layer 120, then the outermost second dielectric layer 120 of the initial stacking structure 200 may be used as the first dielectric layer 110. Alternatively, another layer of dielectric layer material may be formed on the outermost second dielectric layer 120 of the initial stacking structure 200, and the dielectric layer material and the second dielectric layer 120 may be used together as the first dielectric layer 110.

[0159] Regarding the sizes of the first dielectric layer 110, the second dielectric layer 120, and the sacrificial gate layer 220, illustratively, along the thickness direction z of the initial stacked structure 200, the size of the second dielectric layer 120 and the size of the sacrificial gate layer 220 may be the same or different. The size of the first dielectric layer 110 may be, for example, greater than the size of the second dielectric layer 120. In other words, the thickness of the first dielectric layer 110 may be greater than the thickness of the second dielectric layer 120.

[0160] In this way, the thickness of the first dielectric layer 110 is relatively thick, and it is easy to form the top selection gate 410 later.

[0161] For the sake of convenience, the thickness direction z of the initial stacking structure 200 is referred to as the third direction z. It is explained here that the second dielectric layer 120 and the sacrificial gate layer 220 are alternately stacked along the third direction z.

[0162] S113, such as Figure 6C As shown, a first channel hole 601 is opened.

[0163] The method of opening the first channel hole 601 may include, for example, forming a mask layer ( Figure 6C The mask layer exposes the area where the first channel hole 601 is to be opened, and then the first dielectric layer 110 is etched to form the first channel hole 601, and finally the mask layer is removed.

[0164] Exemplarily, the surface of the first dielectric layer 110 away from the initial stacking structure 200 is etched to form the first channel hole 601 . The first channel hole 601 penetrates the first dielectric layer 110 and the initial stacking structure 200 .

[0165] In the embodiment of the present application, there is no limitation on the number of the etched first channel holes 601, which can be reasonably set according to the actual situation. For the convenience of illustration, the following figure illustrates etching one first channel hole 601.

[0166] S114 , forming a first channel structure and a second channel structure in the first channel hole 601 .

[0167] Exemplarily, the first channel structure is formed in the first channel hole 601 located in the first dielectric layer 110 , and the second channel structure is formed in the first channel hole 601 located in the initial stack structure 200 .

[0168] In some embodiments, step S114 may include:

[0169] S1141, such as Fig.6D As shown, a channel layer 610 is formed to cover the sidewalls of the first channel hole 601 .

[0170] In some embodiments, Fig.6D As shown, before forming the channel layer 610 , a functional layer 630 is first formed on the sidewall of the first channel hole 601 .

[0171] For example, Fig.6D As shown, the functional layer 630 may include a barrier layer 631 , a storage layer 632 , and a tunneling layer 633 which are sequentially stacked on the sidewall of the first channel hole 601 .

[0172] The material of the barrier layer 631 may include, for example, one or more combinations of silicon oxide, silicon oxynitride, or other high dielectric constant materials. The material of the storage layer 632 may include, for example, one or more combinations of silicon nitride, silicon oxynitride, or silicon. The material of the tunneling layer 633 may include, for example, at least one of silicon oxide or silicon oxynitride.

[0173] Alternatively, illustratively, the functional layer 630 may also be a composite layer including a combination of silicon oxide / silicon nitride / silicon oxide (ONO).

[0174] For example, the material of the first dielectric layer 110 may be the same as the material of the barrier layer 631. Alternatively, the material of the first dielectric layer 110 may be different from the material of the barrier layer 631. This embodiment of the present application does not limit this.

[0175] It is explained here that in the embodiment of the present application, the functional layer 630 also covers the surface of the first dielectric layer 110 away from the initial stacking structure 200 .

[0176] A channel layer 610 is formed to cover the sidewall of the first channel hole 601. Fig.6D As shown, the channel layer 610 is formed within the functional layer 630 .

[0177] The material of the channel layer 610 may include semiconductor materials such as amorphous silicon, polycrystalline silicon or single crystal silicon.

[0178] S1142, such as Fig. 6E As shown, a channel dielectric 620 filled in the channel layer 610 is formed.

[0179] Illustratively, a channel dielectric material may be first formed in the channel layer 610 and on the surface of the channel layer 610 away from the initial stacking structure, and then the surface of the channel dielectric material away from the initial stacking structure 200 may be ground to remove the channel dielectric material located on the surface of the channel layer 610 away from the initial stacking structure to form a channel dielectric 620.

[0180] That is to say, Fig. 6E As shown, a channel dielectric 620 is formed in the channel layer 610. The material of the channel dielectric 620 may include, for example, insulating materials such as silicon oxide, etc. This embodiment of the application does not limit this.

[0181] S1143, such as Fig. 6F As shown, the channel layer 610 and the channel dielectric 620 located in the first dielectric layer 110 are removed to form a second channel hole 602 .

[0182] like Fig. 6F As shown, the channel layer 610 and the channel dielectric 620 in the first dielectric layer 110 are removed, and part of the functional layer 630 on the surface of the first dielectric layer 110 and part of the functional layer 630 in the first dielectric layer 110 are also removed.

[0183] Exemplarily, the channel layer 610 in the first dielectric layer 110, the channel dielectric 620 in the first dielectric layer 110, the storage layer 632 in the first dielectric layer 110, and the tunneling layer 633 in the first dielectric layer 110 are removed. At this time, the barrier layer 631 serves as an etching barrier layer.

[0184] At this time, the remaining channel layer 610 serves as the second channel layer 320 , and the remaining channel dielectric 620 serves as the second channel dielectric 520 .

[0185] In this way, when the first channel layer 310 is subsequently formed, the size of the first channel layer 310 can be increased.

[0186] S1144, such as Figure 6G As shown, a first channel layer 310 is formed to cover the bottom and sidewalls of the second channel hole 602 .

[0187] The material of the first channel layer 310 may include semiconductor materials such as amorphous silicon, polycrystalline silicon or single crystal silicon. The material of the first channel layer 310 may be the same as or different from the material of the second channel layer 320. The material may be set reasonably according to actual conditions.

[0188] It is explained here that when the first channel layer 310 is formed, the material of the first channel layer 310 also covers the surface of the first dielectric layer 110 away from the initial stacking structure 200 (eg Figure 6G (indicated).

[0189] Since the channel dielectric 620, the channel layer 610, the tunneling layer 633 and the barrier layer 631 in the first dielectric layer 110 are removed when the second channel hole 602 is formed, the maximum size of the second channel hole 602 in the direction perpendicular to the third direction z is greater than the maximum size of the second channel 320, and therefore the maximum size of the first channel layer 310 is greater than the maximum size of the second channel layer 320.

[0190] The maximum dimension may be understood as the maximum dimension along a direction parallel to the first dielectric layer 110 .

[0191] like Figure 6G As shown, along the first direction x, a maximum dimension h1 of the first channel layer 310 is greater than a maximum dimension h2 of the second channel layer 320 .

[0192] Exemplarily, the maximum dimension h1 of the first channel layer 310 is the maximum dimension of the inner wall of the first channel layer 310, and the maximum dimension h2 of the second channel layer 320 is the maximum dimension of the inner wall of the second channel layer 320. Alternatively, exemplary, the maximum dimension h1 of the first channel layer 310 may also be the maximum dimension of the outer wall of the first channel layer 310. The present application embodiment does not limit this, and it can be reasonably set according to actual conditions.

[0193] At this time, the first channel layer 310 and the second channel layer 320 are connected.

[0194] S1145, such as Figure 6H As shown, the first channel dielectric 510 is filled in the first channel layer 310 .

[0195] For example, Figure 6H As shown, a first channel dielectric film 510' can be first formed in the first channel layer 310 and on the side of the first dielectric layer 110 away from the initial stacking structure 200, the first channel dielectric film 510' fills the first channel layer 310 and also covers the surface of the first channel layer 310, and then the surface of the first channel dielectric film 510' away from the initial stacking structure 200 is ground to expose the surface of the first dielectric layer 110.

[0196] It is explained here that when the first channel dielectric film 510 ′ is polished, the first channel layer 310 covering the surface of the first dielectric layer 110 is also polished.

[0197] Among them, the method of grinding the first channel dielectric film 510' and the first channel layer 310, for example, can be to grind the first channel dielectric film 510' and the first channel layer 310 using a chemical mechanical polishing (CMP) process to form the first channel layer 310 and the first channel dielectric 510 located in the first channel layer 310.

[0198] The materials of the first channel medium 510 and the second channel medium 520 may be the same, or may be different. This embodiment of the present application does not limit this, and it can be reasonably set according to actual conditions.

[0199] In the embodiment of the present application, there is no limitation on the number of the first channel layer 310 and the second channel layer 320 formed. Fig.6I The top view shown is for illustration.

[0200] For example, Fig.6I As shown, the first dielectric layer 110 includes a plurality of first channel layers 310. The plurality of first channel layers 310 are arranged at intervals in a plane formed by a first direction x and a second direction y. The plane formed by the first direction x and the second direction y is parallel to the plane where the initial stacking structure 200 is located, and the plane formed by the first direction x and the second direction y is perpendicular to the thickness direction of the initial stacking structure 200. The first direction x and the second direction y intersect, for example, the first direction x and the second direction y are perpendicular. For the convenience of illustration, the thickness direction of the initial stacking structure 200 is referred to as the third direction z. That is to say, any two directions of the first direction x, the second direction y and the third direction z intersect, for example, any two directions of the first direction x, the second direction y and the third direction z are perpendicular.

[0201] like Fig.6I As shown, a plurality of first channel layers 310 are arranged into at least two channel rows 300 .

[0202] For example, the at least two channel rows 300 include a first channel row 301 and a second channel row 302 that are adjacent to each other.

[0203] The first channel row 301 includes at least one first channel layer 310 , and the second channel row 302 also includes at least one first channel layer 310 .

[0204] The number of first channel layers 310 included in the first channel row 301 and the number of first channel layers 310 included in the second channel row 302 may be the same or different. This embodiment of the present application does not limit this. For example, Fig.6I As shown, along the first direction x, the plurality of first channel layers 310 included in the channel row 300 are sequentially arranged at intervals.

[0205] Exemplarily, the first channel layers 310 of the first channel row 301 and the first channel layers 310 of the second channel row 302 are arranged alternately.

[0206] In this way, space can be saved and the integration level of the semiconductor structure 10 can be improved.

[0207] S115, such as Figure 6J As shown, the sacrificial gate layer 220 is removed and replaced by the gate layer 210 .

[0208] like Figure 6J As shown, after the sacrificial gate layer 220 is removed, a metal conductive material is filled at the location of the sacrificial gate layer 220 to form a gate layer 210 .

[0209] For example, the material of the gate layer 210 may include a metal conductive material such as tungsten, cobalt, copper, aluminum, titanium, tantalum or nickel, etc. This embodiment of the present application does not limit this.

[0210] It is explained here that if the material of the sacrificial gate layer 220 is the same as the material of the first channel dielectric 510, then before removing the sacrificial gate layer 220, Figure 6K As shown, it is necessary to form a dielectric layer covering the first channel dielectric 510 away from the initial stacked structure 200, and then remove the sacrificial gate layer 220. In this way, it is possible to avoid the first channel dielectric 510 being removed by mistake when removing the sacrificial gate layer 220.

[0211] At this time, a stacked structure 100 is formed, and the stacked structure 100 includes multiple second dielectric layers 120 and multiple gate layers 210. The second dielectric layers 120 and the gate layers 210 are alternately arranged.

[0212] S12 , opening a connection groove on a surface of the first dielectric layer 110 away from the stacked structure 100 .

[0213] For ease of understanding, the following Fig. 7A The first dielectric layer 110 includes at least one first channel layer 310. Fig. 7A As shown, illustratively, the first dielectric layer 110 includes a plurality of first channel layers 310. A first channel dielectric 510 is formed in the first channel layer 310.

[0214] Exemplarily, step S12 includes:

[0215] S121, such as Figure 7B As shown, a first mask layer 710 is formed on a surface of the first dielectric layer 110 away from the stacked structure 100 .

[0216] That is, a first mask layer 710 is formed to cover the surface of the first dielectric layer 110 away from the stacked structure 100. The first mask layer 710 exposes a portion of the connection groove to be opened.

[0217] The material of the first mask layer 710 may include, for example, any one of oxide, nitride, photoresist (PR) or photoinitiator (PI). For example, the material of the first mask layer 710 may be silicon dioxide (SiO2), silicon nitride (Si3N4) or polysilicon (ploy).

[0218] Exemplarily, a layer of mask material is deposited on the surface of the first dielectric layer 110 away from the stacked structure 100 , and photolithography and etching are performed to open windows in areas where the connection grooves are to be opened, so as to form the first mask layer 710 .

[0219] That is to say, Figure 7B As shown, a patterned first mask layer 710 is formed on a surface of the first dielectric layer 110 away from the stacked structure 100 , and the patterned first mask layer 710 exposes a predetermined formation area of ​​the connection groove.

[0220] It is explained here that the size of the connection groove along the first direction x and the size of the connection groove along the second direction y can be controlled by controlling the size of the window opening in the area where the connection groove is to be opened in the first mask layer 710. The first direction x and the second direction y mentioned above intersect, for example, the first direction x and the second direction y are perpendicular, and the plane formed by the first direction x and the second direction y is perpendicular to the third direction z (the thickness direction of the stacked structure 100).

[0221] Exemplarily, along the second direction y, the window size m1 (ie, the width of the connection groove) is 40 nm to 80 nm. For example, the window size m1 is 40 nm, 50 nm, 60 nm, 70 nm or 80 nm.

[0222] S122, such as Figure 7C As shown, a connecting groove 421 is provided.

[0223] In some embodiments, Figure 7C As shown, along the third direction z, the connection groove 421 overlaps with at least a portion of the first channel structure 101 .

[0224] For example, Figure 7C As shown, the connection groove 421 is arranged across the first channel structure 101 .

[0225] That is to say, Fig.7D As shown, Fig.7D for Figure 7C . Along the first direction x, the connection groove 421 passes through the first channel structure 101. The first direction x is the extension direction of the connection groove 421. That is, along the first direction x, the connection groove 421 passes through the first channel layer 310. That is, the corresponding part of the first channel layer 310 is removed.

[0226] like Fig.7D As shown, along the second direction y, the dimension d1 of the connection groove 421 is smaller than the dimension d2 of the first channel structure 101. Along the second direction y, the dimension d1 of the connection groove 421 is smaller than the dimension d3 of the first channel layer 310.

[0227] It is explained here that, along the second direction y, the size d1 of the connection groove 421 is the same as the window size of the first connection groove 421 in the above step S121 .

[0228] That is, along the second direction y, the size d1 of the connection groove 421 is 40 nm to 80 nm. Exemplarily, the size d1 of the connection groove 421 is 40 nm, 50 nm, 60 nm, 70 nm or 80 nm.

[0229] That is, along the third direction z, the connection groove 421 does not penetrate the first channel layer 310 and the first channel dielectric 510 .

[0230] In this way, the contact area between the top selection gate 410 to be formed subsequently and the first channel 310 can be increased, thereby increasing the signal transmission speed and improving the performance of the semiconductor structure 10 .

[0231] In some embodiments, Fig. 7E As shown, the plurality of first channel layers 310 may be arranged into at least two channel rows 300. The arrangement direction of the plurality of first channel layers 310 in the channel row 300 is the same as the extension direction of the connection groove 421.

[0232] For example, Fig. 7E As shown, the at least two channel rows 300 may include an adjacent first channel row 301 and a second channel row 302. Alternatively, the at least two channel rows 300 may also be a plurality of non-adjacent channel rows 300.

[0233] Continue to refer Fig. 7E A plurality of connection grooves 421 are opened on the surface of the first dielectric layer 110 away from the stack structure 100 , and the plurality of connection grooves 421 respectively pass through the first channel row 301 and the second channel row 302 of the plurality of channel rows 300 .

[0234] Exemplarily, each connection groove 421 extends along the first direction x. Along the second direction y, the plurality of connection grooves 421 are arranged at intervals.

[0235] The embodiment of the present application does not limit the number of the connecting grooves 421 and the extending direction of the connecting grooves 421, which can be reasonably set according to actual conditions.

[0236] For the convenience of preparation and simplicity of process, the extension direction of the plurality of connection grooves 421 is the same, and the extension direction of the connection grooves 421 intersects with the direction in which the connection grooves 421 are arranged at intervals.

[0237] It is explained here that after the connection groove 421 is formed, the first mask layer 710 is removed.

[0238] S13, such as Figure 8 As shown, at least a portion of the first channel dielectric 510 is removed.

[0239] For example, Figure 8 As shown, the first channel dielectric 510 located in the first channel layer 310 is removed.

[0240] In the embodiment of the present application, all the first channel dielectrics 510 in the first channel layer 310 may be removed. Alternatively, part of the first channel dielectrics 510 in the first channel layer 310 may also be removed. The embodiment of the present application does not limit this, and it is only necessary to ensure that the surface of the first channel dielectrics 510 away from the stack structure 100 after removal does not exceed the bottom of the connecting groove 421.

[0241] like Figure 8 As shown, after the first channel dielectric 510 is removed, the first channel layer 310 is exposed.

[0242] S14 , forming a conductive structure in the connecting groove 421 .

[0243] In some embodiments, step S14 may include:

[0244] S141, such as Fig.9A As shown, a gate oxide layer 401 is formed.

[0245] For example, Fig.9A As shown, the gate oxide layer 401 is formed on the inner wall of the first channel layer 310 .

[0246] That is, the gate oxide layer 401 is formed on the surface of the first channel layer 310 away from the first dielectric layer 110 .

[0247] The material of the gate oxide layer 401 may include silicon oxide, for example.

[0248] S142, such as Fig. 9B As shown, a conductive structure 400 is formed.

[0249] For example, Fig. 9B As shown, first, a conductive material may be formed in the area surrounded by the first channel layer 310, in the connection groove 421, and on the surface of the first dielectric layer 110 away from the stacked structure 100, and the conductive material is filled in the first channel layer 310, in the connection groove 421, and on the surface of the first dielectric layer 110 away from the stacked structure 100. Then, the surface of the conductive material away from the first dielectric layer 110 is etched until the surface of the first dielectric layer 110 is exposed, and a portion of the conductive material located in the connection groove 421 is etched back, and the remaining conductive material serves as the conductive structure 400.

[0250] Exemplarily, a wet etching process or a dry etching process may be used to etch back the conductive material in the connection groove 421. For example, the degree of etching back the conductive material may be controlled by controlling the etching solution composition, etching solution concentration, and etching time of the wet etching. Alternatively, the degree of etching back the conductive material may be controlled by controlling the etching gas and etching time of the dry etching.

[0251] In other words, etching back the conductive material can be achieved without using a photolithography process, that is, no mask, exposure, and development processes are required, which can save process steps and preparation time.

[0252] At this time, the conductive structure 400 is formed in both the first channel layer 310 and the connecting groove 421 .

[0253] The material of the conductive structure 400 may include, for example, metal conductive materials such as tungsten, cobalt, copper, aluminum, titanium, tantalum or nickel, etc. This embodiment of the present application does not limit this.

[0254] The materials of the conductive structure 400 and the gate layer 210 may be the same, or may be different. This embodiment of the present application does not limit this, and it can be reasonably set according to actual conditions.

[0255] Exemplarily, the conductive structure 400 located in the first channel layer 310 is referred to as a top selection gate 410 , and the conductive structure 400 located in the connection groove 421 is referred to as a connection line 420 .

[0256] That is, the conductive structure 400 includes a top selection gate 410 filled in the first channel layer 310 , and a connection line 420 connected to the top selection gate 410 .

[0257] At this time, if Fig. 9B As shown, the first channel layer 310 is farther away from the surface of the stack structure 100 than the connection line 420 is farther away from the surface of the stack structure 100 .

[0258] That is, the connection line 420 is away from the surface of the stack structure 100 and does not exceed the surface of the first channel layer 310 away from the stack structure 100 .

[0259] In this way, it is convenient to realize the connection between the bit line contact structure 430 and the first channel layer 310 which is prepared subsequently.

[0260] S15 . Form a bit line contact structure.

[0261] In some embodiments, step S15 may include:

[0262] S151, such as Fig. 10A As shown, a fourth dielectric layer 140 is formed.

[0263] For example, Fig. 10A As shown, first, a fourth dielectric film 140' can be formed in the connection groove 421 and on the surface of the first dielectric layer 110 away from the stack structure 100. The fourth dielectric film 140' is formed in the connection groove 421 and on the surface of the first dielectric layer 110 away from the stack structure 100. Then, the surface of the fourth dielectric film 140' away from the stack structure 100 is etched until the first channel layer 310 is exposed, and the remaining fourth dielectric film 140' serves as the fourth dielectric layer 140.

[0264] That is, the fourth dielectric layer 140 fills the remaining connection grooves 421 . The fourth dielectric layer 140 is located on the surface of the connection line 420 away from the stacked structure 100 .

[0265] The material of the fourth dielectric layer 140 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0266] S152, such as Fig. 10B As shown, a third dielectric layer 130 is formed.

[0267] That is to say, Fig. 10B As shown, a third dielectric layer 130 is formed to cover the surface of the first dielectric layer 110 away from the stack structure 100 .

[0268] Exemplarily, the third dielectric layer 130 may include one or more dielectric layers stacked together.

[0269] The material of the third dielectric layer 130 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride, etc. The material of the third dielectric layer 130 and the material of the fourth dielectric layer 140 may be the same or different, which is not limited in the present embodiment.

[0270] It is explained here that the fourth dielectric layer 140 and the third dielectric layer 130 can be formed in the same process step, or can also be formed in different process steps.

[0271] S153, such as Fig. 10C As shown, the surface of the third dielectric layer 130 away from the first dielectric layer 110 is etched to open a first contact hole 603 .

[0272] The first contact hole 603 exposes the first channel layer 310 .

[0273] That is, the first contact hole 603 at least exposes the second portion 312 of the first channel layer 310 .

[0274] In this way, it is convenient for the bit line contact structure 430 formed in the first contact hole 603 to be connected to the first channel layer 310 .

[0275] Exemplarily, a method for opening the first contact hole 603 may be, for example, forming a mask layer on a surface of the third dielectric layer 130 away from the stacked structure 100, the mask layer exposing an area where the first contact hole 603 is to be formed, then etching the third dielectric layer 130 to form the first contact hole 603, and finally removing the mask layer.

[0276] S154, such as Fig. 10D As shown, a bit line contact structure 430 is formed in the first contact hole 603 .

[0277] For example, Fig. 10D As shown, before forming the bit line contact structure 430 , a bit line contact dielectric layer 431 is first formed in the first contact hole 603 . The bit line contact dielectric layer 431 covers the sidewalls and bottom surface of the first contact hole 603 .

[0278] The material of the bit line contact dielectric layer 431 may include, for example, a conductive material such as titanium nitride.

[0279] In this way, the bit line contact structure 430 to be formed can be more closely attached to the inner wall of the first contact hole 603, thereby improving the adhesion of the bit line contact structure 430 and improving the connection strength. In addition, the bit line contact dielectric layer 431 also wraps the exposed portion of the first channel layer 310 in the first contact hole 603 to improve the connection strength between the bit line contact structure 430 and the first channel layer 310.

[0280] Continue to refer Fig. 10D , forming a bit line contact structure 430.

[0281] The bit line contact structure 430 is filled in the first contact hole 603 , and the bit line contact structure 430 is connected to the first channel layer 310 .

[0282] For example, the material of the bit line contact structure 430 may include a metal conductive material such as tungsten, cobalt, copper, aluminum, titanium, tantalum or nickel, etc. This embodiment of the present application does not limit this.

[0283] S16, forming a top selection gate contact structure.

[0284] Exemplarily, step S16 may include:

[0285] S161, such as Fig.11A As shown, the surface of the third dielectric layer 130 away from the first dielectric layer 110 is etched to form a second contact hole 604 .

[0286] The second contact hole 604 exposes the connecting line 420 .

[0287] For example, along the second direction y, the size of the second contact hole 604 is greater than the size of the connection line 420 (ie, the line width of the connection line 420 ).

[0288] Along the third direction Z, the size of the second contact hole 604 is not less than the distance between the surface of the connection line 420 away from the stack structure 100 and the surface of the third dielectric layer 130 away from the stack structure 100 .

[0289] That is, the second contact hole 604 at least exposes the surface of the connection line 420 away from the stack structure 100 .

[0290] Illustratively, the second contact hole 604 may also expose a portion of the side surface of the connection line 420 .

[0291] Alternatively, illustratively, the second contact hole 604 may also expose all side surfaces of the connection line 420 .

[0292] It is explained here that the more the portion of the connection line 420 is exposed, the greater the contact area between the top selection gate contact structure 440 to be formed subsequently and the connection line 420 can be.

[0293] In this way, it is convenient for the top selection gate contact structure 440 formed in the second contact hole 604 to be connected to the connection line 420 later.

[0294] Illustratively, the method of forming the second contact hole 604 may be the same as the method of forming the first contact hole 603 , and specific reference is made to the description of forming the first contact hole 603 .

[0295] It is explained here that the second contact hole 604 and the first contact hole 603 can be formed in the same process step or in different process steps, which is not limited in the present embodiment.

[0296] S162, such as Fig. 11B As shown, a top selection gate contact structure 440 is formed in the second contact hole 604 .

[0297] For example, Fig. 11BAs shown, before forming the top selection gate contact structure 440 , a gate contact dielectric layer 441 is first formed in the second contact hole 604 . The gate contact dielectric layer 441 covers the sidewalls and bottom surface of the second contact hole 604 .

[0298] The material of the gate contact dielectric layer 441 may include, for example, a conductive material such as titanium nitride.

[0299] In this way, the top selection gate contact structure 440 to be formed can be more closely fitted to the inner wall of the second contact hole 604, thereby improving the adhesion of the top selection gate contact structure 440 and improving the connection strength. In addition, the gate contact dielectric layer 441 also wraps the exposed portion of the connection line 420 in the second contact hole 604 to improve the connection strength between the top selection gate contact structure 440 and the connection line 420.

[0300] Continue to refer Fig. 11B , forming a top selection gate contact structure 440.

[0301] The top selection gate contact structure 440 is filled in the second contact hole 604 , and the top selection gate contact structure 440 is connected to the connection line 420 .

[0302] Exemplarily, the material of the top selection gate contact structure 440 may include a metal conductive material such as tungsten, cobalt, copper, aluminum, titanium, tantalum or nickel. The material of the top selection gate contact structure 440 and the material of the bit line contact structure 430 may be the same or different. This embodiment of the application does not limit this.

[0303] It is noted that, in some embodiments, the top select gate contact structure 440 and the bit line contact structure 430 may be formed in the same process step.

[0304] For example, Fig. 11C As shown, after the first contact hole 603 and the second contact hole 604 are opened on the third dielectric layer 130 , a bit line contact structure 430 is formed in the first contact hole 603 , and a top selection gate contact structure 440 is formed in the second contact hole 604 .

[0305] like Fig.11D As shown, Fig.11D for Fig. 11C The connection line 420 extends along the first direction x and is connected to the top selection gate contact structure 440. A plurality of top selection gate contact structures 440 are arranged at intervals along the second direction y.

[0306] It is explained here that the method for preparing the semiconductor structure provided in the embodiment of the present application may first perform step S15 and then perform step S16. Alternatively, step S16 may be performed first and then step S15. Alternatively, step S15 and step S16 may be performed simultaneously. The embodiment of the present application does not limit this, and it can be reasonably set according to the actual situation.

[0307] The above preparation method provided in the embodiments of the present application is not limited to any step sequence and can be reasonably adjusted as needed.

[0308] In addition, the above steps S11-S16 may remove some steps as needed, and are not limited to include every step. Some steps may also be added as needed, and are not limited to only include the above steps.

[0309] The method for preparing the semiconductor structure 10 provided by the implementation of the present application forms a top selection gate 410 in the first channel layer 310, and forms the top selection gate 410 and the connection line 420 connecting the top selection gate 410 in the same process step, thereby saving the preparation process steps, simplifying the process flow, and reducing the preparation cost. At the same time, since the conductive structure 400 is filled in the connection groove 421 to form the top selection gate 410 and the connection line 420 connected to the top selection gate 410, and the pattern shape of the connection line 420 can be defined by the shape of the connection groove 421, that is, it can be formed without using a photolithography process, saving the mask layer required for preparation, and reducing the influence of the alignment accuracy of the patterns between different layers during the photolithography process, thereby increasing the process window. In addition, in the method for preparing the semiconductor structure provided by the embodiment of the present application, the first channel layer 310 and the second channel layer 320 are connected, thereby avoiding the influence of dry etching plasma damage on the channel, thereby improving the channel performance.

[0310] The semiconductor structure provided in the embodiment of the present application is described below. The semiconductor structure can be obtained by using the above-mentioned method for preparing the semiconductor structure.

[0311] Based on this, Fig. 12A As shown, the semiconductor structure 10 includes a first dielectric layer 110 and a stacked structure 100 , a first channel layer 310 , a second channel layer 320 , a top selection gate 410 , and a connection line 420 .

[0312] The first channel layer 310 is located in the first dielectric layer 110 , and the first channel layer 310 also surrounds the top selection gate 410 .

[0313] That is to say, Fig. 12A As shown, the top select gate 410 is located within the first channel layer 310 .

[0314] The connection line 420 is located in the first dielectric layer 110 , and the top selection gate 410 is connected to the connection line 420 . The top selection gate 410 is located on a side of the connection line 420 close to the stack structure 100 .

[0315] That is, the top selection gate 410 is located between the connection line 420 and the stack structure 100 .

[0316] like Fig. 12A As shown, the stacked structure 100 includes a plurality of second dielectric layers 120 and a plurality of gate layers 210. The second dielectric layers 120 and the gate layers 210 are arranged in an overlapping manner.

[0317] Exemplarily, the second dielectric layer 120 and the gate layer 210 are overlapped in the third direction z. The third direction z is also the thickness direction of the stacked structure 100.

[0318] In the embodiment of the present application, there is no limitation on the number of the second dielectric layers 120 and the number of the gate layers 210 in the stacked structure 100. For example, the stacked structure 100 may include a plurality of pairs of the second dielectric layers 120 and the gate layers 210, and the number of pairs may be selected according to various application scenarios, for example, the number of pairs may be 32, 64, 96, 128, 160, 192, 224, 256 or more.

[0319] The material of the second dielectric layer 120 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0320] The material of the gate layer 210 may include, for example, metal conductive materials such as tungsten, cobalt, copper, aluminum, titanium, tantalum or nickel, etc. This embodiment of the present application does not limit this.

[0321] Continue to refer Fig. 12A , the first dielectric layer 110 is disposed on the stacked structure 100 .

[0322] For example, the material of the first dielectric layer 110 may include silicon oxide, silicon nitride or silicon oxynitride, etc. The material of the first dielectric layer 110 and the material of the second dielectric layer 120 may be the same or different, which is not limited in the present embodiment.

[0323] Continue to refer Fig. 12A , the second channel layer 320 runs through the stack structure 100 .

[0324] Illustratively, the second channel layer 320 extends from the surface of the stack structure 100 into the stack structure 100 and penetrates the stack structure 100 .

[0325] The second channel layer 320 may include, for example, a circular annular column or a rectangular annular column, etc. The present application embodiment does not limit this, and it is only necessary to ensure that the second channel layer 320 is an annular column structure.

[0326] like Fig. 12A As shown, a second channel dielectric 520 is further disposed in the second channel layer 320 .

[0327] The material of the second channel dielectric 520 may include, for example, insulating materials such as silicon oxide, etc. This embodiment of the present application does not limit this.

[0328] In some embodiments, Fig. 12A As shown, a functional layer 630 is further disposed between the second channel layer 320 and the stacked structure 100 .

[0329] For example, Fig. 12A As shown, along the direction of the stacked structure 100 pointing to the second channel layer 320 , the functional layer 630 may include a barrier layer 631 , a storage layer 632 , and a tunneling layer 633 which are sequentially stacked.

[0330] Exemplarily, the material of the barrier layer 631 may include, for example, one or more combinations of silicon oxide, silicon oxynitride, or other high dielectric constant materials. The material of the storage layer 632 may include, for example, one or more combinations of silicon nitride, silicon oxynitride, or silicon. The material of the tunneling layer 633 may include, for example, at least one of silicon oxide or silicon oxynitride.

[0331] Alternatively, illustratively, the functional layer 630 may also be a composite layer including a combination of silicon oxide / silicon nitride / silicon oxide (ONO).

[0332] It is explained here that the material of the barrier layer 631 , the material of the first dielectric layer 110 , and the material of the second dielectric layer 120 may be the same or different.

[0333] Continue to refer Fig. 12A , the first channel layer 310 is located in the first dielectric layer 110 , and the first channel layer 310 is connected to the second channel layer 320 .

[0334] Exemplarily, the first channel layer 310 further extends to a side of the top selection gate 410 close to the stack structure 100 .

[0335] That is, the first channel layer 310 also covers the side of the top selection gate 410 close to the stack structure 100 .

[0336] like Fig. 12A As shown, the first channel layer 310 is disposed between the top selection gate 410 and the first dielectric layer 110 .

[0337] like Fig. 12A As shown, the semiconductor structure 10 further includes a gate oxide layer 401 .

[0338] The gate oxide layer 401 is disposed between the first channel layer 310 and the top selection gate 410 .

[0339] The material of the gate oxide layer 401 may include, for example, silicon oxide, etc. This embodiment of the present application does not limit this.

[0340] like Fig. 12B As shown, along a direction perpendicular to the thickness direction (third direction z) of the stacked structure 100 , the maximum dimension of the first channel layer 310 is greater than the maximum dimension of the second channel layer 320 .

[0341] For example, Fig. 12B As shown, along the first direction x, a maximum dimension h1 of the first channel layer 310 is greater than a maximum dimension h2 of the second channel layer 320 .

[0342] Exemplarily, the maximum dimension h1 of the first channel layer 310 is the maximum dimension of the inner wall of the first channel layer 310, and the maximum dimension h2 of the second channel layer 320 is the maximum dimension of the inner wall of the second channel layer 320. Alternatively, exemplary, the maximum dimension h1 of the first channel layer 310 may also be the maximum dimension of the outer wall of the first channel layer 310. The present application embodiment does not limit this, and it can be reasonably set according to actual conditions.

[0343] Or, for example, Fig. 12C As shown, along the second direction y, a maximum dimension h1 of the first channel layer 310 is greater than a maximum dimension h2 of the second channel layer 320 .

[0344] It is explained here that the plane formed by the first direction x and the second direction y is parallel to the plane where the stacking structure 100 is located, that is, the plane formed by the first direction x and the second direction y is perpendicular to the third direction z. The first direction x and the second direction y intersect, for example, the first direction x and the second direction y are perpendicular.

[0345] Regarding the connection line 420, Fig. 12A and Fig.12D As shown, Fig.12D for Fig. 12A Schematic top view of a semiconductor structure.

[0346] The connection line 420 is located in the first dielectric layer 110, and the top selection gate 410 is connected to the connection line 420. The top selection gate 410 is located on the side of the connection line 420 close to the stack structure 100. Fig. 12A As shown, the top selection gate 410 is protruded from the connection line 420 close to the stack structure 100 .

[0347] That is, the top selection gate 410 is located between the connection line 420 and the stack structure 100 .

[0348] For example, Fig. 12A and Fig.12D As shown, the connection line 420 extends along the first direction x.

[0349] In the embodiment of the present application, the number of the connection lines 420 is not limited. For example, the semiconductor structure 10 includes a plurality of connection lines 420. The plurality of connection lines 420 are arranged at intervals along the second direction y.

[0350] That is, the extending direction of the connection line 420 intersects with the direction in which the plurality of connection lines 420 are arranged at intervals.

[0351] For example, Fig.12D As shown, along the first direction x, the connection line 420 passes through the first channel layer 310 .

[0352] That is, the connection line 420 penetrates the first channel layer 310 .

[0353] like Fig.12D As shown, the first channel layer 310 includes a first portion 311 and a second portion 312. The first portion 311 is a portion of the first channel layer 310 covered by the connection line 420, and the second portion 312 is a portion of the first channel layer 310 other than the first portion 311. In other words, the second portion 312 can be understood as a portion of the first channel layer 310 not covered by the connection line 420.

[0354] In other words, Fig. 12A As shown, one end of the second portion 312 of the first channel layer 310 away from the stack structure 100 exceeds the connection line 420 .

[0355] The second portion 312 of the first channel layer 310 is used to connect to the bit line contact structure 430 .

[0356] like Fig.12D As shown, along the direction perpendicular to the extending direction of the connecting line 420, that is, along the second direction y, the ratio of the size n1 of the first part 311 to the size n2 of the second part 312 is in the range of 0.25 to 1. For example, the ratio of the size n1 of the first part 311 to the size n2 of the second part 312 can be 0.25, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or 1, etc. This embodiment of the application does not limit this, and it can be reasonably set according to actual conditions.

[0357] Continue to refer Fig.12D Along the second direction y, the size of the connection line between adjacent top selection gates is called a first size L1, and the size of the top selection gate is called a second size L2. The first size L1 is smaller than the second size L2.

[0358] The ratio of the first size L1 to the second size L2 ranges from 0.5 to 1. For example, the ratio of the first size L1 to the second size L2 may be 0.5, 0.6, 0.7, 0.8, 0.9 or 1, etc.

[0359] In some embodiments, Fig.13A As shown, the semiconductor structure 10 further includes a third dielectric layer 130 and a bit line contact structure 430. The bit line contact structure 430 is located in the third dielectric layer 130.

[0360] like Fig.13A As shown, the third dielectric layer 130 is located on a side of the first dielectric layer 110 away from the stack structure 100 .

[0361] The third dielectric layer 130 may be a single dielectric layer, or may be a plurality of dielectric layers stacked in sequence, which is not limited in the present embodiment.

[0362] The material of the third dielectric layer 130 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0363] For example, Fig. 13B As shown, Fig. 13B for Fig.13A Cross-sectional view along line B1B2 The bit line contact structure 430 penetrates the third dielectric layer 130 , and the bit line contact structure 430 is connected to the first channel layer 310 .

[0364] That is, the bit line contact structure 430 is connected to the second portion 312 of the first channel layer 310 .

[0365] For example, the material of the bit line contact structure 430 may include a metal conductive material such as tungsten, cobalt, copper, aluminum, titanium, tantalum or nickel, etc. This embodiment of the present application does not limit this.

[0366] For example, Fig. 13C As shown, Fig. 13C for Fig.13A The schematic semiconductor structure is a side view of a plane formed in a first direction x and a third direction z.

[0367] What is explained here is that Fig. 13C The illustrated first channel layer 310 is a first portion 311 of the first channel layer 310 . The first portion 311 of the first channel layer 310 is not connected to the bit line contact structure 430 .

[0368] like Fig. 13B and Fig. 13C As shown, a bit line contact dielectric layer 431 is further disposed between the bit line contact structure 430 and the third dielectric layer 130 .

[0369] The bit line contact dielectric layer 431 covers the sidewalls of the bit line contact structure 430 and the surface of the bit line contact structure 430 close to the third dielectric layer 130 .

[0370] The material of the bit line contact dielectric layer 431 may include titanium nitride, for example.

[0371] Continue to refer Fig.13A The semiconductor structure 10 further includes a fourth dielectric layer 140. The fourth dielectric layer 140 is located between the connection line 420 and the bit line contact structure 430. That is, the connection line 420 and the bit line contact structure 430 are isolated by the fourth dielectric layer 140.

[0372] The fourth dielectric layer 140 may be an integral structure with the third dielectric layer 130. Alternatively, the fourth dielectric layer 140 may be prepared separately from the third dielectric layer 130. This embodiment of the present application does not limit this.

[0373] In some embodiments, Fig.13A As shown, the semiconductor structure 10 further includes a top selection gate contact structure 440 located in the third dielectric layer 130 .

[0374] like Fig.13A As shown, the top select gate contact structure 440 is connected to the connection line 420 .

[0375] Exemplarily, the material of the top selection gate contact structure 440 may include a metal conductive material such as tungsten, cobalt, copper, aluminum, titanium, tantalum or nickel. In the implementation of the present application, the material of the top selection gate contact structure 440 may be the same as the material of the bit line contact structure 430. Alternatively, the material of the top selection gate contact structure 440 may be different from the material of the bit line contact structure 430. The implementation of the present application does not limit this.

[0376] like Fig.13D As shown, Fig.13D for Fig.13A A gate contact dielectric layer 441 is further disposed between the top selection gate contact structure 440 and the third dielectric layer 130 .

[0377] The gate contact dielectric layer 441 covers the sidewalls of the top selection gate contact structure 440 and the surface of the top selection gate contact structure 440 close to the third dielectric layer 130 .

[0378] The material of the gate contact dielectric layer 441 may include titanium nitride, for example.

[0379] In some embodiments, the stacked structure 100 is also formed on a substrate (not shown in the figure). That is, the substrate is located on the side of the stacked structure 100 away from the first dielectric layer 110. The material of the substrate may include, for example, a semiconductor material. For example, silicon (single crystal silicon, polycrystalline silicon or amorphous silicon), germanium (single crystal germanium), silicon germanium, silicon carbide, glass, gallium nitride, gallium arsenide, glass, SOI (silicon on insulator), GOI (germanium on insulator) or other suitable III-V compound substrates, etc. The substrate may also be P-type doped or N-type doped.

[0380] In the semiconductor structure 10 provided in the first embodiment of the present application, the first channel layer 310 surrounds the top selection gate 410 (the top selection gate 410 is located in the first channel layer 310), and the top selection gate 410 is connected by the connection line 420 to achieve separate control of the top selection gate 410. In addition, since the top selection gate 410 is located on the side of the connection line 420 close to the stack structure 100, that is, the top selection gate 410 and the connection line 420 are arranged along the thickness direction z of the stack structure 100, the size of the semiconductor structure 10 in the direction perpendicular to the thickness z direction of the stack structure and perpendicular to the extension direction of the connection line 420 is reduced. In addition, in the semiconductor structure 10 provided in the embodiment of the present application, the first channel layer 310 and the second channel layer 320 are connected, which avoids the influence of dry etching plasma damage on the channel, thereby improving the channel performance.

[0381] Embodiment 2

[0382] The main difference between the second embodiment and the first embodiment is that the first channel layer 310 and the second channel layer 320 are close to each other and have the same size at both ends. Along the second direction y, a plurality of top selection gates 410 are distributed on opposite sides of the connection line 420. The embodiment of the present application also provides a semiconductor structure, such as Fig.14 As shown, the semiconductor structure 10 includes a stacked structure 100 and a first dielectric layer 110 . The first channel layer 310 penetrates the first dielectric layer 110 , and the second channel layer 320 penetrates the stacked structure 100 .

[0383] The present application also provides a method for preparing a semiconductor structure. Fig.15 As shown, including:

[0384] S21 , providing a first dielectric layer 110 and a stacked structure 100 .

[0385] In some embodiments, step S21 includes:

[0386] S211 , forming an initial stacking structure 200 .

[0387] S212 , forming a first dielectric layer 110 on the initial stacked structure 200 .

[0388] S213, opening a first channel hole 601.

[0389] The forming method in steps S211 - S213 is the same as that in steps S111 - S113 , and reference may be made to the above description of S211 - S213 .

[0390] S214 , forming a first channel structure and a second channel structure in the first channel hole 601 .

[0391] In some embodiments, step S214 may include:

[0392] S2141 , forming a channel layer 610 covering the sidewalls of the first channel hole 601 .

[0393] S2142 , forming a channel dielectric 620 filled in the channel layer 610 .

[0394] The materials and formation methods of the channel layer 610 and the channel dielectric in steps S2141 and S2142 are the same as those in steps S1141 and S1142, and reference may be made to the above descriptions of S1141 and S1142.

[0395] S2143, such as Fig.16A As shown, the channel dielectric 620 in the first dielectric layer 110 is removed, and the first channel dielectric 510 is filled.

[0396] For example, Fig.16A As shown, the channel dielectric 620 in the first dielectric layer 110 is removed.

[0397] At this time, the remaining unetched channel dielectric 620 serves as the second channel dielectric 520 . In other words, the channel layer 610 located in the initial stacked structure 200 serves as the second channel layer 320 .

[0398] Then, the channel layer 610 of the first dielectric layer 110 is filled with a channel dielectric material to form a first channel dielectric 510. The material of the first channel dielectric 510 may include, for example, aluminum oxide or nitride doped silicon carbide (NDC). The present application embodiment does not limit this, and it is only necessary to ensure that the material of the first channel dielectric 510 is different from the material of the second channel dielectric 520.

[0399] In this way, when the first channel dielectric 510 is subsequently removed, the second channel dielectric 520 will not be over-etched.

[0400] The method for forming the second channel dielectric 520 is the same as the method for forming the channel dielectric 620 in the channel layer 610. For example, a channel dielectric material may be first formed in the channel layer 610 of the first dielectric layer 110 and on the surface of the channel layer 610 away from the initial stacking structure, and then the surface of the channel dielectric material away from the initial stacking structure 200 is ground to remove the channel dielectric material located on the surface of the channel layer 610 away from the initial stacking structure, so as to form the first channel dielectric 510.

[0401] It is explained here that when the channel dielectric material away from the surface of the initial stacking structure 200 is polished, the channel layer 610 and the functional layer 630 located on the surface of the first dielectric layer 110 away from the initial stacking structure 200 are also removed simultaneously.

[0402] At this time, the channel layer 610 located in the first dielectric layer 110 is used as the first channel layer 310, and the first channel layer 310 and the first channel dielectric 510 constitute the first channel structure 101. The channel layer 610 located in the initial stacking structure 200 is used as the second channel layer 320, and the second channel layer 320 and the second channel dielectric 520 constitute the second channel structure 102.

[0403] That is, the first channel structure 101 includes a first channel layer 310 and a first channel dielectric 510 , and the second channel structure 102 includes a second channel layer 320 and a second channel dielectric 520 .

[0404] For example, Fig. 16B As shown, the first dielectric layer 110 includes a plurality of first channel layers 310. The plurality of first channel layers 310 are arranged at intervals in a plane formed by a first direction x and a second direction y. The plane formed by the first direction x and the second direction y is parallel to the plane where the initial stacking structure 200 is located, and the plane formed by the first direction x and the second direction y is perpendicular to the thickness direction of the initial stacking structure 200. The first direction x and the second direction y intersect, for example, the first direction x and the second direction y are perpendicular. For the convenience of illustration, the thickness direction of the initial stacking structure 200 is referred to as the third direction z. That is to say, any two directions of the first direction x, the second direction y and the third direction z intersect, for example, any two directions of the first direction x, the second direction y and the third direction z are perpendicular.

[0405] like Fig. 16B As shown, a plurality of first channel layers 310 are arranged into at least two channel rows 300 .

[0406] For example, the at least two channel rows 300 include a first channel row 301 and a second channel row 302 that are adjacent to each other.

[0407] The first channel row 301 includes at least one first channel layer 310 , and the second channel row 302 also includes at least one first channel layer 310 .

[0408] The number of first channel layers 310 included in the first channel row 301 and the number of first channel layers 310 included in the second channel row 302 may be the same or different. This embodiment of the present application does not limit this. For example, Fig.6I As shown, along the first direction x, the plurality of first channel layers 310 included in the channel row 300 are sequentially arranged at intervals.

[0409] For example, Fig. 16B As shown, the first channel layers 310 of the first channel row 301 and the first channel layers 310 of the second channel row 302 are alternately arranged.

[0410] In this way, space can be saved and the integration level of the semiconductor structure 10 can be improved.

[0411] S215, such as Fig. 16C As shown, the sacrificial gate layer 220 is removed and replaced by the gate layer 210 .

[0412] like Fig. 16C As shown, the sacrificial gate layer 220 is replaced by the gate layer 210 , and the initial stacked structure 200 is replaced by the stacked structure 100 .

[0413] The method of forming the stacked structure 100 in step S215 is the same as that in step S151 , and reference may be made to the above description of S151 .

[0414] S22, such as Fig.17A As shown, a connection groove 421 is opened on the surface of the first dielectric layer 110 away from the stack structure 100 .

[0415] The method of forming the connection groove 421 in step S22 is the same as the method of forming the connection groove 421 in step S12 , and reference may be made to the above description of S12 .

[0416] like Fig.17A As shown, a patterned mask layer is formed on a surface of the first dielectric layer 110 away from the stacked structure 100 , and the patterned mask layer exposes a predetermined formation area of ​​the connection groove 421 .

[0417] like Fig.17A As shown, along the third direction z, the connection groove 421 overlaps with at least a portion of the first channel structure 101 .

[0418] For example, Fig. 17B As shown, the connection groove 421 is arranged across two channel rows (the first channel row 301 and the second channel row 302 ).

[0419] Exemplarily, along the second direction y, the size d1 of the connection groove 421 is 60 nm to 100 nm. For example, the size d1 of the connection groove 421 is 60 nm, 70 nm, 80 nm, 90 nm or 100 nm.

[0420] For example, along the second direction y, a size d1 of the connection groove 421 is greater than a size of the first channel layer 310 .

[0421] It is explained here that after the connection groove 421 is opened, the mask layer is removed.

[0422] S23, such as Fig.18 As shown, at least a portion of the first channel dielectric 510 is removed.

[0423] The method for removing the first channel dielectric 510 in step S23 is the same as the method for removing the first channel dielectric 510 in step S13 , and reference may be made to the above description of S13 .

[0424] S24, such as Fig.19A and Fig.19B As shown, a conductive structure 400 is formed in the connecting groove 421 .

[0425] The method of forming the conductive structure 400 in step S24 is the same as the method of forming the conductive structure 400 in step S14 , and reference may be made to the above description of S14 .

[0426] For example, Fig.19B As shown, the conductive structure 400 located in the first channel layer 310 is referred to as a top selection gate 410 , and the conductive structure 400 located in the connection groove 421 is referred to as a connection line 420 .

[0427] That is, the conductive structure 400 includes a top selection gate 410 filled in the first channel layer 310 , and a connection line 420 connected to the top selection gate 410 .

[0428] At this time, if Fig.19B As shown, the first channel layer 310 is farther away from the surface of the stack structure 100 than the connection line 420 is farther away from the surface of the stack structure 100 .

[0429] That is, the connection line 420 is away from the surface of the stack structure 100 and does not exceed the surface of the first channel layer 310 away from the stack structure 100 .

[0430] In this way, it is convenient to prepare the bit line contact structure 430 connected to the first channel layer 310 later.

[0431] like Fig.19C As shown, along the second direction y, a plurality of top selection gates 410 are distributed on both sides of the connection line 420 .

[0432] Exemplarily, the top selection gate 410 distributed on one side of the connection line 420 is located in the first channel layer 310 in the first channel row 301 , and the top selection gate 410 distributed on the other side of the connection line 420 is located in the first channel layer 310 in the second channel row 302 .

[0433] S25 , forming a bit line contact structure.

[0434] In some embodiments, step S25 may include:

[0435] S251, such as Fig. 20A As shown, a fourth dielectric layer 140 is formed.

[0436] The method for forming the fourth dielectric layer 140 in step S251 is the same as the method for forming the fourth dielectric layer 140 in step S151 , and reference may be made to the above description of S151 .

[0437] S252, such as Fig. 20B As shown, a third dielectric layer 130 is formed.

[0438] The method for forming the third dielectric layer 130 in step S252 is the same as the method for forming the third dielectric layer 130 in step S152 , and reference may be made to the above description of S152 .

[0439] S253, such as Fig. 20C As shown, a first contact hole 603 is opened.

[0440] The first contact hole 603 is used for subsequently forming a bit line contact structure.

[0441] The method of forming the first contact hole 603 in S253 is the same as the method of forming the first contact hole 603 in the first embodiment, and reference may be made to the relevant description in the first embodiment.

[0442] S254, such as Fig.20D As shown, a bit line contact structure 430 is formed in the first contact hole 603 .

[0443] The method of forming the bit line contact structure 430 in S254 is the same as the method of forming the bit line contact structure 430 in the first embodiment, and reference may be made to the relevant description in the first embodiment.

[0444] S26, forming a top selection gate contact structure.

[0445] The method of forming the top selection gate contact structure 440 in step S26 is the same as the method of forming the top selection gate contact structure 440 in the first embodiment, and reference may be made to the relevant description in the first embodiment.

[0446] It is explained here that the above-mentioned preparation method provided in Example 2 of the present application is not limited to any step sequence and can be reasonably adjusted as needed.

[0447] In addition, the above steps S21-S26 may remove some steps as needed, and are not limited to including every step. Some steps may also be added as needed, and are not limited to only including the above steps.

[0448] The embodiment of the present application also provides a semiconductor structure, which can be prepared using the semiconductor structure preparation method provided in the second embodiment.

[0449] The semiconductor structure of the second embodiment is different from that of the first embodiment in that the first channel layer 310 and the second channel layer 320 are close to each other and have the same size at both ends. Along the second direction y, a plurality of top selection gates 410 are distributed on opposite sides of the connection line 420 .

[0450] like Fig.21A As shown, the semiconductor structure 10 includes a first dielectric layer 110 and a stacked structure 100 , a first channel layer 310 , a second channel layer 320 , a top selection gate 410 , and a connection line 420 .

[0451] The first channel layer 310 penetrates the first dielectric layer 110, and the second channel layer 320 penetrates the stacked structure 100. The size of the first channel layer 310 near one end of the second channel layer 320 is the same as the size of the second channel layer 320 near one end of the first channel layer 310.

[0452] That is to say, Fig.21A As shown, the first channel layer 310 and the second channel layer 320 are continuous.

[0453] Since the two ends of the first channel layer 310 and the second channel layer 320 close to each other in the second embodiment of the present application have the same size, the first channel layer 310 and the second channel layer 320 have the same size in the direction perpendicular to the third direction z. In other words, the size of the first channel layer 310 is smaller in the direction perpendicular to the third direction z.

[0454] like Fig.21B As shown, in the second embodiment, the connection line 420 is arranged across two adjacent channel rows 300. Exemplarily, the connection line 420 is connected to the top selection gate 410 in the first channel layer 310 in the first channel row 301, and the connection line 420 is also connected to the top selection gate 410 in the first channel layer 310 in the second channel row 302.

[0455] That is to say, in the second embodiment, two channel rows 300 can be controlled independently.

[0456] In the second embodiment, the connection line 420 is arranged across two rows of channel layers 300 , which can avoid the need to reduce the size of the connection line 420 due to the small size of the first channel layer 310 .

[0457] like Fig. 21C As shown, the semiconductor structure 10 further includes a bit line contact structure 430 and a top selection gate contact structure ( Fig. 21C not shown).

[0458] like Fig.21D and Fig.21E As shown, the bit line contact structure 430 is connected to the first channel layer 310 .

[0459] Embodiment 3

[0460] The main difference between the third embodiment and the first embodiment is that the first channel layer 310 and the second channel layer 320 are close to each other and have the same size at both ends. The present application also provides a semiconductor structure, such as Fig. 22 As shown, the semiconductor structure 10 includes a first dielectric layer 110 and a stacked structure 100 , a first channel layer 310 , a second channel layer 320 , and a top selection gate 410 , which are stacked.

[0461] like Fig. 22 As shown, the first channel layer 310 and the second channel layer 320 are connected, and the first channel layer 310 and the second channel layer 320 are close to each other and have the same size at both ends.

[0462] That is, along the direction perpendicular to the third direction z, the size of the first channel layer 310 at one end close to the second channel layer 320 is the same as the size of the second channel layer 320 at one end close to the first channel layer 310 .

[0463] Continue to refer Fig. 22 The connection line 420 penetrates the first channel layer 310 . The connection line 420 penetrates one channel row 300 .

[0464] It is explained here that the semiconductor structure 10 provided in the third embodiment of the present application further includes a bit line contact structure ( Fig. 22 Not shown) and top select gate contact structure ( Fig. 22 not shown).

[0465] The bit line contact structure is connected to the first channel layer 310 , and the top selection gate contact structure is connected to the connection line 420 .

[0466] The bit line contact structure and the top selection gate contact structure are the same as those described in the above embodiment 1, and reference may be made to the related descriptions of the bit line contact structure and the top selection gate contact structure in the above embodiment 1.

[0467] The present application also provides a method for preparing a semiconductor structure. Fig.23 As shown, including:

[0468] S31, such as Fig.24A As shown, a first dielectric layer 110 and a stacked structure 100 are provided.

[0469] Step S31 is the same as the above step S21, and reference may be made to the above description of S21.

[0470] S32, such as Fig. 24B As shown, a connection groove 421 is opened on the surface of the first dielectric layer 110 away from the stack structure 100 .

[0471] Step S32 is the same as the above step S12, and reference may be made to the above description of S12.

[0472] like Fig. 24B As shown, the connection groove 421 only penetrates one channel row 300. In other words, the connection groove 421 is arranged across one channel row 300.

[0473] S33, such as Fig.24C As shown, at least a portion of the first channel dielectric 510 is removed.

[0474] Step S33 is the same as the above step S13, and reference may be made to the above description of S13.

[0475] S34, such as Fig.24D As shown, a conductive structure 400 is formed in the connecting groove 421 .

[0476] Step S34 is the same as the above step S14, and reference may be made to the above description of S14.

[0477] like Fig.24D As shown, the conductive structure 400 located in the first dielectric layer 110 serves as a top selection gate 410 , and the conductive structure 400 located in the connection groove 421 serves as a connection line 420 .

[0478] S35, such as Fig.24E As shown, a bit line contact structure 430 is formed.

[0479] Step S35 is the same as the above step S15, and reference may be made to the above description of S15.

[0480] like Fig.24E As shown, the bit line contact structure 430 is connected to the first channel 310 .

[0481] S36, such as Fig.24F As shown, a top select gate contact structure 440 is formed.

[0482] Step S36 is the same as the above step S16, and reference may be made to the above description of S16.

[0483] like Fig.24F As shown, the top select gate contact structure 440 is connected to the connection line 420 .

[0484] It is explained here that the above-mentioned preparation method provided in Example 3 of the present application is not limited to any step sequence and can be reasonably adjusted as needed.

[0485] In addition, the above steps S31-S36 may remove some steps as needed, and are not limited to include every step. Some steps may also be added as needed, and are not limited to only include the above steps.

[0486] Embodiment 4

[0487] The main difference between the fourth embodiment and the first embodiment is that: along the second direction y, a plurality of top selection gates 410 are distributed on opposite sides of the connection line 420. The present application also provides a semiconductor structure, such as Fig.25 As shown, the semiconductor structure 10 includes a first dielectric layer 110 and a stacked structure 100 , a first channel layer 310 , a second channel layer 320 , and a top selection gate 410 , which are stacked.

[0488] like Fig.25 As shown, along the direction perpendicular to the third direction z, the size of the first channel layer 310 is larger than that of the second channel layer 320 , and the first channel layer 310 also extends to a side of the top selection gate 410 close to the stack structure 100 .

[0489] Continue to refer Fig.25 The connection line 420 runs through two adjacent channel rows 300 . That is, the plurality of top selection gates 410 are distributed on opposite sides of the connection line 420 .

[0490] It is explained here that the semiconductor structure 10 provided in the fourth embodiment of the present application further includes a bit line contact structure ( Fig.25 Not shown) and top select gate contact structure ( Fig.25 not shown).

[0491] The bit line contact structure is connected to the first channel layer 310 , and the top selection gate contact structure is connected to the connection line 420 .

[0492] The bit line contact structure and the top selection gate contact structure are the same as those described in the above embodiment 1, and reference may be made to the related descriptions of the bit line contact structure and the top selection gate contact structure in the above embodiment 1.

[0493] The present application also provides a method for preparing a semiconductor structure. Fig.26As shown, including:

[0494] S41, such as Fig.27A As shown, a first dielectric layer 110 and a stacked structure 100 are provided.

[0495] Step S41 is the same as the above step S11, and reference may be made to the above description of S11.

[0496] S42, such as Fig.27B As shown, a connection groove 421 is opened on the surface of the first dielectric layer 110 away from the stack structure 100 .

[0497] Step S72 is the same as the above step S22, and reference may be made to the above description of S22.

[0498] like Fig.27B As shown, the connection groove 421 penetrates two adjacent channel rows 300. In other words, the connection groove 421 is arranged across two adjacent channel rows 300.

[0499] S43, such as Fig.27C As shown, at least a portion of the first channel dielectric 510 is removed.

[0500] Step S43 is the same as the above step S23, and reference may be made to the above description of S23.

[0501] S44, such as Fig.27D As shown, a conductive structure 400 is formed in the connecting groove 421 .

[0502] Step S44 is the same as the above step S24, and reference may be made to the above description of S24.

[0503] like Fig.27D As shown, the conductive structure 400 located in the first dielectric layer 110 serves as a top selection gate 410 , and the conductive structure 400 located in the connection groove 421 serves as a connection line 420 .

[0504] S45 , forming a bit line contact structure.

[0505] Step S45 is the same as the above step S25, and reference may be made to the above description of S25.

[0506] S46, forming a top selection gate contact structure.

[0507] Step S46 is the same as the above step S26, and reference may be made to the above description of S26.

[0508] It is explained here that the above-mentioned preparation method provided in Example 4 of the present application is not limited to any step sequence and can be reasonably adjusted as needed.

[0509] In addition, the above steps S41-S46 may remove some steps as needed, and are not limited to including every step. Some steps may also be added as needed, and are not limited to only including the above steps.

[0510] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A first dielectric layer and a stacked structure are stacked; the stacked structure includes a plurality of second dielectric layers and a plurality of gate layers; The second dielectric layer and the gate layer are arranged to overlap; A first channel layer, located in the first dielectric layer; A second channel layer runs through the stack structure; the first channel layer is connected to the second channel layer; A connecting line, located in the first dielectric layer; A top selection gate is connected to the connection line, the top selection gate is located on a side of the connection line close to the stack structure, and the first channel layer surrounds the top selection gate.

2. The semiconductor structure according to claim 1, characterized in that: The connection line passes through the first channel layer along the first direction; a first dimension of the connection line located between adjacent top selection gates in the second direction is smaller than a second dimension of the top selection gates in the second direction; The first direction is the extending direction of the connecting line, the second direction is perpendicular to the first direction, and a plane formed by the first direction and the second direction is parallel to a plane where the stacking structure is located.

3. The semiconductor structure according to claim 2, characterized in that: The ratio of the first size to the second size ranges from 0.5 to 1.

4. The semiconductor structure according to claim 1, characterized in that The semiconductor structure includes a plurality of the first channel layers; the plurality of first channel layers are arranged into at least two channel rows, and the first channel layers in the channel rows are arranged at intervals along the extension direction of the connecting line; the at least two channel rows include adjacent first channel rows and second channel rows; along a second direction, the plurality of top selection gates are distributed on both sides of the connecting line, and the second direction is a direction perpendicular to the extension direction of the connecting line; the top selection gates distributed on one side of the connecting line are located in the first channel layer in the first channel row; the top selection gates distributed on the other side of the connecting line are located in the first channel layer in the second channel row.

5. The semiconductor structure according to claim 4, characterized in that: The first channel layers in the first channel row and the first channel layers in the second channel row are arranged alternately.

6. The semiconductor structure according to claim 1, characterized in that The first channel layer includes a first portion and a second portion, the first portion is a portion of the first channel layer covered by the connection line, and the second portion is a portion of the first channel layer excluding the first portion.

7. The semiconductor structure according to claim 6, characterized in that: Along a direction perpendicular to the extending direction of the connecting line, a ratio of a size of the first portion to a size of the second portion is in a range of 0.25 to 1.

8. The semiconductor structure according to claim 6 or 7, characterized in that: One end of the second portion away from the stacking structure exceeds the connecting line.

9. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure includes a plurality of connecting lines; the plurality of connecting lines are distributed at intervals.

10. The semiconductor structure according to claim 1, characterized in that The first channel layer is disposed between the top selection gate and the first dielectric layer.

11. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes a gate oxide layer, wherein the gate oxide layer is located between the first channel layer and the top selection gate.

12. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further includes a third dielectric layer and a bit line contact structure located in the third dielectric layer; the third dielectric layer is located on a side of the first dielectric layer away from the stacking structure, and the bit line contact structure is connected to the first channel layer.

13. The semiconductor structure according to claim 12, characterized in that: The bit line contact structure penetrates the third dielectric layer and is connected to the second portion of the first channel layer.

14. The semiconductor structure according to claim 12 or 13, characterized in that: The connecting line and the bit line contact structure are isolated by a fourth dielectric layer.

15. The semiconductor structure according to claim 1, wherein: The first channel layer and the second channel layer have the same size at two ends close to each other.

16. The semiconductor structure according to claim 1, characterized in that The first channel layer extends to a side of the top selection gate close to the stack structure.

17. The semiconductor structure according to claim 16, characterized in that: Along a direction perpendicular to a thickness direction of the stacked structure, a maximum dimension of the first channel layer is greater than a maximum dimension of the second channel layer.

18. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a third dielectric layer and a top selection gate contact structure located in the third dielectric layer; the third dielectric layer is located on a side of the first dielectric layer away from the stacking structure, and the top selection gate contact structure is connected to the connection line.

19. The semiconductor structure according to claim 18, characterized in that The semiconductor structure further includes a bit line contact structure; the bit line contact structure is located in the third dielectric layer and connected to the first channel layer; The material of the top selection gate contact structure is the same as that of the bit line contact structure.

20. A method for preparing a semiconductor structure, characterized in that: include: A first dielectric layer and a stacked structure are provided; the stacked structure includes a plurality of second dielectric layers and a plurality of gate layers, the second dielectric layers and the gate layers are overlapped; the first dielectric layer includes a first channel structure, and the stacked structure includes a second channel structure; the first channel structure runs through the first dielectric layer, the first channel structure includes a first channel layer and a first channel dielectric located in the first channel layer; the second channel structure runs through the stacked structure, the second channel structure includes a second channel layer and a second channel dielectric located in the second channel layer; the first channel layer is connected to the second channel layer; A connection groove is formed on a surface of the first dielectric layer away from the stacking structure; Along the thickness direction of the stacked structure, the connecting groove overlaps with a portion of the first channel structure; removing at least a portion of the first channel dielectric; A conductive structure is formed in the connection groove, wherein the conductive structure includes: a top selection gate filling the first channel layer, and a connection line connected to the top selection gate.

21. The preparation method according to claim 20, characterized in that: Opening the connection slot includes: Along the first direction, the connecting groove passes through the first channel layer; the first direction is the extension direction of the connecting groove; along the second direction, the size of the connecting groove is smaller than the size of the first channel layer; the second direction is perpendicular to the first direction, and the plane formed by the first direction and the second direction is parallel to the plane where the stacking structure is located.

22. The preparation method according to claim 20, characterized in that: The first dielectric layer includes a plurality of the first channel layers; the plurality of the first channel layers are arranged into at least two channel rows; the at least two channel rows include adjacent first channel rows and second channel rows; Opening the connection slot includes: Along a first direction, the connecting groove passes through the first channel row and the second channel row; the first direction is an extending direction of the connecting groove.

23. The preparation method according to claim 20, characterized in that: A first dielectric layer and a stacked structure are provided, comprising: forming an initial stacking structure, wherein the initial stacking structure comprises a plurality of second dielectric layers and a plurality of sacrificial gate layers, wherein the second dielectric layers and the sacrificial gate layers are arranged in an overlapping manner; forming the first dielectric layer on the initial stacked structure; Opening a first channel hole penetrating the first dielectric layer and the initial stacking structure; forming the first channel structure and the second channel structure in the first channel hole; The sacrificial gate layer is removed, and the sacrificial gate layer is replaced by the gate layer.

24. The preparation method according to claim 23, characterized in that: Forming the first channel structure and the second channel structure includes: forming a channel layer covering the first channel hole; forming a channel dielectric filled in the channel layer; Among them, the channel layer located in the first dielectric layer serves as the first channel layer, the channel layer located in the initial stacking structure serves as the second channel layer, the channel medium located in the first dielectric layer serves as the first channel medium, and the channel medium located in the initial stacking structure serves as the second channel medium; the first channel medium and the first channel layer constitute the first channel structure, and the second channel medium and the second channel layer constitute the second channel structure.

25. The preparation method according to claim 23, characterized in that: Forming the first channel structure and the second channel structure includes: forming a channel layer covering the first channel hole; forming a channel dielectric filled in the channel layer; The channel layer and the channel medium located in the first dielectric layer are removed to form a second channel hole; the remaining channel layer is used as the second channel layer, and the remaining channel medium is used as the second channel medium; forming the first channel layer covering the bottom and sidewalls of the second channel hole; Filling the first channel dielectric in the first channel layer; The first channel medium and the first channel layer constitute the first channel structure, and the second channel medium and the second channel layer constitute the second channel structure.

26. The preparation method according to claim 20, characterized in that: After forming the top selection gate and the connection line, the manufacturing method further includes: A bit line contact structure is formed, wherein the bit line contact structure is connected to the first channel layer.

27. The preparation method according to claim 26, characterized in that: Forming the bit line contact structure includes: forming a third dielectric layer covering the first dielectric layer and away from the surface of the stacked structure, wherein the third dielectric layer also covers the top selection gate and the connection line; Etching a surface of the third dielectric layer away from the first dielectric layer to form a first contact hole, wherein the first contact hole exposes the channel layer; A bit line contact structure is formed in the first contact hole.

28. The preparation method according to claim 20, characterized in that: After forming the top selection gate and the connection line, the manufacturing method further includes: A top selection gate contact structure is formed, wherein the top selection gate contact structure is connected to the connection line.

29. The preparation method according to claim 28, characterized in that: Forming the top selection gate contact structure includes: forming a third dielectric layer covering the first dielectric layer and away from the surface of the stacked structure, wherein the third dielectric layer also covers the top selection gate and the connecting line; Etching a surface of the third dielectric layer away from the first dielectric layer to form a second contact hole, wherein the second contact hole exposes the connecting line; A top selection gate contact structure is formed in the second contact hole.

30. The preparation method according to claim 29, characterized in that: The preparation method further includes: forming a bit line contact structure, wherein the bit line contact structure is located in the third dielectric layer and connected to the first channel layer; The top selection gate contact structure and the bit line contact structure are formed in the same process step.

31. A storage system, characterized in that: include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1 to 19; The controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

32. An electronic device, characterized in that: Comprising a storage system as claimed in claim 31.

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