Novel structure in deep groove type super junction field effect transistor and manufacturing method

Abstract

The invention discloses a novel structure in a deep groove type super junction field effect transistor and a manufacturing method, the novel structure comprises a semiconductor layer arranged on a substrate, and the semiconductor layer is internally provided with a drift region of a first doping type; the groove enters the semiconductor layer from the surface of the semiconductor layer and is positioned in the drift region; the buffer layer is arranged on the surface of the inner wall of the groove, and a filling cavity is formed in the groove in the buffer layer; the buffer layer and the semiconductor layer contain the same first element, and the buffer layer further contains at least one second element different from the first element. According to the invention, material diffusion between materials inside and outside the trench can be effectively controlled, and the characteristic resistance of the drift region is further reduced, so that a finer and more stable voltage-withstanding characteristic is provided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit technology, and in particular to a novel structure and a manufacturing method of a deep trench super junction field effect transistor. Background Art

[0002] Compared with the traditional planar field effect transistor, the super junction field effect transistor has an ideal drift region characteristic resistance that exceeds the silicon limit (theoretical critical point) due to the structural change. Among them, the common super junction manufacturing method includes two methods, namely, forming a P-type column by multiple ion implantation in the N-type drift region on the substrate, or forming a P-type column by etching a deep trench and filling it. Of the above two methods, because the deep trench etching and filling method is relatively easy to control the diffusion at the boundary of N-type / P-type materials, it has a better effect on electrical withstand voltage.

[0003] As the device area continues to shrink, how to further reduce the characteristic resistance (Ron) of the drift region and reduce the diffusion at the boundary of N-type / P-type materials has become an important issue for continuous improvement. Summary of the invention

[0004] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a new structure and manufacturing method of a deep trench super junction field effect transistor.

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] The present invention provides a novel structure in a deep trench super junction field effect transistor, comprising:

[0007] A semiconductor layer disposed on the substrate, wherein a drift region of a first doping type is disposed in the semiconductor layer;

[0008] A trench extending from a surface of the semiconductor layer into the semiconductor layer and located in the drift region;

[0009] a buffer layer disposed on the inner wall surface of the groove, wherein a filling cavity is formed in the groove within the buffer layer;

[0010] The buffer layer and the semiconductor layer contain the same first element, and the buffer layer further contains at least one second element different from the first element.

[0011] Furthermore, the first element includes Si, the second element includes at least one of Ge, C, P, and As, and / or the content of the second element in the buffer layer changes gradually or gradiently in an inward direction along the inner wall of the groove.

[0012] Furthermore, the buffer layer is a single layer or a multilayer stack, and the materials of any two adjacent layers in the multilayer stack are different; or, the buffer layer includes a single layer formed by one of SiGe, SiGeC, SiC, SiP, SiAs, and SiAsC, or a multilayer stack formed by two or more of them.

[0013] Furthermore, the buffer layer contains doping impurities of a first doping type and / or doping impurities of a second doping type different from the first doping type.

[0014] Furthermore, it also includes: a filling layer of a second doping type different from the first doping type arranged in the cavity.

[0015] The present invention also provides a method for manufacturing a novel structure in a deep trench super junction field effect transistor, comprising:

[0016] Providing a substrate, and forming a semiconductor layer of a first doping type on a surface of the substrate to form a drift region;

[0017] forming a trench on a surface of the semiconductor layer that enters the semiconductor layer and is located in the drift region;

[0018] A buffer layer is formed on the inner wall surface of the groove, and a filling cavity is formed in the groove within the buffer layer; wherein the buffer layer and the semiconductor layer contain the same first element, and the buffer layer also contains at least one second element different from the first element.

[0019] Furthermore, an epitaxial process is adopted to form one or more epitaxial layers of the semiconductor layer on the inner wall surface of the groove, and by adding the second element in the process of forming the epitaxial layer, the one or more buffer layers correspondingly formed by the one or more epitaxial layers contain the same first element as the semiconductor layer, and the buffer layer also contains at least one second element different from the first element.

[0020] Furthermore, when performing the epitaxial process, by adjusting the amount of the second element added, the content of the second element in the buffer layer is adjusted to gradually change or gradiently change in the inward direction along the inner wall of the groove, and / or, when forming multiple layers of the epitaxial layers, by adding at least one different second element to any two adjacent layers, the materials of any two adjacent layers in the formed multiple layers of the buffer layer are different.

[0021] Furthermore, when performing the epitaxial process, the epitaxial layer is doped so that the buffer layer contains doping impurities of a first doping type and / or doping impurities of a second doping type different from the first doping type.

[0022] Furthermore, the method further includes: forming a filling layer of a second doping type different from the first doping type in the cavity by filling the cavity.

[0023] It can be seen from the above technical scheme that the present invention forms one or more epitaxial layers of different components on the inner wall surface of the trench as a material buffer layer before the trench is filled, and utilizes the concentration difference of different components in the buffer layer and the difference in atomic radius to effectively control the material diffusion between the interfaces (boundaries) of different doping types of materials inside and outside the trench, further reducing the characteristic resistance (Ron) of the drift region to provide more precise and stable withstand voltage characteristics. The performance can also be fine-tuned by doping impurities in the buffer layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of a novel structure in a deep trench super junction field effect transistor according to a preferred embodiment of the present invention.

[0025] Figure 2-Figure 5 The figure is a schematic diagram of the process steps of a method for manufacturing a novel structure in a deep trench super junction field effect transistor according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0027] Unless otherwise specified below, the various parts of the MOSFET device can be made of materials known to those skilled in the art. Semiconductor materials may include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate conductor may be formed of various materials that can conduct electricity, such as metal, doped polysilicon layer, or a stacked gate conductor including a metal and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x, Ni3Si, Pt, Ru, W, and combinations of the above-mentioned various conductive materials. The gate dielectric (gate oxide layer) may be made of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Furthermore, the gate dielectric may be formed not only of materials known to those skilled in the art, but also of materials to be developed in the future for use as gate dielectrics.

[0028] The first doping type may be one of N-type and P-type, and the second doping type may be the other of N-type and P-type. N-type may be formed by injecting N-type dopants (e.g., P, As, etc.) into a semiconductor material. P-type may be formed by injecting P-type dopants (e.g., B, etc.) into a semiconductor material. The above may be understood with reference to known techniques.

[0029] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0030] refer to Figure 1 A novel structure in a deep trench super junction field effect transistor (Deep Trench Super Junction MOSFET) of the present invention comprises: a substrate 10, a semiconductor layer 11 disposed on the substrate 10, a trench 15 disposed in the semiconductor layer 11, and a buffer layer 14 disposed on the inner wall surface of the trench 15.

[0031] The semiconductor layer 11 is located on the surface of the substrate 10 ; a drift region 111 of the first doping type is disposed in the semiconductor layer 11 . The trench 15 is usually a deep trench 15 known in the industry; and the trench 15 extends from the surface of the semiconductor layer 11 downward into the semiconductor layer 11 and is located in the drift region 111 .

[0032] The buffer layer 14 is disposed on the inner wall surface of the groove 15, and a filling cavity 16 is formed in the groove 15 within the buffer layer 14 (refer to Figure 3 The cavity 16 is used to be filled with a filling layer 13 of the second doping type.

[0033] The buffer layer 14 and the semiconductor layer 11 both contain the same first element; and the buffer layer 14 further contains at least one second element different from the first element.

[0034] The embodiment of the present invention is described below by taking the case where the first doping type is N-type and the second doping type is P-type as an example.

[0035] refer to Figure 1 In some embodiments, the substrate 10 may be an N+ type silicon substrate 10 (N+SUBSTRATE) of a first doping type.

[0036] The semiconductor layer 11 may be an epitaxial N-type silicon semiconductor layer 11 of a first doping type disposed on the surface of the substrate 10 , and an epitaxial N-type drift region 111 (N-DRIFT REGION) of a first doping type is formed in the semiconductor layer 11 .

[0037] A dielectric layer 12 is also disposed on the surface of the semiconductor layer 11. The groove 15 also extends downward from the surface of the dielectric layer 12 into the semiconductor layer 11. The material of the dielectric layer 12 may be silicon dioxide, but is not limited thereto.

[0038] The filling layer 13 filled in the cavity 16 within the buffer layer 14 may be a P-type filling layer 13. The P-type filling layer 13 may be, for example, a P-type column 131.

[0039] The buffer layer 14 may be continuously distributed along the inner wall surface of the trench 15. The top surface of the P-type filling layer 13 (P-type pillar 131) is flush with the surface of the dielectric layer 12.

[0040] The bottom of the trench 15 may be located in contact with the surface of the substrate 10 or at a certain distance from the surface of the substrate 10 .

[0041] In some embodiments, when the semiconductor layer 11 is an epitaxial silicon semiconductor layer 11, the buffer layer 14 and the semiconductor layer 11 both contain Si as the first element. In addition, the buffer layer 14 further contains at least one of Ge, C, and As as the second element.

[0042] The content (concentration) of the second element in the buffer layer 14 changes gradually or gradiently along the inner wall of the groove 15 toward the inside of the groove 15 . The content of the second element may be the mass fraction of the second element in the buffer layer 14 .

[0043] In some embodiments, the buffer layer 14 may be a single-layer buffer layer 14. Alternatively, the buffer layer 14 may be a plurality of buffer layers 14 stacked one on another, that is, the buffer layer 14 is a multi-layer stacked structure. Furthermore, when the buffer layer 14 is a multi-layer stacked structure, any two adjacent layers in the multi-layer stacked structure (that is, any two adjacent buffer layers 14) are made of different materials.

[0044] For example, the buffer layer 14 includes a single layer formed of any one of SiGe, SiGeC, SiC, SiP, SiAs, and SiAsC. Alternatively, the buffer layer 14 includes a multilayer stack formed of any two or more of SiGe, SiGeC, SiC, SiP, SiAs, and SiAsC.

[0045] When the buffer layer 14 is a single layer, the second element Ge / C / P / As in the buffer layer 14 has a concentration that changes gradually or changes in a gradient (jumps) inwardly along the inner wall of the trench 15 .

[0046] When the buffer layer 14 is a multilayer, the second element Ge / C / P / As in the buffer layer 14 has a concentration that gradually changes along the layers of the stack in the inward direction along the inner wall of the groove 15; or forms a gradient concentration in each layer of the stack; or forms a gradient concentration between the layers of the stack.

[0047] By forming Ge / C / P / As etc. with different concentrations in Si of the buffer layer 14, the buffer layer 14 can be formed into a multilayer structure with different concentration jumps or gradients. In this way, by utilizing the difference between the concentration gradient formed in the buffer layer 14 and the atomic radius, the potential energy of the P-type impurities in the filling layer 13 diffusing out of the trench 15 is changed, so as to limit the material diffusion between the N-type / P-type interface (i.e., the boundary between the N-type drift region 111 and the P-type filling layer 13), and reduce the characteristic resistance (Ron) of the drift region 111, so as to provide a more precise and stable withstand voltage characteristic.

[0048] In some embodiments, the buffer layer 14 contains N-type dopant impurities.

[0049] Alternatively, the buffer layer 14 contains P-type dopant impurities.

[0050] Alternatively, the buffer layer 14 contains both N-type doping impurities and P-type doping impurities.

[0051] The buffer layer 14 has a doping concentration that changes gradually or gradiently (jumps) along the inner wall of the trench 15 toward the inside of the trench 15 .

[0052] For example, when the buffer layer 14 is a single layer, the buffer layer 14 has a doping concentration that changes gradually or gradiently inwardly along the inner wall of the trench 15 (including a region in the buffer layer 14 where the doping concentration is zero).

[0053] When the buffer layer 14 is multi-layer, the buffer layer 14 has a doping concentration that gradually changes along the layers of the stack in the inward direction along the inner wall of the groove 15; or a doping concentration that forms a gradient change in each layer of the stack (including a region in the layer with a doping concentration of 0); or a doping concentration that forms a gradient change between the layers of the stack (including a layer with a doping concentration of 0).

[0054] By doping impurities in the buffer layer 14 using the above-mentioned multiple methods, the doping concentration difference inside and outside the trench 15 can be reduced, and the potential energy of the P-type impurities in the filling layer 13 diffusing out of the trench 15 can be weakened, thereby reducing the amount of P-type impurities in the filling layer 13 diffusing outward and their impact on device performance, thereby achieving a fine-tuning effect.

[0055] A plurality of the deep trenches 15 (including the buffer layer 14 and the P-type filling layer 13 disposed therein) may be disposed in parallel in the semiconductor layer 11 .

[0056] The deep trench super junction field effect transistor may also have conventional device structures such as a body region, a source region, a gate, a gate oxide layer and a lead structure, which can be understood by referring to the prior art and will not be described in detail.

[0057] The novel structure manufacturing method in a deep trench super junction field effect transistor of the present invention is further described in detail below through specific implementation modes and in combination with the accompanying drawings.

[0058] refer to Figure 2-Figure 5 The novel structure manufacturing method of the deep trench super junction field effect transistor of the present invention can be used to manufacture the above-mentioned Figure 1 A novel structure in a deep trench super junction field effect transistor of the present invention may include the following steps:

[0059] Step S1 : providing a substrate 10 , and forming a semiconductor layer 11 on a surface of the substrate 10 to form a drift region 111 .

[0060] like Figure 2 As shown, a heavily doped N+ silicon substrate 10 (N+SUBSTRATE) can be used, and an epitaxial process can be used to form a lightly doped N-type epitaxial silicon semiconductor layer 11 on the silicon substrate 10, and an epitaxial N-type drift region 111 (N-DRIFT REGION) is also formed in the semiconductor layer 11.

[0061] Step S2 : forming a trench 15 on the surface of the semiconductor layer 11 , entering the semiconductor layer 11 and being located in the drift region 111 .

[0062] like Figure 2 As shown, then, a deposition process is used to form, for example, a silicon dioxide dielectric layer 12 on the surface of the semiconductor layer 11 .

[0063] Next, a photolithography and etching process is used to etch downward through the surface of the dielectric layer 12 to form a deep trench 15 that enters the semiconductor layer 11 , and the formed deep trench 15 is located in the drift region 111 .

[0064] Step S3 : forming a buffer layer 14 on the inner wall surface of the trench 15 , and forming a filling cavity 16 in the trench 15 within the buffer layer 14 .

[0065] like Figure 3 As shown, a single or multi-layer buffer layer 14 structure containing Ge / C / As is grown on the inner wall surface of the deep trench 15 by a selective epitaxial process. The buffer layer 14 grows along the inner wall surface of the deep trench 15, thereby forming a filled cavity 16 in the trench 15 within the buffer layer 14.

[0066] For example, a single-layer buffer layer 14 made of SiGe, SiGeC, SiC, SiP, SiAs or SiAsC can be grown on the inner wall surface of the deep trench 15. Alternatively, a multilayer buffer layer 14 made of any two or more of SiGe, SiGeC, SiC, SiP, SiAs and SiAsC can be grown on the inner wall surface of the deep trench 15. In this way, the buffer layer 14 and the semiconductor layer 11 contain the same first element of silicon, and the buffer layer 14 also contains a second element different from the first element of silicon, such as at least one of Ge, C, P and As.

[0067] By adding a second element such as Ge / C / As during the process of forming the epitaxial layer, the one or more buffer layers 14 formed corresponding to the one or more epitaxial layers contain the same silicon first element as the semiconductor layer 11, and the buffer layer 14 also contains a second element different from the silicon first element, such as at least one of Ge, C, P, and As.

[0068] Furthermore, when performing the epitaxial process of this step, the content of the second element in the buffer layer 14 is adjusted by adjusting the addition amount of the second element such as Ge / C / P / As in the epitaxial layer, and the content of the second element in the buffer layer 14 is gradually changed or gradiently changed along the inner wall of the groove 15 toward the inside of the groove 15.

[0069] Furthermore, when forming a multilayer epitaxial layer, at least one different second element is added to any two adjacent layers so that the materials of any two adjacent layers in the formed multilayer buffer layer 14 are different. For example, Ge can be added to the first epitaxial layer closest to the inner wall of the trench 15, and Ge and C (or C, or P, or As, or As and C) can be added to the second epitaxial layer within the first epitaxial layer to form a SiGe first epitaxial layer (first buffer layer 14), and a SiGeC (or SiC, SiP, SiAs, SiAsC) second epitaxial layer (second buffer layer 14), etc., thereby forming a multilayer epitaxial layer (multilayer buffer layer 14) of different materials.

[0070] It can be understood that the inner and outer order of the above-mentioned SiGe layer, SiGeC layer, SiC layer, SiP layer, SiAs layer, and SiAsC layer in the multilayer buffer layer 14 can be changed. Moreover, by adding different combinations between the second elements, a material layer (buffer layer 14) of a gradual or jump state of a single or multiple mixed material of different concentrations or materials, such as SiGe, SiGeC, SiC, SiP, SiAs, SiAsC, etc., arranged in a time sequence of the manufacturing process, can be formed in the buffer layer 14.

[0071] In some embodiments, when performing the epitaxial process of this step, impurities are doped into the epitaxial layer so that the corresponding buffer layer 14 contains N-type doped impurities, or P-type doped impurities, or both N-type and P-type doped impurities.

[0072] Furthermore, by adjusting the doping dose of the impurities, the concentration of the impurities in the buffer layer 14 is adjusted so that the buffer layer 14 has a doping concentration that changes gradually or changes in a gradient (jumps) along the inner wall of the trench 15 toward the inside of the trench 15 .

[0073] Furthermore, when forming a single-layer buffer layer 14, the impurity doping dosage is gradually changed so that the single-layer buffer layer 14 has a doping concentration that gradually changes inward along the inner wall of the groove 15. Alternatively, the impurity doping dosage is changed in an abrupt manner so that the single-layer buffer layer 14 has a doping concentration that changes in a gradient inward along the inner wall of the groove 15 (including a region within the single-layer buffer layer 14 where the doping concentration is 0).

[0074] Furthermore, when forming a multi-layer buffer layer 14, by gradually changing the doping dose of impurities, the multi-layer buffer layer 14 has a doping concentration that gradually changes along the inner wall of the groove 15 inward along each layer of the stack. Alternatively, by changing the doping dose of impurities in an abrupt manner, a doping concentration with a gradient change (including a region in a layer with a doping concentration of 0) is formed in each layer of the stack. Alternatively, by changing the doping dose of impurities in an abrupt manner, a doping concentration with a gradient change (including a layer with a doping concentration of 0) is formed between each layer of the stack.

[0075] Step S4 : forming a filling layer 13 in the cavity 16 .

[0076] like Figure 4 As shown, the cavity 16 is filled by using a conventional P-type column filling process, a P-type filling layer 13 is grown in the cavity 16 of the deep trench 15 within the buffer layer 14 , and the deep trench 15 is filled.

[0077] like Figure 5 As shown, finally, a planarization process, such as a chemical mechanical polishing process, is used to remove excess P-type filling layer 13 material on the surface of the dielectric layer 12 that overflows the deep trench 15, to form a P-type column 131 in the trench 15, and to make the top surface of the formed P-type column 131 flush with the surface of the dielectric layer 12.

[0078] In addition, the device structures such as the body region, source region, gate, gate oxide layer and lead-out structure conventionally found in deep trench super junction field effect transistors can be further manufactured, which can be understood by referring to the prior art and will not be described in detail.

[0079] In summary, the present invention forms one or more epitaxial layers of different components on the inner wall surface of the deep trench 15 as the material buffer layer 14 before the deep trench 15 is filled, and utilizes the concentration difference of different components and the difference of atomic radius in the buffer layer 14 to effectively control the material diffusion between the interface (boundary) of different doping types of materials inside and outside the deep trench 15, further reducing the characteristic resistance (Ron) of the drift region 111, so as to provide more precise and stable withstand voltage characteristics. The performance can be further fine-tuned by doping impurities in the buffer layer 14.

[0080] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A novel structure in a deep trench superjunction field effect transistor, characterized in that: include: A semiconductor layer disposed on the substrate, wherein a drift region of a first doping type is disposed in the semiconductor layer; A trench extending from a surface of the semiconductor layer into the semiconductor layer and located in the drift region; a buffer layer disposed on the inner wall surface of the groove, wherein a filling cavity is formed in the groove within the buffer layer; The buffer layer and the semiconductor layer contain the same first element, and the buffer layer further contains at least one second element different from the first element.

2. The novel structure in the deep trench super junction field effect transistor according to claim 1, characterized in that: The first element includes Si, the second element includes at least one of Ge, C, P, and As, and / or the content of the second element in the buffer layer changes gradually or gradiently in an inward direction along the inner wall of the groove.

3. The novel structure in the deep trench super junction field effect transistor according to claim 1, characterized in that: The buffer layer is a single layer or a multilayer stack, and the materials of any two adjacent layers in the multilayer stack are different; or, the buffer layer includes a single layer formed by one of SiGe, SiGeC, SiC, SiP, SiAs, and SiAsC, or a multilayer stack formed by two or more of them.

4. The novel structure in the deep trench super junction field effect transistor according to claim 1, characterized in that: The buffer layer contains doping impurities of a first doping type and / or doping impurities of a second doping type different from the first doping type.

5. The novel structure in the deep trench super junction field effect transistor according to claim 1, characterized in that: Also includes: A filling layer of a second doping type different from the first doping type is disposed in the cavity.

6. A novel structure manufacturing method in a deep trench super junction field effect transistor, characterized in that: include: Providing a substrate, and forming a semiconductor layer of a first doping type on a surface of the substrate to form a drift region; forming a trench on a surface of the semiconductor layer that enters the semiconductor layer and is located in the drift region; A buffer layer is formed on the inner wall surface of the groove, and a filling cavity is formed in the groove within the buffer layer; wherein the buffer layer and the semiconductor layer contain the same first element, and the buffer layer also contains at least one second element different from the first element.

7. The novel structure manufacturing method in deep trench super junction field effect transistor according to claim 6, characterized in that: An epitaxial process is adopted to form one or more epitaxial layers of the semiconductor layer on the inner wall surface of the groove, and by adding the second element in the process of forming the epitaxial layer, the one or more buffer layers correspondingly formed by the one or more epitaxial layers contain the same first element as the semiconductor layer, and the buffer layer also contains at least one second element different from the first element.

8. The method for manufacturing a novel structure in a deep trench super junction field effect transistor according to claim 7, characterized in that: When performing the epitaxial process, by adjusting the amount of the second element added, the content of the second element in the buffer layer is adjusted to gradually change or gradiently change in the inward direction along the inner wall of the groove, and / or, when forming multiple layers of the epitaxial layer, by adding at least one different second element to any two adjacent layers, the materials of any two adjacent layers in the formed multiple layers of the buffer layer are different.

9. The method for manufacturing a novel structure in a deep trench super junction field effect transistor according to claim 7, characterized in that: During the epitaxial process, the epitaxial layer is doped so that the buffer layer contains doping impurities of a first doping type and / or doping impurities of a second doping type different from the first doping type.

10. The method for manufacturing a novel structure in a deep trench super junction field effect transistor according to claim 6, characterized in that: Also includes: By filling the cavity, a filling layer of a second doping type different from the first doping type is formed in the cavity.

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