CMOS device for high voltage applications

Abstract

The invention relates to a CMOS device for high voltage applications. An integrated device includes a conductive substrate having an upper surface including a recess and a lower surface for contacting the device; a multilayer stack disposed on an upper surface of the substrate and backing the recess; and a conductive layer for contacting a device disposed on the multilayer stack. The multilayer stack includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer. The immediately adjacent dielectric layers have different band gaps to trap charge carriers at respective interfaces between the dielectric layers during operation of the device.

Description

Technical Field

[0001] The present disclosure relates to complementary metal oxide semiconductor (CMOS) devices, such as RC snubber devices. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) capacitors have a wide range of applications. For example, CMOS capacitors can be connected in series with resistor sections to form "RC snubber" devices, i.e., resistor-capacitor snubber devices (e.g., for integration into power modules). In this case, the device typically includes a trench structure to increase the effective surface area of ​​the electrode, thereby increasing the capacitance per unit area. However, the patterned electrodes typically have sharp corners, which result in higher electric field strengths near the corners, which in turn limits the operating voltage of the capacitor and the operating voltage of the RC snubber device.

[0003] To further illustrate this point, refer to Figures 1A to 1C A conventional CMOS RC snubber device is described (a similar device is also described in US7738226 B2). The device has a lower metal layer P14 in contact with a doped silicon substrate P10, which determines the resistance part of the device. The substrate P10 includes a large number of deep trenches P11 etched into the upper surface of the substrate. The trench walls are coated with an insulating layer P12, which determines the capacitance part of the device. The trench is filled with a conductive material, which forms an upper electrode P13. A portion of the upper electrode protrudes into the trench P11. Thus, as Figure 1B (It shows Figure 1A As further shown in the enlarged area P17 of FIG. 1 , the substrate P10 has a sharp corner P15 at the upper surface, and the upper electrode P13 has a sharp corner P16 at the lower end of the portion protruding into the groove. As described above, such a sharp corner causes a high electric field during use of the device. Figure 1C The variation of the electric field strength inside the insulating layer P12 along the indicated paths A-A' and BB' when a voltage is applied between the metal layer P14 and the upper electrode P13 is shown in curves P17 and P18, respectively. The electric field strength is highest near the corners P15 and P16 and decreases as the distance from the corners increases. In this example, the electric field strength near the corners is greater than the critical field strength E of the device. c This means that the electric field enhancement caused by the sharp corner may lead to electrical breakdown of the insulating layer P12, thereby damaging the device. Summary of the invention

[0004] One problem with conventional complementary metal oxide semiconductor (CMOS) devices including trench capacitors is that the patterned electrodes have sharp corners, which limit the operating voltage of the device (due to the electric field enhancement effect near the sharp corners). This means that these devices are not suitable for high voltage applications. For example, a conventional CMOS RC snubber device with an integrated trench capacitor may not be suitable for use in a high voltage (e.g., 800V) integrated power module. In order to at least partially address this problem, the present invention provides an improved CMOS device and an improved integrated power module such as set forth in the appended claims.

[0005] In general, the purpose of the present invention is to provide new and useful CMOS devices (e.g., capacitors, RC buffer devices, etc.). In general, embodiments of the present invention can realize, for example, CMOS devices having a higher breakdown voltage than conventional devices. Embodiments can realize the CMOS device by providing a conductive substrate including one or more grooves (e.g., pits and / or trenches), a multilayer stack (e.g., a stack of dielectric layers) disposed on the substrate and lining one or more grooves, and a conductive layer disposed on the multilayer stack. The multilayer stack may include at least four dielectric layers, and may be configured to capture charge carriers at corresponding interfaces between dielectric layers during operation of the device. The trapped charges can form "effective and rounded electrodes" that reduce the electric field strength near the sharp corners of the electrodes. Therefore, compared to conventional designs using a single dielectric layer between electrodes, embodiments can exhibit reduced peak electric field strengths between electrodes. Therefore, embodiments of the present invention can operate at higher voltages than conventional devices and are particularly suitable for high voltage applications such as high voltage integrated power modules. Embodiments of the present invention can be manufactured using conventional CMOS processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which:

[0007] Figure 1A It is a schematic diagram of a conventional RC snubber device;

[0008] Figure 1B yes Figure 1A Close-up of part P17 of a conventional RC snubber device;

[0009] Figure 1C Two graphs illustrating the electric field strength are shown;

[0010] Figure 2 is a schematic diagram of a semiconductor device according to an embodiment;

[0011] Figure 3A yes Figure 2 a band diagram of a multilayer stack included in a device;

[0012] Figure 3B shows that when an external voltage is applied Figure 3A ; and

[0013] Figure 4 It shows Figure 2 A graph of the electric field strength within a multilayer stack included in a device.

[0014] To avoid unnecessary repetition, like reference numerals in the drawings will be used to denote like features. DETAILED DESCRIPTION

[0015] According to a first embodiment, an integrated device (hereinafter, also referred to as a "complementary metal oxide semiconductor (CMOS) device") (e.g., a capacitor or an RC snubber device) is provided, comprising: a conductive substrate having an upper surface including a recess (e.g., a groove or a pit) and a lower surface for contacting the device; a multilayer stack disposed on the upper surface of the substrate and lining the recess; and a conductive layer for contacting the device disposed on the multilayer stack. The multilayer stack comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer. The adjacent dielectric layers have different band gaps to capture charge carriers at corresponding interfaces between the dielectric layers during operation of the device.

[0016] By trapping charge at the interface between the dielectric layers, an "effective electrode" is formed that mitigates any electric field enhancement caused by sharp corners or edges of the recesses or conductive layers disposed on the multilayer stack. This enables CMOS devices with higher breakdown voltages that can be fabricated using conventional methods (i.e., the recesses and conductive layers disposed on the multilayer stack can be formed in conventional ways that would result in sharp corners or edges).

[0017] The conductive substrate may be a semiconductor substrate including a doped region extending from a lower surface of the substrate to an upper surface of the substrate, and may have a predetermined conductivity. In some embodiments, the conductive substrate may be a semiconductor substrate doped to have a predetermined conductivity.

[0018] Each dielectric layer may have a corresponding band gap. The first dielectric layer may be disposed on the upper surface of the substrate. The second dielectric layer may be disposed on the first dielectric layer. The third dielectric layer may be disposed on the second dielectric layer. The fourth dielectric layer may be disposed on the third dielectric layer. The band gaps of adjacent dielectric layers may be different. In this case, the first dielectric layer and the third dielectric layer may include a first dielectric material, and the second dielectric layer and the fourth dielectric layer may include a second dielectric material.

[0019] The first dielectric material may include an oxide (eg, silicon oxide). For example, the first dielectric layer may be a thermally grown silicon oxide layer.

[0020] The second dielectric material may include silicon nitride.

[0021] The first dielectric layer and the second dielectric layer may have the same thickness. The third dielectric layer and the fourth dielectric layer may have the same thickness. The first dielectric layer and the second dielectric layer may have a first thickness, and the third dielectric layer and the fourth dielectric layer may have a second thickness different from the first thickness.

[0022] The second thickness may be greater than the first thickness. The second thickness may be twice the first thickness.

[0023] The breakdown voltage of the device may be equal to or greater than 800V, preferably equal to or greater than 1200V.

[0024] The upper surface of the conductive substrate may include a plurality of recesses, and the multilayer stack may line each recess.

[0025] The multilayer stack may include further dielectric layers.

[0026] The thickness of the multilayer stack may be equal to or greater than 1 μm. The thickness of each dielectric layer of the multilayer stack may be equal to or greater than 100 nm.

[0027] The device can be manufactured using (conventional) CMOS processing techniques.

[0028] In some embodiments, the integrated device includes a polar capacitor including a conductive substrate, a multilayer stack, and a conductive layer. In some embodiments, the integrated device can be an integrated buffer circuit and can also include an electrode disposed on a lower surface of the substrate. The electrode and the substrate can together form a resistive portion of the buffer circuit (electrically connected in series with the capacitor).

[0029] According to a second embodiment, there is provided an integrated power module comprising the CMOS device of the first aspect and a transistor for controlling current through a load, the transistor being connected in parallel with the CMOS device.

[0030] In a broad sense, a high voltage integrated circuit (or "integrated device") is proposed that can be formed using a standard complementary metal oxide semiconductor (CMOS) manufacturing process (hence, hereinafter, the integrated circuit is referred to as a CMOS device or a CMOS component). The proposed CMOS device may include a (trench) capacitor portion. In the proposed CMOS device, a stack of dielectric layers (hereinafter, referred to as a "multilayer stack") is provided between electrodes of the (trench) capacitor portion. As described below with reference to Figures 2 to 4 As described in detail, the purpose of the multilayer stack is to increase the breakdown voltage of the capacitor portion by trapping charges at the interfaces of the dielectric layers.

[0031] Figure 2A schematic cross-section of a CMOS device 1 according to an embodiment is shown. In general, the CMOS device 1 includes a capacitor portion electrically connected in series with a resistor portion to form an "RC snubber" device. More specifically, the device 1 may include a first (or lower) electrode 3 and a second (or upper) electrode 5 for contacting the device 1. The lower electrode 3 and the upper electrode 5 may each include a metal layer. The lower electrode 3 may be an anode of the CMOS device 1, and the upper electrode 5 may be a cathode of the CMOS device 1. In other words, the CMOS device 1 may operate with a fixed polarity, i.e., during operation of the CMOS device 1, the potential applied to the lower electrode 3 may be equal to or greater than the potential applied to the upper electrode 5. For example, the upper electrode 5 may be electrically connected to ground.

[0032] The lower electrode 3 may be disposed on the lower surface of the conductive substrate 7. The substrate 7 may be a doped semiconductor substrate (e.g., silicon). For example, the substrate 7 may be a semiconductor substrate doped so that the substrate 7 has a predetermined conductivity (i.e., doped with appropriately selected doping polarity, doping concentration, etc.).

[0033] The substrate 7 has an upper surface 9 including at least one groove 11. Figure 2 Only one groove 11 is shown in the figure, but it should be understood that the substrate 7 generally includes a plurality of (substantially identical) grooves. In general, the depression 11 can extend from the upper surface 9 in a vertically downward direction. The groove 11 can have a sidewall 13 and a bottom surface 15. The sidewall 13 of the groove 11 can form a sharp corner 17 (or sharp edge) with a portion of the upper surface 9 of the substrate 7. For example, the upper portion of the sidewall 13 can be in direct contact with a (substantially) orthogonal portion of the upper surface 9.

[0034] The groove 11 may have any suitable shape, for example the groove 11 may have a groove or a cylindrical shape. Figure 2 As shown, the groove 11 can be deep and narrow, that is, the groove 11 can have a high aspect ratio (for example, a ratio of depth to width greater than 10 or greater than 20). The width of the groove 11 can be equal to or greater than 0.5 μm. For example, the width of the groove 11 can be in a range between 0.5 μm and 20 μm. In either case, the width of the groove 11 can be greater than twice the thickness of the multilayer stack 19 described below. The depth of the groove 11 can be equal to or greater than 5 μm. For example, the depth of the groove 11 can be in a range between 5 μm and 200 μm. Any known suitable method (for example, reactive ion etching) can be used to form the groove 11.

[0035] The multilayer stack 19 is disposed on the upper surface 9 of the substrate 7. Specifically, the multilayer stack 19 may line the groove 11, i.e., the first surface of the multilayer stack 19 may be in contact with the sidewalls 13 and the bottom surface of the groove 11. The multilayer stack 19 may include four dielectric layers that will be described in detail below. Typically, on the sidewalls 13 of the groove 11, the multilayer stack 19 may have a (total) layer thickness equal to or greater than 1 μm. For example, the layer thickness of the multilayer stack 19 on the sidewalls 13 may be in the range between 1 μm and 3 μm. In an embodiment, the multilayer stack 19 may have a substantially uniform thickness (e.g., Figure 2 In other embodiments, the thickness of the multilayer stack 19 may be non-uniform, for example, due to the manufacturing process, the layer thickness of the multilayer stack 19 on the (vertical) side wall 13 may be different from (for example, smaller than) the layer thickness of the multilayer stack 19 on the horizontal portion of the upper surface 9.

[0036] The upper electrode 5 is disposed on the multilayer stack 19, that is, the second surface of the multilayer stack 19 may be in contact with the upper electrode 5. Figure 2 As shown, the upper electrode 5 can cover the multilayer stack 19 and fill the groove 11. Therefore, the upper electrode 5 can include a portion 21, which extends into the groove. At the lower end of the portion 21, the electrode can include a sharp corner 23 (or a sharp edge). Therefore, both the substrate 7 and the upper electrode 5 can include sharp corners 17 and 23. As described below, the problematic electric field peaks associated with these sharp corners 17, 23 can be mitigated by the multilayer stack 19.

[0037] The multilayer stack 19 includes a first dielectric layer 25 1 , the second dielectric layer 25 2 , the third dielectric layer 25 3 and the fourth dielectric layer 25 4 .like Figure 2 As shown, the first dielectric layer 25 1 The second dielectric layer 25 may be disposed on the upper surface of the substrate 9 (ie, may be in contact with the upper surface). 2 It can be arranged on the first dielectric layer 25 1 on (ie, may be connected to the first dielectric layer 25 1 The third dielectric layer 25 3 The second dielectric layer 25 may be provided 2 on (ie, may be connected to the second dielectric layer 25 2 contact). Fourth dielectric layer 25 4 The third dielectric layer 25 may be provided 3 (ie, may be connected to the third dielectric layer 25 3 The upper electrode 5 may be disposed on the fourth dielectric layer 25 4 (ie, may be connected to the fourth dielectric layer 25 4 touch).

[0038] Generally speaking, the dielectric layer 25 1 Up to 25 4 is configured to trap charge carriers at respective interfaces between dielectric layers during operation of the device, as described below with reference to Figure 3A and Figure 3B This can be achieved by appropriately selecting the dielectric layer 25 1 Up to 25 4 More specifically, the dielectric layer 25 1 Up to 25 4 Each of them has a corresponding band gap (usually greater than 2 eV), and the dielectric layer 25 is selected 1 Up to 25 4 The band gap of the adjacent dielectric layer is different (for example, the first dielectric layer 25 1 The second dielectric layer 25 may have 2 Different band gap, the second dielectric layer 25 2 The third dielectric layer 25 may have 3 To this end, the immediately adjacent dielectric layer may be formed of a different material (silicon oxide, silicon nitride, or any other suitable CMOS compatible dielectric material).

[0039] In broad terms, the trapping of charge carriers at the interface of dielectric layers (with different band gaps) can occur for a number of reasons. For example, it is known that charge carriers can be (temporarily) trapped at the interface of dielectric layers due to a change in the band gap at the interface when a dielectric layer is placed between two electrodes and an external voltage is applied. It is known that the trapping of charge carriers can occur due to the (inevitable) appearance of (lattice) defects at the boundary between two different dielectric materials.

[0040] exist Figure 2 In the embodiment of the present invention, the first dielectric layer 25 1 and the third dielectric layer 5 3 The first dielectric material comprises a first dielectric material, and the second dielectric layer and the fourth dielectric layer comprise a second dielectric material. Using (only) two dielectric materials to form the layers of the multilayer stack 19 may result in a simpler manufacturing process for the device 1. However, it should be understood that in other embodiments, more than two dielectric materials may be used to form the multilayer stack 19 (e.g., the dielectric layer 25 1 Up to 25 4 Each of which may include a different dielectric material).

[0041] More specifically, in Figure 2 In the embodiment of the present invention, the first dielectric material may include an oxide (eg, silicon oxide), that is, the first dielectric layer 25 1 and the third dielectric layer 253 For example, the first dielectric layer 25 may include an oxide. 1 The third dielectric layer 25 may include a thermal oxide formed by thermal oxidation of the substrate 7, and the oxide 3 The first dielectric layer 25 may be formed by any suitable and known deposition process (eg, chemical vapor deposition (CVD)). 1 Including a thermal oxide may be advantageous because the thermal oxide may consume substrate material during a corresponding production process, thereby reducing damage (eg, damage resulting from a previous production process such as plasma etching) and may smooth surface roughness of the recess 11 .

[0042] In addition, the second dielectric material may include silicon nitride, that is, the second dielectric layer 25 2 and the fourth dielectric layer 25 4 May include silicon nitride.

[0043] Generally speaking, the dielectric layer 25 1 Up to 25 4 The interface between the groove 11 and the groove 11 may include a rounded corner, specifically, a rounded corner 27 near the top of the groove 11. 1 , 27 2 , 27 3 (ie, the sharp corner 17 of the covering substrate 7) and the rounded corner 29 near the bottom end of the groove 11 1 , 29 2、 29 3 (ie, covering the sharp corner 23 of the upper electrode 5). In this case, due to the working device of the device 1, the dielectric layer 25 1 Up to 25 4 The charge carriers are trapped at the interface between Figure 3A As described above), and these interfaces include rounded corners covering the sharp corners of the substrate 7 and the upper electrode 5, so the electric field peak near the sharp corners can be greatly reduced and the breakdown voltage of the device can be improved.

[0044] Rounded corners 27 1、 27 2、 27 3、 29 1、 29 2、 29 3 The radius of curvature of can be determined by the layer thickness of the dielectric layer below the corresponding interface. 1 and the second dielectric layer 25 2 The rounded corners of the interface between 1 The radius of curvature may be determined by the first dielectric layer 25 1 As another example, the second dielectric layer 25 2and the third dielectric layer 25 3 The rounded corners of the interface between 2 The radius of curvature of the first dielectric layer 25 may be 1 and the second dielectric layer 25 2 As another example, the third dielectric layer 25 3 and the fourth dielectric layer 25 4 The rounded corners of the interface between 3 The radius of curvature of the first dielectric layer 25 may be 1、 The second dielectric layer 25 2 and the third dielectric layer 25 3 The thickness of the layer is determined by

[0045] The first dielectric layer 25 1 and the second dielectric layer 25 2 can have (substantially) the same thickness. In addition, the third dielectric layer 25 3 and the fourth dielectric layer 25 4 have (substantially) the same thickness, which may be different from (eg, greater than) the first dielectric layer 25. 1 and the second dielectric layer 25 2 More specifically, Figure 2 In the embodiment of the present invention, the third dielectric layer 25 3 and the fourth dielectric layer 25 4 The first dielectric layer 25 may be 1 and the second dielectric layer 25 2 In other words, Figure 2 In the embodiment of the present invention, the first dielectric layer 25 1 and the second dielectric layer 25 2 is about 1 / 6 of the total thickness of the multilayer stack 19, and the third dielectric layer 25 3 and the fourth dielectric layer 25 4 The thickness of each of the first dielectric layer 25 is about 1 / 3 of the total thickness of the multilayer stack 19. However, it will be apparent to those skilled in the art that this is not a strict requirement. 1 To the fourth dielectric layer 25 4 Each of the above may be different. In any case, the dielectric layer 25 of the multilayer stack 19 1 Up to 25 4 The thickness of each of may be equal to or greater than 100 nm.

[0046] refer to Figure 3A and Figure 3B The trapping of charge carriers during operation of the device 1 is described. Figure 3AThe band diagram of the valence band 31 and the conduction band 33 along the cross section between the substrate 7 and the upper electrode 5 is shown (when no voltage is applied between the lower electrode 3 and the upper electrode 5). Reference numerals 35, 37, 39, 41, 43 and 45 respectively indicate the substrate 7, the first dielectric layer 25 1 To the fourth dielectric layer 25 4 And the valence band and conduction band of the upper electrode 5. Figure 3A As shown, the dielectric layer 25 1 Up to 25 4 Significantly larger than the band gap of the substrate 7 and the upper electrode 5. Figure 3A As further shown, the band gap of the oxide layer is greater than the band gap of the nitride layer (eg, thermal silicon oxide may have a band gap between 8 eV and 11 eV, and silicon nitride may have a band gap between 4 eV and 6 eV).

[0047] Figure 3B shows when a positive voltage is applied to the lower electrode 3 and the upper electrode 5 is grounded (i.e., during operation of the device 1). Figure 3A With diagram. Figure 3B The first dielectric layer and the second dielectric layer 25 are shown 1、 25 2 Positive charge carriers 47 (indicated by the "+" sign) are trapped at the interface of the first dielectric layer 25. These charges can be trapped in the state between the valence band 31 and the conduction band 33 caused by the crystal defects at the interface. 1 and the second dielectric layer 25 2 The interface of the second dielectric layer 25 is closer to the substrate 7 (anode) than the upper electrode 5 (cathode), so the charge carriers 47 can be mainly positive charge carriers. 2 and the third dielectric layer 25 3 The interface of the third dielectric layer 25 captures positive charge carriers 49 in a state between the valence band 31 and the conduction band 33. 3 The second dielectric layer 25 2 A large band gap (particularly, near the interface, the third dielectric layer 25 3 The valence band of the second dielectric layer is lower than 25 2 The discontinuity of the valence band forms a potential barrier for positive charges. Therefore, in the second dielectric layer 25 2 and the third dielectric layer 25 3 Additional positive charge carriers 51 are trapped at the interface.

[0048] In addition, in the third dielectric layer 25 3 and the fourth dielectric layer 25 4 The interface of the third dielectric layer 25 is between the valence band 31 and the conduction band 33, and the negative charge carriers 53 (indicated by the "-" sign) are trapped. 3and the fourth dielectric layer 25 4 The upper electrode 5 (cathode) is closer than the substrate 7 (anode), so the charge carriers 53 can be mainly negative charge carriers. In addition, since the fourth dielectric layer 25 4 The third dielectric layer 25 has 2 Small band gap (particularly, near the interface, the fourth dielectric layer 25 4 The conduction band of the third dielectric layer is 25 3 The conduction band discontinuity forms a potential barrier for negative charge carriers. Therefore, in the third dielectric layer 25 3 and the fourth dielectric layer 25 4 Additional negative charge carriers 55 are captured at the interface.

[0049] Broadly speaking, the dielectric layer 25 1 Up to 25 4 The charges 47, 49, 51, 53, 55 trapped at the interface of the dielectric layer 25 reduce the sharp corners (specifically, 1 Up to 25 4 The interface includes a strong peak electric field generated by the rounded corners (as described above). Therefore, in simple terms, it can be considered that the dielectric layer 25 1 Up to 25 4 An "effective" rounded electrode is formed, which mitigates the field enhancement effect of the sharp corners of the substrate 7 and the upper electrode 5. Therefore, since the radius of curvature of the interface is determined by the dielectric layer 25 1 Up to 25 4 The thickness of the dielectric layer can be determined by 1 Up to 25 4 layer thickness to optimize the radius of the “effective” electrode while avoiding, for example, dielectric layers 25 1 Up to 25 4 harmful tunneling effect between them.

[0050] Figure 4 Shown along Figure 2 The electric field curve 57 of the "C-C'" section and the electric field curve along Figure 1B 59 is a graph of the electric field of the “A-A′” section of a conventional RC snubber. Figure 4 It is shown that the peak electric field of the proposed device is reduced (due to charge trapping as described above). Figure 1A Curve 57 is not based on a computational simulation of the device 1 described above (such a simulation is believed to result in a more complex but substantially equivalent electric field distribution), but is provided to facilitate understanding of the effect of the multilayer stack 19 described above.

[0051] although Figure 2The embodiments include a multilayer stack including four dielectric layers, but it will be apparent to one skilled in the art that the embodiments may include more than four dielectric layers.

[0052] Although Figure 2 The embodiment is an RC snubber device, but it will be apparent to a person skilled in the art that embodiments include other CMOS devices that can employ the described multilayer stack to increase the breakdown (and operating) voltage of the corresponding device. For example, the described multilayer stack can be used in a (high voltage) CMOS capacitor. In this case, the substrate 7 may not be a semiconductor substrate, but a metal, for example. As another example, the described multilayer stack can be used as an effective gate dielectric (i.e., as an effective dielectric between the gate and the substrate of a field effect transistor). In this case, the size of the device can be smaller, for example the depth of the groove can be only about 0.5 μm.

[0053] Although specific embodiments of the present invention have been described above, it should be understood that the present invention may be practiced in a manner different from that described. The above description is intended to be illustrative rather than limiting. It will be apparent to those skilled in the art that the present invention may be modified without departing from the scope of the appended claims.

[0054] Each feature disclosed or shown in this specification may be included in the invention either alone or in any appropriate combination with any other features disclosed or shown herein.

Claims

1. An integrated device comprising: a conductive substrate having an upper surface and a lower surface, the upper surface including a groove; a multi-layer stack disposed on the upper surface of the substrate and lining the groove; as well as a conductive layer disposed on the multilayer stack; The multilayer stack comprises a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer, and adjacent dielectric layers have different band gaps to capture charge carriers at corresponding interfaces between the dielectric layers during operation of the device.

2. The integrated device according to claim 1, wherein: The conductive substrate is a semiconductor substrate including a doping region extending from a lower surface of the substrate to an upper surface of the substrate, and wherein the substrate has a predetermined conductivity.

3. The integrated device according to claim 1, wherein: The first dielectric layer is disposed on the upper surface of the substrate, The second dielectric layer is disposed on the first dielectric layer, The third dielectric layer is disposed on the second dielectric layer, The fourth dielectric layer is disposed on the third dielectric layer, and The first dielectric layer and the third dielectric layer include a first dielectric material, and the second dielectric layer and the fourth dielectric layer include a second dielectric material.

4. The integrated device according to claim 3, wherein: The first dielectric material includes an oxide.

5. The integrated device according to claim 4, wherein: The oxide is silicon oxide.

6. The integrated device according to claim 1, wherein: The first dielectric layer is a thermally grown silicon oxide layer.

7. The integrated device according to claim 1, wherein: The second dielectric material includes silicon nitride.

8. The integrated device according to claim 1, wherein: The first dielectric layer and the second dielectric layer have the same thickness.

9. The integrated device according to claim 1, wherein: The third dielectric layer and the fourth dielectric layer have the same thickness.

10. The integrated device according to claim 1, wherein: The first dielectric layer and the second dielectric layer have a first thickness, and the third dielectric layer and the fourth dielectric layer have a second thickness different from the first thickness.

11. The integrated device according to claim 10, wherein: The second thickness is greater than the first thickness.

12. The integrated device according to claim 11, wherein: The second thickness is twice the first thickness.

13. The integrated device according to claim 1, wherein: The breakdown voltage of the device is equal to or greater than 800V, or equal to or greater than 1200V.

14. The integrated device according to claim 1, wherein: The recess is a groove or has a cylindrical shape.

15. The integrated device according to claim 1, wherein: The upper surface of the conductive substrate includes a plurality of recesses, and the multilayer stack lines each of the recesses.

16. The integrated device according to claim 1, wherein: The multilayer stack comprises further dielectric layers.

17. The integrated device according to claim 1, wherein: The thickness of the multilayer stack is equal to or greater than 1 μm.

18. The integrated device according to claim 1, wherein: The thickness of each dielectric layer of the multilayer stack is equal to or greater than 100 nm.

19. The integrated device according to claim 1, wherein: The device can be fabricated using complementary metal oxide semiconductor (CMOS) processing technology.

20. The integrated device according to claim 1, wherein: The integrated device includes a polar capacitor including a conductive substrate, a multilayer stack, and the conductive layer.

21. The integrated device according to claim 20, wherein: The integrated device is an integrated buffer circuit and further includes an electrode disposed on a lower surface of the substrate, wherein the electrode and the substrate together form a resistive portion of the buffer circuit.

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