Preparation method of laminated cell with resistance-increasing bulge structure

Abstract

The invention provides a preparation method of a laminated cell with a resistance-increasing bulge structure. The preparation method comprises the following steps: forming a tunnel junction on one surface of a heterogeneous crystalline silicon cell; preparing a conductive layer on the surface, far away from the heterogeneous crystalline silicon cell, of the tunnel junction; the surface, away from the tunnel junction, of the conductive layer is coated with a first carrier transmission layer; the surface, away from the conductive layer, of the first carrier transmission layer is coated with a resistance increasing layer; coating a perovskite light absorption layer on the surface, far away from the first carrier transmission, of the resistance increasing layer; preparing a second carrier transport layer on one surface, far away from the resistance increasing layer, of the perovskite light absorption layer; forming a transparent electrode layer on one surface, far away from the perovskite light absorption layer, of the second carrier transport layer; wherein the step of preparing the resistance increasing layer also comprises the step of preparing a suede with nanoscale bulges. According to the invention, the resistance increasing layer is provided with the nano-scale dispersed nanoparticles, so that the problem of cell short circuit caused by non-uniformity and exposure of the perovskite light absorption layer during deposition of the perovskite light absorption layer is solved.

Description

Technical Field

[0001] The present application relates to the field of battery technology, and in particular to a method for preparing a laminated battery with a resistance-increasing protrusion structure. Background Art

[0002] Monocrystalline silicon solar cells occupy the vast majority of the photovoltaic market due to their high conversion efficiency and low cost. At present, the world's highest conversion efficiency of monocrystalline silicon solar cells is 26.81%, created by LONGi's heterojunction technology, which is very close to the theoretical efficiency of 29.4%. An effective way to break through the theoretical limit is to develop tandem cell technology, that is, stacking absorption layers with different band gaps together to reduce heat loss. Simulations and calculations show that tandem cells at both ends of the surface can achieve a theoretical efficiency of 43%. Perovskite has become an excellent top cell material in tandem cells because of its easy processing, low cost, and easy band gap adjustment. Recently, the Berlin Helmholtz Center (HZB) created a conversion efficiency of 32.5%.

[0003] In the process of preparing perovskite / crystalline silicon tandem solar cells, it is necessary to deposit a contoured perovskite film on the pyramid velvet silicon dioxide tunneling layer to ensure that the perovskite / crystalline silicon tandem cell has a high light trapping structure to obtain higher photoelectric conversion efficiency. However, the surface texture structure of heterogeneous crystalline silicon cells makes it difficult to deposit a perovskite film of uniform thickness, which will lead to a short circuit in the final cell. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the purpose of the present application is to propose a method for preparing a stacked cell with a resistance-enhancing protrusion structure, which solves the problem of cell short circuit caused by uneven and exposed perovskite light absorption layer during the deposition of perovskite light absorption layer by using dispersed nanoparticles of nanometer scale on the resistance-enhancing layer, thereby improving the photoelectric conversion efficiency of the stacked cell.

[0005] According to an embodiment of the present application, a method for preparing a stacked battery having a resistance-increasing protrusion structure is proposed, comprising the following steps:

[0006] Forming a tunnel junction on one surface of a heterogeneous crystalline silicon cell;

[0007] Prepare a conductive layer on the surface of the tunnel junction away from the heterogeneous crystalline silicon cell;

[0008] Coating a first carrier transport layer on a surface of the conductive layer away from the tunnel junction;

[0009] Coating a resistance-enhancing layer on a surface of the first carrier transport layer away from the conductive layer;

[0010] Coating a perovskite light absorption layer on a surface of the resistance increasing layer away from the first carrier transmission;

[0011] Prepare a second carrier transport layer on a side of the perovskite light absorption layer away from the resistance increasing layer;

[0012] forming a transparent electrode layer on a side of the second carrier transport layer away from the perovskite light absorption layer;

[0013] The preparation of the resistance-enhancing layer also includes preparing a suede surface with nanoscale protrusions.

[0014] In some embodiments, the method for preparing the resistance-enhancing layer comprises:

[0015] Preparing a suspension containing nano suspended particles; and spraying the suspension onto a side of the first carrier transport layer away from the conductive layer to obtain a nano coating;

[0016] The resistance-enhancing layer obtained by drying and curing the nano coating has a velvety surface with nano-scale protrusions.

[0017] In some embodiments, the method of drying the nanocoating is heating or vacuuming.

[0018] In some embodiments, the nano coating is cured at 200-500° C. for 100-200 min.

[0019] In some embodiments, the ratio of the volume of the nano-suspended particles to the total volume of the suspension is 1 / 800-1 / 500.

[0020] In some embodiments, the particle size of the dispersed nanoparticles in the resistance-enhancing layer is 10-300 nm.

[0021] In some embodiments, the dispersed nanoparticles in the resistance-enhancing layer are randomly and evenly distributed with a spacing of 20-200 nm.

[0022] In some embodiments, the perovskite light absorbing layer covers the resistance increasing layer.

[0023] In some embodiments, the first carrier transport layer has a thickness of 20-120 nm and is selected from one of TiO2, SnO2, ZnO or one of PEDOT, PEDOT:PSS, P3HT, P3OHT, P3ODDT, PTAA, and NiO.

[0024] In some embodiments, the stacked cell further includes metal electrodes respectively disposed on the heterogeneous crystalline silicon cell and the transparent electrode layer on a side away from the perovskite absorption layer.

[0025] Compared with the related art, this application has the following technical effects:

[0026] The present application provides a resistance-enhancing layer having nanoscale dispersed nanoparticles on the first carrier transport layer to enhance the resistance of the perovskite light absorption layer, thereby enhancing the light trapping effect of the stacked battery with the resistance-enhancing protrusion structure, effectively solving the battery short circuit problem caused by the exposure of the perovskite film, and improving the photoelectric conversion efficiency of the perovskite / crystalline silicon stacked battery.

[0027] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a schematic structural diagram of a stacked battery with a resistance-increasing protrusion structure proposed in one embodiment of the present application;

[0030] Figure 2 is a flow chart of a method for preparing a resistance-enhancing layer proposed in one embodiment of the present application;

[0031] In the figure, 1. Heterocrystalline silicon cell; 2. Tunnel junction; 3. Conductive layer; 4. First carrier transport layer; 5. Perovskite light absorption layer; 6. Second carrier transport layer; 7. Transparent electrode layer; 8. Resistance increasing layer; 9. Metal electrode. DETAILED DESCRIPTION

[0032] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be construed as limiting the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

[0033] Unless otherwise defined, the technical and scientific terms in this specification have the same meaning as those generally understood by those skilled in the art. Although similar or identical methods and materials as described herein may be used in experiments or practical applications, materials and methods are described herein below. In the event of a conflict, the present specification including the definitions therein shall prevail. In addition, materials, methods and examples are provided for illustration only and are not restrictive. The present application is further described below in conjunction with specific embodiments, but is not intended to limit the scope of the present application.

[0034] According to an embodiment of the present application, a method for preparing a stacked battery with a resistance-increasing protrusion structure is proposed, including forming a tunnel junction on one surface of a heterogeneous crystalline silicon battery; preparing a conductive layer on the surface of the tunnel junction away from the heterogeneous crystalline silicon battery; coating a first carrier transport layer on the surface of the conductive layer away from the tunnel junction; coating a resistance-increasing layer on the surface of the first carrier transport layer away from the conductive layer; coating a perovskite light absorption layer on the surface of the resistance-increasing layer away from the first carrier transport; preparing a second carrier transport layer on a side of the perovskite light absorption layer away from the resistance-increasing layer; forming a transparent electrode layer on a side of the second carrier transport layer away from the perovskite light absorption layer; wherein preparing the resistance-increasing layer also includes preparing a velvet surface with nanoscale protrusions.

[0035] like Figure 1 As shown, the generated stacked battery with a resistance-increasing protrusion structure includes a heterogeneous crystalline silicon battery 1, a tunnel junction 2, a conductive layer 3, a first carrier transport layer 4, a resistance-increasing layer 8, a perovskite light absorption layer 5, a second carrier transport layer 6 and a transparent electrode layer 7 stacked in sequence, wherein the resistance-increasing layer 8 is a velvet surface with nanoscale protrusions.

[0036] The heterogeneous crystalline silicon cell 1 is of n-type or p-type, and can be of single-sided or double-sided structure. It can be prepared by a method known in the prior art, or it can be a commercialized heterogeneous crystalline silicon cell 1, wherein the side of the heterogeneous crystalline silicon cell 1 facing the tunnel junction 2 has a pyramid velvet surface, that is, the heterogeneous crystalline silicon cell 1 has a pyramid velvet surface. Figure 1 In the structure shown, the side facing the tunnel junction 2 has continuously arranged pyramid structures.

[0037] In some embodiments, the structure of the tunnel junction 2 is selected from at least one of a hydrogen-doped n-type microcrystalline silicon stacked with a hydrogen-doped p-type microcrystalline silicon structure, an oxygen-doped n-type amorphous silicon stacked with an oxygen-doped p-type amorphous silicon structure, and a microcrystalline silicon stacked with a silicon oxide structure.

[0038] For example, the structure of the tunnel junction 2 is selected from a structure of hydrogen-doped n-type microcrystalline silicon stacked with hydrogen-doped p-type microcrystalline silicon (nc-Si:H(n + ) / nc-Si:H(p + )), oxygen-doped n-type amorphous silicon stacked with oxygen-doped p-type amorphous silicon structure (a-Si:H(n + ) / a-Si:H(p + )), and microcrystalline silicon stacked silicon oxide structure (nc-Si:H(n + ) / SiO2). During the preparation process, when the tunnel junction 2 is deposited on the n-side of the heterogeneous crystalline silicon cell 1, n-type microcrystalline silicon / amorphous silicon is deposited first, and then p-type microcrystalline silicon / amorphous silicon is deposited thereon; when the tunnel junction 2 is deposited on the p-side of the heterogeneous crystalline silicon cell 1, p-type microcrystalline silicon / amorphous silicon is deposited first, and then n-type microcrystalline silicon / amorphous silicon is deposited thereon.

[0039] The thickness of the tunnel junction 2 is 8-15 nm, for example, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm and any range therebetween.

[0040] In some embodiments, the conductive layer 3 is a metal oxide layer, or a metal material, a mixed material of multiple metals, etc. For example, the material can be selected from one or more of indium tin oxide (ITO), indium zinc oxide (IZO), indium dextrin oxide (IWO), indium oxide (ln2O3), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), zinc oxide (ZnO2), antimony tin oxide (ATO), fluorine tin oxide (FTO), tin oxide (SnO2), and titanium dioxide (TiO2). In addition, the conductive layer 3 can be a complete layer, or a structure with holes or grooves filled with conductive materials.

[0041] Meanwhile, the thickness of the conductive layer 3 is 0.5-20 nm, for example, 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, and any ranges between these values. For example, in a specific embodiment, the thickness of the conductive layer 3 is 5-10 nm, and the conductivity of the conductive layer 3 is greater than 1500 S / m, for example, 1500 S / m, 1600 S / m, 1700 S / m, 1800 S / m, 1900 S / m, 2000 S / m, and any ranges between these values.

[0042] For example, the transmittance of the conductive layer 3 in the range of 300-1200nm light wave is greater than 85%, for example, it can be 86%, 87%, 88%, 89%, 90%, 91%, 92%, 93%, 94%, 95%, and any range between these values. Its work function is 4.5-5.4eV, for example, it can be 4.5eV, 4.6eV, 4.7eV, 4.8eV, 4.9eV, 5eV, 5.1eV, 5.2eV, 5.3eV, 5.4eV, and any range between these values. Among them, the conductivity, work function, carrier concentration, conductivity, and carrier concentration of the conductive layer 3 can all be detected by a Hall effect tester, and the work function can be tested by ultraviolet photoelectron spectroscopy.

[0043] When preparing the conductive layer 3, those skilled in the art will appreciate that different processes may be selected according to different heterogeneous crystalline silicon battery types. For example, when the heterogeneous crystalline silicon battery is a heterogeneous crystalline silicon battery 1, the conductive layer 3 may be deposited by PVD, ALD, spin coating, etc., with a deposition temperature of less than 250°C, preferably less than 190°C.

[0044] The tunnel junction 2 and the conductive layer 3 of the present application are located between the heterogeneous crystalline silicon cell 1 and the first carrier transport layer 4, which is conducive to the collection of lateral charges and improves the filling factor of the stacked cell. Among them, the conductive layer 3 can reduce parasitic absorption, increase the current of the stacked cell, improve the contact resistance between the charge transport layer of the top cell and the tunnel junction 2, and improve the filling factor of the stacked cell. The tunnel junction 2 serves as a barrier layer during the preparation of the conductive layer 3, protecting the heterogeneous crystalline silicon cell from process damage and improving the open circuit voltage of the stacked cell.

[0045] In some embodiments, the first carrier transport layer 4 has a thickness of 20-120 nm and is selected from one of TiO2, SnO2, ZnO or one of PEDOT, PEDOT:PSS, P3HT, P3OHT, P3ODDT, PTAA, and NiO.

[0046] Among them, the first carrier transport layer 4 can be an organic polymer material or a metal oxide material. For organic polymers, a one-step conformal preparation method can be used for preparation; for metal oxide materials, a two-step conformal preparation method can be used for preparation. For example, the first carrier transport layer 4 can be made of an electron transport material or a hole transport material. Among them, the battery transport material can be TiO2, SnO2, ZnO, BBL:PEI (poly (benzimidazole and benzophenanthroline) - polyethylene imine), etc., and the hole transport material can be PEDOT, PEDOT:PSS, P3HT, P3OHT, P3ODDT, PTAA and NiO, etc.

[0047] In the present application, the thickness of the first carrier transport layer 4 is 20-120nm, for example, it can be 0nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm or 120nm. Among them, the first carrier transport layer 4 mainly plays the role of lateral collection and transmission of carriers, that is, the carriers generated by the absorption layer are collected and transmitted horizontally to the perovskite light absorption layer 5. Therefore, this thickness should not be too thick or too thin. If the first carrier transport layer 4 is too thick, the distance of longitudinal transmission to the series structure is too long, resulting in excessive transmission resistance; if the thickness is too thin, the lateral transmission resistance is too large, which is not conducive to the lateral collection and transmission of carriers in the absorption layer.

[0048] Particularly, in the present application, the first carrier transport layer 4 includes a resistance-enhancing layer 8 on one side facing the perovskite light absorption layer 5 .

[0049] The preparation method of the resistance increasing layer 8 is as follows Figure 2 The method includes: S1: preparing a suspension containing nano suspended particles; spraying the suspension onto the side of the first carrier transport layer away from the conductive layer to obtain a nano coating; S2: drying and curing the nano coating to obtain a resistance-enhancing layer having a velvet surface with nano-scale protrusions.

[0050] In some embodiments S1, the nano suspended particles may be nano SiO2, nano TiO2, etc.; the size of the SiO2 nanoparticles is 10-90nm; the size of the TiO2 nanoparticles is 10-150nm. The ratio of the nano suspended particles to the total volume of the suspension is 1 / 800-1 / 500. The suspension is sprayed onto the side of the first carrier transport layer away from the conductive layer using an atomizing device to obtain a nano coating with a thickness of 200nm.

[0051] In S2, the nano coating is dried by heating at 100°C or by vacuuming; and the dried nano coating is cured by treating it at a high temperature of 200-500°C for 100-200 minutes.

[0052] The particle size of the dispersed nanoparticles in the resistance-enhancing layer 8 is 10-300nm; the dispersed nanoparticles in the resistance-enhancing layer 8 are randomly and evenly distributed, with a spacing of 20-200nm. For example, the particle size of the dispersed nanoparticles in the resistance-enhancing layer 8 is 100-300nm, for example, it can be 50nm, 100nm, 200nm, 300nm, etc.; the spacing can be further 50-200nm; for example, it can be 50nm, 100nm, 150nm, 200nm, etc.; by setting the particle size and spacing of the nanoparticles, the perovskite precursor solution can form a thin film with uniform thickness and complete coverage on the velvet pyramid structure of the crystalline silicon battery. The perovskite light absorption layer 5 covers the resistance-enhancing layer 8, wherein when the perovskite light absorption layer 5 is deposited, there will be no exposed area not covered by the resistance-enhancing layer 8, thereby further enhancing the carrier collection and conduction capabilities of the carrier transport material.

[0053] In some embodiments, the stacked cell further includes a metal electrode 9 which is respectively arranged on the heterogeneous crystalline silicon cell 1 and the transparent electrode layer 7 on a side away from the perovskite absorption layer.

[0054] The perovskite light absorption layer 5, the second carrier transport layer 6, the transparent electrode layer 7 and the metal electrode 9 can be prepared based on the technology known in the art. For example, the perovskite light absorption layer 5 can be an organic-hybrid halide perovskite, an all-inorganic halide perovskite, or a lead-free perovskite, a double perovskite or other perovskite structure light absorption material; the transparent electrode layer 7 can be a transparent electrode commonly used in the prior art, such as FTO, ITO, AZO, etc.; the second carrier transport layer 6 can be made of an electron transport material or a hole transport material. For example, in a specific embodiment, Figure 1 As shown, the stacked cell includes a heterogeneous crystalline silicon cell 1, a tunnel junction 2, a conductive layer 3, a first carrier transport layer 4, a perovskite absorption layer, a second carrier transport layer 6 and a transparent electrode layer 7 which are stacked in sequence, and a metal electrode 9 arranged on the side of the heterogeneous crystalline silicon cell 1 and the transparent electrode layer 7 away from the perovskite absorption layer.

[0055] Example 1

[0056] Provide an HJT (heterojunction) solar cell with an N-type silicon wafer as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited using PECVD with a total thickness of 10nm. PVD is used to deposit an ITO layer on the tunnel junction with a thickness of 5nm, and annealed at 190℃ for 30min after deposition.

[0057] A first carrier transport layer is prepared on the surface of the ITO layer, which is PEDOT synthesized by a vapor phase method. The thickness of the first carrier transport layer is 100nm. A resistance increasing layer 8 is coated on the surface of the first carrier transport layer away from the ITO layer. The resistance increasing layer 8 has a thickness of 200nm, wherein the dispersed nanoparticles are randomly and evenly distributed, and the particle size is 300nm; the spacing is 200nm.

[0058] The preparation method of the resistance-increasing layer 8 is as follows: the nano-suspended particles are nano-SiO2 with a size of 10 nm, and the ratio of the nano-suspended particles to the total volume of the suspension is 1 / 800. The suspension is sprayed onto the side of the first carrier transport layer away from the conductive layer by an atomizing device to obtain a nano-coating with a thickness of 200 nm. The nano-coating is dried by heating at 100° C.; and the dried nano-coating is cured at a high temperature of 500° C. for 100 minutes.

[0059] A perovskite light absorption layer is coated on the surface of the resistance-increasing layer 8 away from the ITO layer, wherein the perovskite light absorption layer uses MAPbI3 perovskite with a thickness of 1000nm. The perovskite coating method uses a dip coating method to immerse the crystalline silicon cell covered with the first carrier transport layer in a DMF solution of 1.5M MAPbI3 perovskite and pull it at a speed of 20mm / min. After the pulling is completed, it is dried at 100°C for 10 minutes to obtain the MAPbI3 perovskite light absorption layer. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation. It is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0060] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the stacked cell with the resistance-increasing protrusion structure of this embodiment is 35.9%.

[0061] Example 2

[0062] Provide a HJT (heterojunction) solar cell with a P-type silicon wafer as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited using PECVD with a total thickness of 15nm. PVD is used to deposit an ITO layer on the tunnel junction with a thickness of 15nm, and annealed at 190°C for 30min after deposition.

[0063] A first carrier transport layer is prepared on the surface of the ITO layer, which adopts PEDOT synthesized by a vapor phase method, and the thickness of the first carrier transport layer is 100nm. A resistance increasing layer 8 is coated on the surface of the first carrier transport layer away from the ITO layer, and the thickness of the resistance increasing layer 8 is 5000nm, wherein the dispersed nanoparticles are randomly and evenly distributed, and the particle size is 20nm; the spacing is 200nm.

[0064] The preparation method of the resistance-increasing layer 8 is as follows: the nano-suspended particles are 90 nm nano-TiO2, and the ratio of the nano-suspended particles to the total volume of the suspension is 1 / 600. The suspension is sprayed onto the side of the first carrier transport layer away from the conductive layer by an atomizing device to obtain a nano-coating with a thickness of 200 nm. The nano-coating is dried by heating at 100° C.; and the dried nano-coating is cured at a high temperature of 500° C. for 100 minutes.

[0065] A perovskite light absorption layer is coated on the surface of the resistance increasing layer 8 away from the ITO layer, wherein the perovskite light absorption layer uses lead-free perovskite with a thickness of 1000 nm, and the perovskite coating method refers to Example 1. A second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation, which is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50 nm.

[0066] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the stacked cell with a resistance-increasing protrusion structure of this embodiment is 30.8%.

[0067] Example 3

[0068] Provide HJT (heterojunction) solar cells with N-type silicon wafers as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited by PECVD, with a total thickness of 8nm. PVD is used to deposit an ITO layer on the tunnel junction, with a thickness of 20nm, and annealed at 190℃ for 30min after deposition.

[0069] A first carrier transport layer is prepared on the surface of the ITO layer, which adopts PEDOT synthesized by a vapor phase method. The thickness of the first carrier transport layer is 100nm. A resistance increasing layer 8 is coated on the surface of the first carrier transport layer away from the ITO layer. The resistance increasing layer 8 has a thickness of 1000nm, wherein dispersed nanoparticles are randomly and evenly distributed, and the particle size is 200nm; the spacing is 20nm.

[0070] The preparation method of the resistance-increasing layer 8 is as follows: the nano-suspended particles are 90 nm nano-TiO2, and the ratio of the nano-suspended particles to the total volume of the suspension is 1 / 500. The suspension is sprayed onto the side of the first carrier transport layer away from the conductive layer by an atomizing device to obtain a nano-coating with a thickness of 200 nm. The nano-coating is dried by heating at 100° C.; and the dried nano-coating is cured at a high temperature of 200° C. for 200 min.

[0071] A perovskite light absorption layer is coated on the surface of the resistance increasing layer 8 away from the ITO layer, wherein the perovskite light absorption layer uses lead-free perovskite with a thickness of 1000 nm, and the perovskite coating method refers to Example 1. A second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation, which is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50 nm.

[0072] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the stacked cell with the resistance-increasing protrusion structure of this embodiment is 29.7%.

[0073] Example 4

[0074] Provide a HJT (heterojunction) solar cell with a P-type silicon wafer as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited using PECVD with a total thickness of 13nm. PVD is used to deposit an ITO layer on the tunnel junction with a thickness of 3nm, and annealed at 190℃ for 30min after deposition.

[0075] A first carrier transport layer is prepared on the surface of the ITO layer, which is PEDOT synthesized by a vapor phase method. The thickness of the first carrier transport layer is 100nm. A resistance increasing layer 8 is coated on the surface of the first carrier transport layer away from the ITO layer. The resistance increasing layer 8 has a thickness of 2000nm, wherein dispersed nanoparticles are randomly and evenly distributed, with a particle size of 300nm and a spacing of 100nm.

[0076] The preparation method of the resistance-increasing layer 8 is as follows: the nano-suspended particles are 60 nm nano-TiO2, and the ratio of the nano-suspended particles to the total volume of the suspension is 1 / 600. The suspension is sprayed onto the side of the first carrier transport layer away from the conductive layer by an atomizing device to obtain a nano-coating with a thickness of 200 nm. The nano-coating is dried by heating at 100° C.; and the dried nano-coating is cured at a high temperature of 300° C. for 150 minutes.

[0077] A perovskite light absorption layer is coated on the surface of the resistance increasing layer 8 away from the ITO layer, wherein the perovskite light absorption layer is made of Cs4Mn1-xCuxSb2Cl 12 Perovskite, thickness is 1000nm. The perovskite coating method adopts dip coating method and will not be described in detail. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation method. It is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0078] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the stacked cell with a resistance-increasing protrusion structure of this embodiment is 32.3%.

[0079] Example 5

[0080] Provide HJT (heterojunction) solar cells with N-type silicon wafers as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited by PECVD, with a total thickness of 14nm. PVD is used to deposit an ITO layer on the tunnel junction, with a thickness of 18nm, and annealed at 190℃ for 30min after deposition.

[0081] A first carrier transport layer is prepared on the surface of the ITO layer, which adopts PEDOT synthesized by a vapor phase method. The thickness of the first carrier transport layer is 100nm. A resistance increasing layer 8 is coated on the surface of the first carrier transport layer away from the ITO layer. The thickness of the resistance increasing layer 8 is 3000nm, wherein the dispersed nanoparticles are randomly and evenly distributed, and the particle size is 150nm; the spacing is 150nm.

[0082] The preparation method of the resistance-increasing layer 8 is as follows: the nano-suspended particles are nano-TiO2 with a size of 150 nm, and the ratio of the nano-suspended particles to the total volume of the suspension is 1 / 600. The suspension is sprayed onto the side of the first carrier transport layer away from the conductive layer by an atomizing device to obtain a nano-coating with a thickness of 200 nm. The nano-coating is dried by heating at 100° C.; and the dried nano-coating is cured at a high temperature of 300° C. for 150 minutes.

[0083] A perovskite light absorption layer is coated on the surface of the resistance-increasing layer 8 away from the ITO layer, wherein the perovskite light absorption layer uses MAPbI3 perovskite with a thickness of 1000nm. The perovskite coating method adopts the dip coating method and is not described in detail. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation, which is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0084] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the stacked cell with a resistance-increasing protrusion structure of this embodiment is 31.9%.

[0085] Comparative Example 1

[0086] An HJT (heterojunction) solar cell with an N-type silicon wafer is provided as a bottom cell. An ITO layer with a thickness of 5 nm is deposited on the n-side of the bottom cell by PVD, and annealed at 190° C. for 30 min after deposition.

[0087] A first carrier transport layer is prepared on the surface of the ITO layer, which adopts PEDOT synthesized by a vapor phase method. The thickness of the first carrier transport layer is 100nm. A resistance increasing layer 8 is coated on the surface of the first carrier transport layer away from the ITO layer. The thickness of the resistance increasing layer 8 is 3000nm, wherein the dispersed nanoparticles are randomly and evenly distributed, and the particle size is 150nm; the spacing is 150nm.

[0088] The preparation method of the resistance-increasing layer 8 is as follows: the nano-suspended particles are nano-TiO2 with a size of 200 nm, and the ratio of the nano-suspended particles to the total volume of the suspension is 1 / 600. The suspension is sprayed onto the side of the first carrier transport layer away from the conductive layer by an atomizing device to obtain a nano-coating with a thickness of 200 nm. The nano-coating is dried by heating at 100° C.; and the dried nano-coating is cured at a high temperature of 300° C. for 150 minutes.

[0089] The surface of the resistance-increasing layer 8 is coated with a perovskite light absorption layer, wherein the perovskite light absorption layer adopts MAPbI3 perovskite with a thickness of 800nm. The perovskite coating method adopts a dip coating method to immerse the crystalline silicon cell covered with the first carrier transport layer in a DMF solution of 1.5M MAPbI3 perovskite, and pull it at a speed of 20mm / min. After the pulling is completed, it is dried at 100°C for 10 minutes to obtain the MAPbI3 perovskite light absorption layer. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation. It is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0090] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the stacked cell with the resistance-increasing protrusion structure in this comparative example is 19.9%.

[0091] Comparative Example 2

[0092] Provide HJT (heterojunction) solar cells with N-type silicon wafers, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all using PECVD deposition, with a total thickness of 10nm.

[0093] A first carrier transport layer is prepared on the surface of the ITO layer, which adopts PEDOT synthesized by a vapor phase method. The thickness of the first carrier transport layer is 100nm. A resistance increasing layer 8 is coated on the surface of the first carrier transport layer away from the ITO layer. The thickness of the resistance increasing layer 8 is 3000nm, wherein the dispersed nanoparticles are randomly and evenly distributed, and the particle size is 150nm; the spacing is 150nm.

[0094] The preparation method of the resistance-increasing layer 8 is as follows: the nano-suspended particles are nano-TiO2 with a size of 200 nm, and the ratio of the nano-suspended particles to the total volume of the suspension is 1 / 1000. The suspension is sprayed onto the side of the first carrier transport layer away from the conductive layer by an atomizing device to obtain a nano-coating with a thickness of 200 nm. The nano-coating is dried by heating at 100° C.; and the dried nano-coating is cured at a high temperature of 300° C. for 150 minutes.

[0095] A perovskite light absorption layer is coated on the surface of the resistance-increasing layer 8 away from the tunnel junction, wherein the perovskite light absorption layer uses MAPbI3 perovskite with a thickness of 800nm. The perovskite coating method uses a dip coating method to immerse the crystalline silicon cell covered with the first carrier transport layer in a DMF solution of 1.5M MAPbI3 perovskite and pull it at a speed of 20mm / min. After the pulling is completed, it is dried at 100°C for 10 minutes to obtain the MAPbI3 perovskite light absorption layer. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation. It is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0096] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the stacked cell with a resistance-increasing protrusion structure in this comparative example is 18.4%.

[0097] Comparative Example 3

[0098] Provide HJT (heterojunction) solar cells with P-type silicon wafers. Deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure. Both are deposited using PECVD with a total thickness of 15nm. PVD is used to deposit an ITO layer on the tunnel junction with a thickness of 15nm. After deposition, anneal at 190℃ for 30min.

[0099] A first carrier transport layer is prepared on the surface of the ITO layer, wherein the first carrier transport layer is an ordinary hole transport layer, which adopts PEDOT synthesized by a vapor phase method, and the thickness of the first carrier transport layer is 80nm. A perovskite light absorption layer is coated on the surface of the first carrier transport layer away from the ITO layer, wherein the perovskite light absorption layer adopts lead-free perovskite and has a thickness of 800nm. The perovskite coating method refers to comparative example 1. A second carrier transport layer is prepared by evaporation on the side of the perovskite light absorption layer away from the first carrier transport layer, which is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0100] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the stacked cell with the resistance-increasing protrusion structure in this comparative example is 24.2%.

[0101] Comparative Example 4

[0102] Provide an HJT (heterojunction) solar cell with an N-type silicon wafer as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited using PECVD with a total thickness of 10nm. PVD is used to deposit an ITO layer on the tunnel junction with a thickness of 5nm, and annealed at 190℃ for 30min after deposition.

[0103] A first carrier transport layer is prepared on the surface of the ITO layer, which adopts PEDOT synthesized by a vapor phase method. The thickness of the first carrier transport layer is 100nm. A resistance increasing layer 8 is coated on the surface of the first carrier transport layer away from the ITO layer. The thickness of the resistance increasing layer 8 is 3000nm, wherein the dispersed nanoparticles are randomly and evenly distributed, and the particle size is 150nm; the spacing is 150nm.

[0104] The preparation method of the resistance-enhancing layer 8 is as follows: the nano-suspended particles are nano-TiO2 with a size of 100 nm, and the ratio of the nano-suspended particles to the total volume of the suspension is 1 / 800. The suspension is sprayed onto the side of the first carrier transport layer away from the conductive layer by an atomizing device to obtain a nano-coating with a thickness of 200 nm. The nano-coating is directly cured at a high temperature of 300° C. for 150 minutes.

[0105] A perovskite light absorption layer is coated on the surface of the resistance-increasing layer 8 away from the ITO layer, wherein the perovskite light absorption layer uses MAPbI3 perovskite with a thickness of 800nm. The perovskite coating method uses a dip coating method to immerse the crystalline silicon cell covered with the first carrier transport layer in a DMF solution of 1.5M MAPbI3 perovskite and pull it at a speed of 20mm / min. After the pulling is completed, it is dried at 100°C for 10 minutes to obtain the MAPbI3 perovskite light absorption layer. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation. It is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0106] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the stacked cell with the resistance-increasing protrusion structure in this comparative example is 26.1%.

[0107] It should be noted that, in the description of this application, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0108] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0109] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0110] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for preparing a laminated battery having a resistance-increasing protrusion structure, characterized in that: The following steps are involved: Forming a tunnel junction on one surface of a heterogeneous crystalline silicon cell; Prepare a conductive layer on the surface of the tunnel junction away from the heterogeneous crystalline silicon cell; Coating a first carrier transport layer on a surface of the conductive layer away from the tunnel junction; Coating a resistance-enhancing layer on a surface of the first carrier transport layer away from the conductive layer; Coating a perovskite light absorption layer on a surface of the resistance increasing layer away from the first carrier transmission; Prepare a second carrier transport layer on a side of the perovskite light absorption layer away from the resistance increasing layer; forming a transparent electrode layer on a side of the second carrier transport layer away from the perovskite light absorption layer; The preparation of the resistance-enhancing layer also includes preparing a suede surface with nanoscale protrusions.

2. The preparation method according to claim 1, characterized in that: The method for preparing the resistance-enhancing layer comprises: Preparing a suspension containing nano suspended particles; and spraying the suspension onto a side of the first carrier transport layer away from the conductive layer to obtain a nano coating; The resistance-enhancing layer obtained by drying and curing the nano coating has a velvety surface with nano-scale protrusions.

3. The preparation method according to claim 2, characterized in that: The method of drying the nano coating is heating or vacuuming.

4. The preparation method according to claim 2, characterized in that: The curing method of the nano coating is 200-500°C and the treatment time is 100-200 minutes.

5. The preparation method according to claim 2, characterized in that: The ratio of the volume of nano-suspended particles to the total volume of the suspension is 1 / 800-1 / 500.

6. The preparation method according to any one of claims 2 to 5, characterized in that: The particle size of the dispersed nanoparticles in the resistance-enhancing layer is 10-300 nm.

7. The preparation method according to any one of claims 2 to 5, characterized in that: The dispersed nanoparticles in the resistance-enhancing layer are randomly and evenly distributed with a spacing of 20-200 nm.

8. The preparation method according to claim 6, characterized in that: The perovskite light absorbing layer covers the resistance increasing layer.

9. The preparation method according to claim 6, characterized in that: The first carrier transport layer has a thickness of 20-120 nm and is selected from one of TiO2, SnO2, ZnO or one of PEDOT, PEDOT:PSS, P3HT, P3OHT, P3ODDT, PTAA, and NiO.

10. The preparation method according to claim 6, characterized in that: The stacked cell further comprises metal electrodes respectively arranged on the heterogeneous crystalline silicon cell and the transparent electrode layer on a side away from the perovskite absorption layer.

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