Display device and method for manufacturing same

Abstract

The present disclosure may provide a display device and a method for manufacturing the same. According to one or more embodiments, a display device includes: a pixel electrode over a substrate; a light emitting element over the pixel electrode and including a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer in order, the third semiconductor layer defining a recess exposing a portion of the second semiconductor layer; a via layer over the substrate and surrounding at least a portion of the light emitting element; and a common electrode over the light emitting element and the via layer, and directly contacting the second semiconductor layer through the recess.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0119553 filed in the Korean Intellectual Property Office on September 8, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0003] As multimedia develops, display devices are becoming more and more important. In response to this, various types of display devices such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs) are being used.

[0004] The device for displaying an image on the display device includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. Among them, the light-emitting display panel may include a light-emitting element. For example, a light-emitting diode (LED) includes an organic light-emitting diode (OLED) using an organic material as a light-emitting material, an inorganic light-emitting diode using an inorganic material as a light-emitting material, and the like. Summary of the invention

[0005] Aspects of embodiments of the present disclosure provide a display device that reduces contact resistance of a common electrode and a method of manufacturing the display device.

[0006] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to one or more embodiments, a display device includes: a pixel electrode above a substrate; a light emitting element above the pixel electrode and sequentially including a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer, the third semiconductor layer defining a recess exposing a portion of the second semiconductor layer; a via layer above the substrate and surrounding at least a portion of the light emitting element; and a common electrode above the light emitting element and the via layer and directly contacting the second semiconductor layer through the recess.

[0008] The display device may further include a partition wall unit over the common electrode and defining the light emitting region, and a wavelength conversion layer in a space formed by the partition wall unit and filling the recess.

[0009] The wavelength conversion layer may include a wavelength conversion pattern including a matrix resin and wavelength conversion particles, or include a light transmission pattern including a matrix resin and a scatterer.

[0010] The wavelength conversion layer may further include a scattering layer under the wavelength conversion pattern, the scattering layer including a base resin and a scatterer.

[0011] The width of the recess may be between about 40% and about 90% of the width of the light emitting element.

[0012] The display device may further include: an element insulating layer surrounding the light emitting element in a plan view; and a connection electrode between the first semiconductor layer and the pixel electrode.

[0013] The display device may further include a covering layer over and covering the common electrode.

[0014] The height of the via layer may be lower than the height of the light emitting element.

[0015] The partition wall unit may include: a first partition wall having an inverse tapered shape having a width that narrows in a downward direction; and a first reflective layer surrounding the first partition wall in a plan view.

[0016] The partition wall unit may include: a second partition wall above the first partition wall and having an inverted tapered shape having a width narrowed in a downward direction; and a second reflective layer surrounding the second partition wall in a plan view.

[0017] The display device may further include: an organic pattern layer between the connection electrode and the pixel electrode; and a sub-connection electrode extending along a side surface of the connection electrode to a side surface of the pixel electrode and electrically connecting the connection electrode and the pixel electrode.

[0018] The pixel electrode may protrude outward from a side surface of the organic pattern layer.

[0019] The partition wall unit may include: a first partition wall having an inverse tapered shape having a width that narrows in a downward direction; and a first reflective layer surrounding the first partition wall in a plan view.

[0020] The partition wall unit may include: a second partition wall above the first partition wall and having an inverted tapered shape having a width narrowed in a downward direction; and a second reflective layer surrounding the second partition wall in a plan view.

[0021] The display device may further include an overcoat layer and a color filter layer sequentially over the wavelength conversion layer and the partition wall unit.

[0022] According to one or more embodiments, a method for manufacturing a display device includes: bonding a light emitting element to a pixel electrode above a substrate; the light emitting element includes a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer; forming a via layer above the substrate, the via layer having a height lower than that of the light emitting element; forming a photoresist pattern above the via layer, the photoresist pattern surrounding the light emitting element in a plan view; etching by using the photoresist pattern as a mask to form a recess in the third semiconductor layer to expose a portion of the second semiconductor layer; and forming a common electrode, the common electrode covering the via layer and the light emitting element, and directly contacting the second semiconductor layer through the recess.

[0023] The method may further include: forming a partition wall unit defining a light emitting area over the common electrode; forming a reflective layer surrounding the partition wall unit in a plan view; and forming a wavelength conversion layer in a space formed by the partition wall unit.

[0024] The method may further include forming a scattering layer including a base resin and a scatterer in the light emitting region over the common electrode.

[0025] The light emitting element may further include a connection electrode under the first semiconductor layer, wherein the step of bonding the light emitting element to the pixel electrode includes: performing fusion bonding over the pixel electrode using the connection electrode.

[0026] The light emitting element may further include: a connection electrode under the first semiconductor layer, and wherein the step of bonding the light emitting element to the pixel electrode includes: forming an organic pattern layer between the pixel electrode and the connection electrode; and forming a sub-connection electrode in contact with the pixel electrode and the connection electrode.

[0027] According to the display device according to the embodiment, the second semiconductor layer and the common electrode can be in direct contact to reduce the contact resistance of the common electrode, thereby improving power consumption.

[0028] However, aspects of the present disclosure are not limited to the aforementioned aspects, and various other aspects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a perspective view illustrating a display device according to one or more embodiments.

[0030] Figure 2 and Figure 3 is a plan view showing a display device according to one or more embodiments.

[0031] Figure 4 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0032] Figure 5is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more other embodiments.

[0033] Figure 6 is a cross-sectional view schematically illustrating a display device according to one or more embodiments.

[0034] Figure 7 is schematically shown with reference to Figure 6 An enlarged view of the first light emitting region is depicted.

[0035] Figure 8 Based on reference Figure 7 An enlarged view of a light emitting element of one or more described embodiments.

[0036] Fig. 9 Based on reference Figure 7 A plan view of a pixel electrode and a light emitting element of one or more embodiments is described.

[0037] Fig.10 and Fig.11 It is based on Fig. 9 A plan view of a pixel electrode and a light emitting element of one or more embodiments corresponding to one or more modifications of the embodiments.

[0038] Fig.12 is a cross-sectional view schematically illustrating a display device according to one or more other embodiments.

[0039] Fig.13 is schematically shown with reference to Fig.12 An enlarged view of the first light emitting region is depicted.

[0040] Fig.14 is a cross-sectional view schematically illustrating a display device according to one or more other embodiments.

[0041] Fig.15 is schematically shown with reference to Fig.14 An enlarged view of the first light emitting region is depicted.

[0042] Fig.16 is a cross-sectional view schematically illustrating a display device according to one or more other embodiments.

[0043] Fig.17 is schematically shown with reference to Fig.16 An enlarged view of the first light emitting region is depicted.

[0044] Fig.18 is a cross-sectional view schematically illustrating a display device according to one or more other embodiments.

[0045] Fig.19 is schematically shown with reference to Fig.18 An enlarged view of the first light emitting region is depicted.

[0046] Fig. 20 is a cross-sectional view schematically illustrating a display device according to one or more other embodiments.

[0047] Fig.21 is schematically shown with reference to Fig. 20 An enlarged view of the first light emitting region is depicted.

[0048] Figures 22 to 38 is a diagram for illustrating a method of manufacturing a display device according to one or more embodiments.

[0049] Fig.39 is a view schematically illustrating a virtual reality device including a display device according to one or more embodiments.

[0050] Fig.40 is a view schematically illustrating a smart device including a display device according to one or more embodiments.

[0051] Fig.41 is a view schematically illustrating a vehicle including a display device according to one or more embodiments.

[0052] Fig.42 is a view schematically illustrating a transparent display device including a display device according to one or more embodiments. DETAILED DESCRIPTION

[0053] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for implementing the embodiments. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0054] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown here. The use of "can", "may" or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and alternatives within the conceptual and technical scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be partially combined with each other or all combined with each other, and various technical interlocks and drives are feasible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0055] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading is generally provided in the drawings to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for a specific material, material property, size, ratio, commonality between illustrated elements, and / or any other characteristic, attribute, property, etc. of an element.

[0056] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. As such, variations in the shapes of the diagrams caused by, for example, manufacturing techniques and / or tolerances are anticipated. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the descriptions of the specific structures or functions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the illustrated shapes of elements, layers, or regions, but will include deviations in shapes caused by, for example, manufacturing.

[0057] For example, an implanted region illustrated as a rectangle will, typically, have chamfered or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0058] For ease of explanation, spatial relative terms such as "under ...", "below ...", "lower", "under ...", "below ...", "above ...", "upper", "upper side", etc. may be used here to describe the relationship of one element or feature to another (additional) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element described as "under" "under" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "under ..." and "under ..." can include both upper and lower orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used here should be interpreted accordingly. Similarly, when a first component (part) is described as being arranged "on" a second component (part), this means that the first component (part) is arranged at the upper or lower side of the second component (part), without being limited to its upper side based on the direction of gravity.

[0059] In addition, the phrase "in a plan view" means when viewing an object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting an object portion from the side. The term "overlapping with..." or "overlapping" means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "overlapping with..." may include stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "separate" or "biased" or "deviation" and any other suitable equivalents that will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, but still facing each other.

[0060] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that one or more intervening elements, layers, regions, or components may be present. Additionally, this may collectively mean directly coupled or indirectly coupled or directly connected or indirectly coupled as well as integrally coupled or non-integrally coupled or integrally connected or non-integrally connected. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, capacitors, etc. When describing embodiments, unless explicitly described as being directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component, or is directly on another component, without intermediate components.

[0061] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly below" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components (such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to...") can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0062] For the purposes of this disclosure, expressions such as "at least one of..." or "any one of..." or "one or more of...", when following a list of elements, modify the entire list of elements without modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one of the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XYY, YZ, and ZZ as examples), or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0063] It will be understood that, although the terms "first", "second", "third", etc. can be used here to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or superiority, and are only used to distinguish one element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first section described below may be referred to as the second element, second component, second region, second layer or second section. Describing an element as a "first" element may not require or imply the presence of a second element or other element. The terms "first", "second", etc. may also be used here to distinguish between elements of different categories or elements of different groups. For the sake of simplicity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0064] In the example, directions DR1, DR2 and / or DR3 are not limited to directions corresponding to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, directions DR1, DR2 and DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0065] The terms used herein are only for the purpose of describing the embodiments and are not intended to be limitations of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "one (kind / person)" are also intended to include plural forms, and the plural forms are also intended to include singular forms. It will also be understood that when the terms "include", "comprise", "have" and variations thereof are used in this specification, the descriptions indicate the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0066] When one or more embodiments may be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order.

[0067] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to explain the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. As used herein, "about" or "approximately" includes the stated value and means: taking into account the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system), within the acceptable deviation range of the specific value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0068] In addition, any numerical range disclosed and / or recorded herein is intended to include all sub-ranges of the same numerical precision contained in the recorded range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the recorded minimum value 1.0 and the recorded maximum value 10.0 (and including the recorded minimum value 1.0 and the recorded maximum value 10.0), that is, all sub-ranges with a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit recorded here is intended to include all lower numerical limits contained therein, and any minimum numerical limit recorded in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification (including claims) to explicitly record any sub-ranges contained in the range explicitly recorded here. All such ranges are intended to be inherently described in this specification so that modifications to explicitly record any such sub-ranges will meet the requirements.

[0069] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0070] Figure 1 is a perspective view illustrating a display device according to one or more embodiments.

[0071] Reference Figure 1 The display device 10 is a device for displaying video or still images (such as mobile phones, smart phones, tablet personal computers, and portable electronic devices such as smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMP), navigation and ultra mobile PCs (UMPC)), and display screens for various products such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices).

[0072] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a miniaturized light-emitting display device using a micron or nanometer light-emitting diode (micron LED or nano LED). Hereinafter, the description will focus on the case where the display device 10 is a micro-light-emitting display device, but the present disclosure is not limited thereto. On the other hand, for ease of explanation, an ultra-small light-emitting diode is described here as a micro light-emitting diode.

[0073] The display device 10 includes a display panel 100 , a display driving circuit 250 , and a circuit board 300 .

[0074] The display panel 100 may be formed as a rectangular plane having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. The corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 meet may be rounded to have a curvature (e.g., a predetermined curvature), or may be formed as a right angle. The planar shape of the display panel 100 is not limited to a rectangle, and may be formed as other polygons, a circle, or an ellipse. The display panel 100 may be formed to be flat, but is not limited thereto. For example, the display panel 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel 100 may be formed to be flexible (such as being able to be bent, curved, folded, or curled).

[0075] The display panel 100 may include a main area MA and a sub area SBA.

[0076] The main area MA may include a display area DA that displays an image and a non-display area NDA that is a peripheral area of ​​the display area DA. The display area DA may include a plurality of pixels that display an image. For example, a pixel may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0077] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. Figure 1 The sub-region SBA is shown as being expanded, but the sub-region SBA may be curved, in which case the sub-region SBA may be located on the bottom surface of the display panel 100. When the sub-region SBA is curved, the sub-region SBA may overlap the main region MA in the third direction DR3 that is the thickness direction of the display panel 100. The display driving circuit 250 may be located in the sub-region SBA.

[0078] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC) and may be attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 using a chip on film (COF) method.

[0079] The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. As such, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0080] Figure 2 and Figure 3 is a plan view showing a display device according to one or more embodiments. Figure 2 The sub-area SBA is shown unfolded without being bent. Figure 3 It is shown that the sub-area SBA is bent.

[0081] Reference Figure 2 and Figure 3 , the display panel 100 may include a main area MA and a sub-area SBA.

[0082] The main area MA may include a display area DA displaying an image and a non-display area NDA as a peripheral area of ​​the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be placed at the center of the main area MA.

[0083] The non-display area NDA may be positioned adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be arranged to surround the display area DA. The non-display area NDA may be an edge area of ​​the display panel 100.

[0084] The first scan driver SDC1 and the second scan driver SDC2 may be located in the non-display area NDA. The first scan driver SDC1 is located at one side (e.g., the left side) of the display panel 100, and the second scan driver SDC2 is located at the other side (e.g., the right side) of the display panel 100. However, this is not limited thereto. Each of the first scan driver SDC1 and the second scan driver SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 may receive a scan control signal from the display driving circuit 250, may generate a scan signal according to the scan control signal, and may output the scan signal to the scan line.

[0085] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be less than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and may be located at a lower portion of the display panel 100. In this case, the sub-region SBA may overlap the main region MA in the third direction DR3.

[0086] The sub-area SBA may include a connection area CA, a pad (also referred to as a “pad” or “bonding pad”) area PA, and a bending area BA.

[0087] The connection area CA is an area protruding from one side of the main area MA in the second direction DR2. One side of the connection area CA may contact the non-display area NDA of the main area MA, and the other side of the connection area CA may contact the bending area BA.

[0088] The pad area PA is an area where the pad PD and the display driving circuit 250 are located. The display driving circuit 250 may be attached to the driving pad of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA may be in contact with the bending area BA.

[0089] The bending area BA is a bending area. When the bending area BA is bent, the pad area PA may be located below the connection area CA and below the main area MA. The bending area BA may be located between the connection area CA and the pad area PA. One side of the bending area BA may contact the connection area CA, and the other side of the bending area BA may contact the pad area PA.

[0090] Figure 4 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0091] Reference Figure 4 , the first subpixel SPX1 according to one or more embodiments may be connected to the scan lines GWL, GIL, GCL and GBL, one or more emission lines EL and one or more data lines DL. For example, the first subpixel SPX1 may be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission line EL and the data line DL.

[0092] The first subpixel SPX1 according to one or more embodiments includes a driving transistor DT, a switching element, a capacitor C1, and a first light emitting element LE1. The switching element includes first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0093] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current (hereinafter referred to as a "driving current") flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0094] The first light emitting element LE1 may be a micro light emitting diode. The first light emitting element LE1 emits light according to the driving current. The amount of light emitted from the first light emitting element LE1 may be proportional to the driving current. The anode electrode of the first light emitting element LE1 may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode may be connected to the second power line VSL to which the second power supply voltage is applied.

[0095] The capacitor C1 is formed between the gate electrode of the driving transistor DT and the first power line VDL to which the first power voltage is applied. The first power voltage may be at a higher level than the second power voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode of the capacitor C1 may be connected to the first power line VDL.

[0096] like Figure 4 As shown in , the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 and the driving transistor DT may all be formed as p-type MOSFETs. In this case, the active layer of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 and the driving transistor DT may be formed of polysilicon or an oxide semiconductor.

[0097] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL. The gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL. The gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. Because the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 are formed as p-type MOSFETs, when the scan signal of the gate low voltage and the emission signal are respectively applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL and the light emitting line EL, the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 may be turned on. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0098] Figure 5 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more other embodiments.

[0099] Reference Figure 5 , the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 may be formed as n-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as p-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as n-type MOSFETs may be formed of an oxide semiconductor. In this case, the transistor formed of polysilicon and the transistor formed of an oxide semiconductor may be arranged in different layers.

[0100] Because the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can be turned on when a control scan signal with a gate high voltage is applied to the control scan line GCL, and the third transistor ST3 can be turned on when an initialization scan signal with a gate high voltage is applied to the initialization scan line GIL. In contrast, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, so when a scan signal with a gate low voltage and an emission signal are applied to the write scan line GWL, the bias scan line GBL, and the light emitting line EL, respectively, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be turned on.

[0101] Optionally, Figure 4The fourth transistor ST4 in the embodiment may be formed by an n-type MOSFET. In this case, the active layer of each fourth transistor ST4 may be formed by an oxide semiconductor. When the fourth transistor ST4 is formed by an n-type MOSFET, the fourth transistor ST4 may be turned on when a bias scan signal of a gate high voltage is applied to the bias scan line GBL.

[0102] Alternatively, in one or more embodiments, the first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , and ST6 and the driving transistor DT may all be formed as n-type MOSFETs.

[0103] Meanwhile, the circuit diagram of the second sub-pixel and the third sub-pixel according to one or more embodiments is combined with Figure 4 and Figure 5 The circuit diagram of the first sub-pixel SPX1 described is substantially the same, and thus a description thereof will be omitted.

[0104] Figure 6 is a cross-sectional view schematically illustrating a display device according to one or more embodiments.

[0105] Reference Figure 6 , the display device 10 may include a substrate 110 , a light emitting element unit LEP, a wavelength control unit 200 , and a color filter layer CFL.

[0106] The substrate 110 may be an insulating substrate. The substrate 110 may include a transparent material. For example, the substrate 110 may include a transparent insulating material such as glass, quartz, etc. The substrate 110 may be a rigid substrate. However, the substrate 110 is not limited thereto and may include a plastic such as polyimide and may have a flexible property that allows it to bend, bend, fold, or curl. A plurality of light emitting areas EA1, EA2, and EA3 and a non-emitting area NEA may be defined in the substrate 110.

[0107] The switching elements T1, T2, and T3 may be located on the substrate 110. In one or more embodiments, the first switching element T1 may be located in the first light emitting area EA1 of the substrate 110, the second switching element T2 may be located in the second light emitting area EA2, and the third switching element T3 may be located in the third light emitting area EA3. However, it is not limited thereto, and in one or more other embodiments, at least one of the first switching element T1, the second switching element T2, and the third switching element T3 may be located in the non-emission area NEA.

[0108] In one or more embodiments, the first switching element T1, the second switching element T2, and the third switching element T3 may each be a thin film transistor including amorphous silicon, polycrystalline silicon, or an oxide semiconductor. In one or more embodiments, a plurality of signal lines (e.g., gate lines, data lines, power lines, etc.) transmitting signals to each switching element may be further positioned on the substrate 110.

[0109] Each of the switching elements T1 , T2 , and T3 may include a semiconductor layer 65 , a gate electrode 75 , a source electrode 85 a , and a drain electrode 85 b .

[0110] For example, the buffer layer 60 may be located on the substrate 110 (as used herein, "located on" may mean "over"). The buffer layer 60 may cover the entire surface of the substrate 110. The buffer layer 60 includes silicon nitride, silicon oxide, or silicon oxynitride, and may be composed of a single layer thereof or a double layer thereof.

[0111] The semiconductor layer 65 may be located on the buffer layer 60 (e.g., above the buffer layer 60). The semiconductor layer 65 may form a channel for each of the switching elements T1, T2, T3. The semiconductor layer 65 may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. For example, the oxide semiconductor may include a binary compound (AB) containing, for example, indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ) or quaternary compounds (AB x C y D z In one or more embodiments, the semiconductor layer 65 may include indium tin zinc oxide (ITZO).

[0112] The gate insulating layer 70 may be located on the semiconductor layer 65. The gate insulating layer 70 may include a silicon compound, a metal oxide, etc. For example, the gate insulating layer 70 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. In one or more embodiments, the gate insulating layer 70 may include silicon oxide.

[0113] The gate electrode 75 may be located on the gate insulating layer 70. The gate electrode 75 may overlap the semiconductor layer 65. The gate electrode 75 may include a conductive material. The gate electrode 75 may include a conductive material such as ITO, IZO, ITZO, In 2 O 3The gate electrode 75 may be a metal oxide of a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), or nickel (Ni). For example, the gate electrode 75 may be composed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but is not limited thereto.

[0114] The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may be located on the gate electrode 75. The first interlayer insulating layer 80 may be directly located on the gate electrode 75, and the second interlayer insulating layer 82 may be directly located on the first interlayer insulating layer 80. The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may each include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, etc. However, the present disclosure is not limited thereto, and the second interlayer insulating layer 82 may include an organic insulating material capable of flattening the low level difference. In one or more embodiments, two interlayer insulating layers (the first interlayer insulating layer 80 and the second interlayer insulating layer 82) are shown and described, but the present disclosure is not limited thereto, and only one interlayer insulating layer may be located.

[0115] The source electrode 85a and the drain electrode 85b may be located on the second interlayer insulating layer 82. The source electrode 85a and the drain electrode 85b may contact the semiconductor layer 65 through contact holes passing through the first interlayer insulating layer 80, the second interlayer insulating layer 82, and the gate insulating layer 70, respectively. The source electrode 85a and the drain electrode 85b may include a semiconductor layer such as ITO, IZO, ITZO, In 2 O 3 The source electrode 85a and the drain electrode 85b may be a metal oxide of a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) and / or nickel (Ni). For example, the source electrode 85a and the drain electrode 85b may be composed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but is not limited thereto.

[0116] The first planarization layer 120 may be located on the first switching element T1, the second switching element T2, and the third switching element T3. The first planarization layer 120 may include an organic material. For example, the first planarization layer 120 may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, etc. In one or more embodiments, the first planarization layer 120 may include a positive photosensitive material or a negative photosensitive material.

[0117] The pixel connection electrode 125 may be located on the first planarization layer 120. The pixel connection electrode 125 may correspond to each of the first switching element T1, the second switching element T2, and the third switching element T3, and may be electrically connected to each of the first switching element T1, the second switching element T2, and the third switching element T3. The pixel connection electrode 125 may connect the pixel electrodes PE1, PE2, and PE3 described later to the above-mentioned switching elements T1, T2, and T3. The pixel connection electrode 125 may contact the switching elements T1, T2, and T3 through a contact hole penetrating the first planarization layer 120.

[0118] The second planarization layer 130 may be located on the first planarization layer 120 and the pixel connection electrode 125. The second planarization layer 130 may planarize a low level difference, and may include the same material as the first planarization layer 120 described above.

[0119] The light emitting element unit LEP may be located on the second planarization layer 130. The light emitting element unit LEP may include a plurality of pixel electrodes PE1, PE2 and PE3, a plurality of light emitting elements LE, a via layer VIA and a common electrode CE. In addition, the light emitting element unit LEP may further include a cover layer CAP covering the common electrode CE.

[0120] The plurality of pixel electrodes PE1, PE2 and PE3 may include a first pixel electrode PE1, a second pixel electrode PE2 and a third pixel electrode PE3. The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may be used as first electrodes of the light emitting element LE and may be anode electrodes or cathode electrodes. The first pixel electrode PE1 may be located in the first light emitting area EA1, the second pixel electrode PE2 may be located in the second light emitting area EA2, and the third pixel electrode PE3 may be located in the third light emitting area EA3. The light emitting elements LE may be regularly arranged with a specific rule. For example, the light emitting elements LE may be arranged to be spaced apart from each other at regular intervals.

[0121] In one or more embodiments, the first pixel electrode PE1 may overlap the first light emitting region EA1, the second pixel electrode PE2 may overlap the second light emitting region EA2, and the third pixel electrode PE3 may overlap the third light emitting region EA3.

[0122] Each pixel electrode PE1, PE2 and PE3 may be directly connected to the corresponding pixel connection electrode 125 through a contact hole penetrating the second planarization layer 130, and may be electrically connected to the corresponding switching elements T1, T2 and T3 through the pixel connection electrode 125. The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may include a metal. The metal may include, for example, copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. In addition, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a multilayer structure in which two or more metal layers are stacked. For example, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a double-layer structure in which a copper layer is stacked on a titanium layer, but the structure is not limited thereto.

[0123] A plurality of light emitting elements LE may be located on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The light emitting element LE may be an inorganic light emitting element made of an inorganic material such as GaN.

[0124] The light emitting element LE may be located in each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. The light emitting element LE may be a vertical light emitting diode element extending longitudinally in the third direction DR3. That is, the length of the light emitting element LE in the third direction DR3 may be longer than the length / width in the horizontal direction. The length / width in the horizontal direction refers to the length / width in the first direction DR1 or the length / width in the second direction DR2. For example, the length / width of the light emitting element LE in the first direction DR1 or the length / width in the second direction DR2 may be about 7 μm to about 10 μm, but is not limited thereto. In addition, the length of the light emitting element LE in the third direction DR3 may be about 1 μm to about 5 μm. However, the present disclosure is not limited thereto, and the length of the light emitting element LE in the third direction DR3 may be equal to or less than the length in the horizontal direction.

[0125] The light emitting element LE may be a micro light emitting diode element. The light emitting element LE includes a depression protruding from the top to the bottom. Figures 7 to 10 The structure of the light emitting element LE is described.

[0126] The via layer VIA may be located on the second planarization layer 130 and the pixel electrodes PE1, PE2, and PE3. The via layer VIA covers the pixel electrodes PE1, PE2, and PE3 and may planarize the lower step so that a common electrode CE described later may be formed. The height of the via layer VIA may be less than the height of the light emitting element LE.

[0127] The via layer VIA may include, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0128] The common electrode CE may be located on the via layer VIA and the plurality of light emitting elements LE. For example, the common electrode CE is located on one surface of the substrate 110 on which the light emitting elements LE are formed, and may be located entirely in the display area DA of the substrate 110. The common electrode CE overlaps each of the light emitting areas EA1, EA2, and EA3 and the non-emission area NEA, and may be thin enough to allow light emission.

[0129] The common electrode CE may be directly located on the top surface of the plurality of light emitting elements LE. The common electrode CE may be connected to the second semiconductor layer ( Figure 8 SEM2) in direct contact. Figure 6 As shown in , the common electrode CE covers the via layer VIA and the plurality of light emitting elements LE, and may be a common layer commonly connected to the plurality of light emitting elements LE.

[0130] Since the common electrode CE is entirely located on the substrate 110 and a common voltage can be applied, the common electrode CE may include a material having a low resistance. In addition, the common electrode CE may be formed to be thin for easy light transmission. For example, the common electrode CE may include a metal material having a low resistance such as aluminum (Al), silver (Ag), copper (Cu), etc., or a metal oxide such as ITO, IZO, ITZO, etc. The thickness of the common electrode CE may be about 10Å to about 200Å, but is not limited thereto.

[0131] The above-mentioned light emitting element LE can receive a pixel voltage or an anode voltage from each pixel electrode PE1, PE2 and PE3, and can receive a common voltage through the common electrode CE. The light emitting element LE can emit light with a brightness (e.g., a predetermined brightness) according to the voltage difference between the pixel voltage and the common voltage. In one or more embodiments, by arranging a plurality of light emitting elements LE (i.e., inorganic light emitting diodes) on the pixel electrodes PE1, PE2 and PE3, the disadvantage that the organic light emitting diode is susceptible to external moisture or oxygen can be reduced or eliminated, and the service life and reliability can be improved.

[0132] The covering layer CAP may also be located on the common electrode CE. The covering layer CAP may cover the light emitting element unit LEP located thereunder, and may protect the light emitting element unit LEP from moisture or debris. The covering layer CAP may include an inorganic material. For example, the covering layer CAP may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxide. Meanwhile, the accompanying drawings show that the covering layer CAP is formed as a layer, but the present disclosure is not limited thereto. For example, the covering layer CAP may be formed by a plurality of layers in which inorganic layers containing at least one of the materials that the covering layer CAP may include are alternately stacked. The thickness of the covering layer CAP may be in the range of about 0.05 μm to about 2 μm, but is not limited thereto. The covering layer CAP may be omitted.

[0133] The wavelength control unit 200 may be located on the light emitting element unit LEP. The wavelength control unit 200 may include a partition wall unit PW, a wavelength conversion layer QDL, and a reflective layer RF.

[0134] The partition wall unit PW is located on the cover layer CAP and may divide the plurality of light emitting areas EA1, EA2, and EA3. The partition wall unit PW may extend in the first direction DR1 and the second direction DR2 and may be formed in a grid-like pattern throughout the display area DA. In addition, the partition wall unit PW may not overlap the plurality of light emitting areas EA1, EA2, and EA3 and may overlap the non-emission area NEA.

[0135] The partition wall unit PW may include a negative photosensitive material and may have an inverted tapered shape. The partition wall unit PW may be used to provide a space for a wavelength conversion layer QDL to be formed. The partition wall unit PW may have a relatively large thickness to provide a space in which a wavelength conversion layer QDL is formed. For example, the height of the partition wall unit PW may be in the range of about 8 μm to about 12 μm. The partition wall unit PW may include an organic insulating material. The organic insulating material may include, for example, an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0136] In one or more embodiments, the partition wall unit PW may block the transmission of light in the non-emitting area NEA. The partition wall unit PW may also include a shading material, and may include a dye or pigment having a shading property. For example, the partition wall unit PW may be a black matrix. External light incident from the outside of the display device 10 may cause the problem of color gamut distortion of the wavelength control unit 200. According to one or more embodiments, the partition wall unit PW including the shading material is located in the wavelength control unit 200 so that at least a portion of the external light is absorbed by the shading member. Therefore, the color distortion caused by the reflection of external light can be reduced. In addition, the partition wall unit PW including the shading material can reduce or prevent color mixing due to light entering between adjacent light-emitting areas, thereby further improving the color reproduction rate.

[0137] The reflective layer RF may be located on an inner surface of a space formed by the partition wall unit PW. The reflective layer RF may not overlap the light emitting areas EA1, EA2, and EA3, and may overlap the non-emission area NEA.

[0138] The reflective layer RF may reflect light emitted from the light emitting element LE and traveling laterally upward (eg, in the third direction DR3). The reflective layer RF may include a metal material having high light reflectivity. For example, the reflective layer RF may include aluminum or silver or an alloy thereof.

[0139] The wavelength conversion layer QDL may be located in a space formed by the partition wall unit PW. The wavelength conversion layer QDL may convert or shift the peak wavelength of the incident light into light of another corresponding peak wavelength, and may emit the light. The wavelength conversion layer QDL may convert the blue first light emitted from the light emitting element LE into the red second light or the green third light, or may transmit the blue first light as is.

[0140] The wavelength conversion layer QDL may be located in each of the light emitting regions EA1, EA2, and EA3 divided by the partition wall unit PW, and may be spaced apart from each other. That is, the wavelength conversion layer QDL may be formed into an island pattern spaced apart from each other. The wavelength conversion layer QDL may overlap the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, respectively. In one or more embodiments, each of the wavelength conversion layers QDL may completely overlap the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3.

[0141] The wavelength conversion layer QDL includes a first wavelength conversion pattern WCL1 overlapping the first light emitting area EA1 , a second wavelength conversion pattern WCL2 overlapping the second light emitting area EA2 , and a light transmitting pattern TPL overlapping the third light emitting area EA3 .

[0142] The first wavelength conversion pattern WCL1 may overlap the first light emitting area EA1. The first wavelength conversion pattern WCL1 may convert or shift the peak wavelength of the incident light into light of another corresponding peak wavelength and may emit the light. In one or more embodiments, the first wavelength conversion pattern WCL1 may convert the blue first light emitted from the light emitting element LE of the first light emitting area EA1 into the second light as red light and may emit the red light, the red light having a single peak wavelength in the range of about 610 nm to about 650 nm.

[0143] The first wavelength conversion pattern WCL1 may include a first base resin BRS1, first wavelength conversion particles WCP1, and a scatterer SCP. The first base resin BRS1 may be a first base resin BRS1 and a first wavelength conversion particle WCP1. Fig.15 ) of the base resin BRS0 (see, for example, Fig.15 ) is the same material as, but not limited to. The first base resin BRS1 may include a light-transmitting organic material. For example, the first base resin BRS1 may include epoxy resin, acrylic resin, cardo resin, or imide resin.

[0144] The first wavelength conversion particle WCP1 may convert the first light incident from the light emitting element LE into the second light. For example, the first wavelength conversion particle WCP1 may convert the light in the blue band into the light in the red band. The first wavelength conversion particle WCP1 may be a quantum dot (QD), a quantum rod, a fluorescent material, or a phosphorescent material. For example, a quantum dot may be a particle material that emits a corresponding color when an electron transitions from a conduction band to a valence band.

[0145] Quantum dots can be semiconductor nanocrystal materials. Depending on the composition and size of the quantum dots, the quantum dots can have corresponding band gaps to absorb light and emit light with a specific wavelength. Examples of semiconductor nanocrystals of quantum dots include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group compound nanocrystals, or combinations thereof.

[0146] The II-VI compound may be a binary compound selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; a binary compound selected from the group consisting of InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, A ternary compound selected from the group consisting of CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; and / or a quaternary compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe and mixtures thereof.

[0147] The III-V compound may be: a binary compound selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof; a ternary compound selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb and mixtures thereof; and / or a quaternary compound selected from the group consisting of GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaAlNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0148] The IV-VI compound may be selected from the group comprising: a binary compound selected from the group comprising SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; a ternary compound selected from the group comprising SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; and / or a quaternary compound selected from the group comprising SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. The IV group element may be selected from the group comprising Si, Ge and / or mixtures thereof. The IV group compound may be a binary compound selected from the group comprising SiC, SiGe and mixtures thereof.

[0149] The binary, ternary or quaternary compound may be present in a particle at a uniform concentration, or may be present in the same particle at a partially different concentration distribution. The quantum dot may also have a core-shell structure in which one quantum dot surrounds another quantum dot. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0150] In one or more embodiments, the quantum dot can have a core-shell structure, the core-shell structure comprising a core comprising a nanocrystal as described above and a shell surrounding the core. The shell of the quantum dot can be used as a protective layer to reduce or prevent the possibility of chemical denaturation of the core to maintain semiconductor properties, and / or can be used as a charged layer to impart electrophoretic properties to the quantum dot. The shell can be monolayer or multilayer. Examples of shells for quantum dots include metal or non-metal oxides, semiconductor compounds, or combinations thereof.

[0151] For example, an oxide of a metal or nonmetal may be SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 , NiO, or binary compounds such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 、CoMn 2 O4 The present disclosure may include, but is not limited to, a ternary compound.

[0152] In addition, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but is not limited thereto.

[0153] The second wavelength conversion pattern WCL2 may overlap the second light emitting area EA2. The second wavelength conversion pattern WCL2 may emit light by converting or shifting the peak wavelength of the incident light into light of another corresponding peak wavelength. In one or more embodiments, the second wavelength conversion pattern WCL2 converts the blue first light emitted from the light emitting element LE of the second light emitting area EA2 into a green third light, and may emit the light, the third light having a peak wavelength in the range of about 510 nm to about 550 nm.

[0154] The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2 and scatterers SCP dispersed in the second base resin BRS2.

[0155] The second base resin BRS2 may be made of a material having high light transmittance, may be made of the same material as the first base resin BRS1, or may include at least one of the above materials as its constituent material.

[0156] The second wavelength conversion particles WCP2 may convert or shift the peak wavelength of the incident light to another corresponding peak wavelength. In one or more embodiments, the second wavelength conversion particles WCP2 may convert the blue first light provided from the light emitting element LE into a green third light, and may emit the light, the third light having a peak wavelength in the range of about 510 nm to about 550 nm. Examples of the second wavelength conversion particles WCP2 include quantum dots, quantum rods, or phosphors. A more specific description of the second wavelength conversion particles WCP2 is substantially the same or similar to the description in the description of the first wavelength conversion particles WCP1 described above, and will not be repeated.

[0157] The light-transmitting pattern TPL may be arranged to overlap with the third light-emitting area EA3. The light-transmitting pattern TPL may transmit incident light. The light-transmitting pattern TPL may directly transmit the blue first light emitted from the light-emitting element LE located in the third light-emitting area EA3. The light-transmitting pattern TPL may include a third base resin BRS3 and a scatterer SCP dispersed in the third base resin BRS3. Since the third base resin BRS3 is substantially the same as or similar to the above-mentioned first base resin BRS1, its repeated description will be omitted.

[0158] Meanwhile, a color filter layer CFL may be positioned on the wavelength control unit 200. The color filter layer CFL may include a first overcoat layer OC1, a first color filter CF1, a second color filter CF2, a third color filter CF3, and a second overcoat layer OC2.

[0159] The first overcoat layer OC1 may be located on the wavelength control unit 200. The first overcoat layer OC1 may be located directly on the wavelength control unit 200. The first overcoat layer OC1 may be located entirely throughout the display area DA and may have a flat surface. The first overcoat layer OC1 may flatten a step formed by the underlying wavelength control unit 200 to facilitate formation of a color filter layer CFL.

[0160] The first overcoat layer OC1 may include a light-transmitting organic material. For example, the first overcoat layer OC1 may include epoxy resin, acrylic resin, cardo resin, or imide resin.

[0161] First, second, and third color filters CF1, CF2, and CF3 may be located on the first overcoat layer OC1, in the first emission area EA1, in the second emission area EA2, and in the third emission area EA3.

[0162] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant that absorbs wavelengths other than the corresponding color wavelength, such as a dye or a pigment. The first color filter CF1 may selectively transmit the second light (e.g., red light), and may block or absorb the first light (e.g., blue light) and the third light (e.g., green light). The second color filter CF2 may selectively transmit the third light (e.g., green light), and may block or absorb the first light (e.g., blue light) and the second light (e.g., red light). The third color filter CF3 may selectively transmit the first light (e.g., blue light), and may block or absorb the second light (e.g., red light) and the third light (e.g., green light). For example, the first color filter CF1 may be a red filter, the second color filter CF2 may be a green filter, and the third color filter CF3 may be a blue filter.

[0163] In one or more embodiments, the light incident on the first color filter CF1 may be light converted into the second light in the first wavelength conversion pattern WCL1, the light incident on the second color filter CF2 may be light converted into the third light in the second wavelength conversion pattern WCL2, and the light incident on the third color filter CF3 may be the first light transmitted through the light-transmitting pattern TPL. As a result, the second light transmitted through the first color filter CF1, the third light transmitted through the second color filter CF2, and the first light transmitted through the third color filter CF3 may be emitted to realize full color.

[0164] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb a portion of light entering from the outside of the display device 10 to reduce reflected light caused by the external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can reduce or prevent color distortion caused by reflection of external light.

[0165] The plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be greater than the plane area of ​​each of the plurality of light-emitting regions EA1, EA2, and EA3. For example, the plane area of ​​the first color filter CF1 may be greater than the plane area of ​​the first light-emitting region EA1. The plane area of ​​the second color filter CF2 may be greater than the plane area of ​​the second light-emitting region EA2. The plane area of ​​the third color filter CF3 may be greater than the plane area of ​​the third light-emitting region EA3. However, it is not limited thereto, and the plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be substantially equal to the plane area of ​​each of the plurality of light-emitting regions EA1, EA2, and EA3.

[0166] The second overcoat layer OC2 may be located on the color filter layer CFL. The second overcoat layer OC2 may be located directly on the color filter layer CFL. The second overcoat layer OC2 may be located in the entire display area DA and may have a flat surface. The second overcoat layer OC2 may flatten a step formed by the underlying color filter layer CFL. The second overcoat layer OC2 may include a light-transmitting organic material and may be substantially the same as or similar to the above-described first overcoat layer OC1.

[0167] Figure 7 is schematically shown with reference to Figure 6 An enlarged view of the first light emitting region is depicted. Figure 8 Based on reference Figure 7 An enlarged view of a light emitting element of one or more described embodiments. Fig. 9 Based on reference Figure 7 A plan view of a pixel electrode and a light emitting element of one or more embodiments is described. Fig.10 and Fig.11 is based on Fig. 9 Plan views of pixel electrodes and light emitting elements corresponding to modified versions of one or more embodiments.

[0168] Reference Figures 7 to 9 , the structure on the first light emitting area EA1 has been described as an example, but the structure is not limited thereto, and the structures on the second light emitting area EA2 and the third light emitting area EA3 may be identically configured.

[0169] The connection electrode 150 may be located on each of the plurality of pixel electrodes PE1 , PE2 , and PE3 .

[0170] Hereinafter, the light emitting element LE located on the first pixel electrode PE1 will be described as an example, but the scope is not limited thereto, and the structure of the light emitting element LE located on the second pixel electrode PE2 and the third pixel electrode PE3 may be similarly configured.

[0171] The connection electrode 150 is an electrode connecting the light emitting element LE to the pixel electrodes PE1 , PE2 , and PE3 , and may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti).

[0172] although Figure 8 The connection electrode 150 in which the light emitting element LE has a single-sided structure is shown, but the present disclosure is not limited thereto. In some cases, the light emitting element LE may include a connection electrode 150 in which multiple layers are stacked. For example, the connection electrode 150 may include a reflective layer and a connection layer. The reflective layer may be used to reflect light emitted from the active layer MQW of the light emitting element LE. The reflective layer may be positioned adjacent to the active layer MQW of the light emitting element LE. The reflective layer may include a metal material that is conductive and has a high light reflectivity. The reflective layer may include, for example, aluminum (Al) or silver (Ag) or an alloy thereof. The connection layer may be used to transmit a light emitting signal from the first pixel electrode PE1 to the light emitting element LE. The connection layer may be an ohmic connection electrode. However, the connection layer is not limited thereto and may be a Schottky connection electrode. The connection layer may be located at the bottom of the light emitting element LE and may be positioned farther from the active layer MQW than the reflective layer. The connection layer may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the connection layer may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and tin (SAC305).

[0173] like Figure 8As shown in the figure, the light emitting element LE includes a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, a second semiconductor layer SEM2, and a third semiconductor layer SEM3 in the third direction DR3. The first semiconductor layer SEM1, the electron blocking layer EBL, the active layer MQW, the superlattice layer SLT, the second semiconductor layer SEM2, and the third semiconductor layer SEM3 may be sequentially stacked in the third direction DR3.

[0174] The first semiconductor layer SEM1 may be doped with a first conductive type dopant such as Mg, Zn, Ca, or Ba. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The thickness of the first semiconductor layer SEM1 may be about 30 nm to about 200 nm.

[0175] The electron blocking layer EBL may be located on the first semiconductor layer SEM1. The electron blocking layer EBL may be a layer for suppressing or preventing excessive electrons from flowing into the active layer MQW. For example, the electron blocking layer EBL may be p-AlGaN doped with p-type Mg. The thickness of the electron blocking layer EBL may be about 10 nm to about 50 nm. The electron blocking layer EBL may be omitted.

[0176] The active layer MQW may be located on the electron blocking layer EBL. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light (i.e., light in a blue band) having a central wavelength range of about 450 nm to about 495 nm.

[0177] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. The thickness of the well layer may be about 1 nm to about 4 nm, and the thickness of the barrier layer may be about 3 nm to about 10 nm.

[0178] Alternatively, the active layer MQW may have a structure in which a semiconductor material having a high energy band gap and a semiconductor material having a low energy band gap are alternately stacked with each other, and the active layer MQW may include other group III to group V semiconductor materials according to the wavelength range of the emitted light. The light emitted from the active layer MQW is not limited to the first light (light in the blue band), and in some cases the second light (light in the green band) or the third light (light in the red band) may be emitted. The thickness of the active layer MQW may be about 10 nm to about 25 nm.

[0179] The superlattice layer SLT may be located on the active layer MQW. The superlattice layer SLT may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer SLT may be formed of InGaN or GaN. The thickness of the superlattice layer SLT may be about 50 nm to about 200 nm. The superlattice layer SLT may be omitted.

[0180] The second semiconductor layer SEM2 may be located on the superlattice layer SLT. The second semiconductor layer SEM2 may be doped with a second conductive type dopant such as Si, Ge, Se, or Sn. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may be about 500 nm to about 1 μm.

[0181] The third semiconductor layer SEM3 may include the same material as the second semiconductor layer SEM2, but may be a material not doped with an n-type or p-type dopant. In one or more embodiments, the third semiconductor layer SEM3 may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0182] The third semiconductor layer SEM3 has a recess LE-R protruding in a downward direction. The recess LE-R may penetrate the third semiconductor layer SEM3 and may expose one surface of the second semiconductor layer SEM2. The inclination angle of the inclined surface of the recess LE-R may be a right angle. The width W2 of the recess LE-R may be about 40% to about 90% or more of the width W1 of the light emitting element LE. For example, when the width of the light emitting element LE is about 10 μm, the width of the recess LE-R may be between about 4 μm and about 9 μm, but is not limited thereto. When the recess LE-R is located on the top surface of the second semiconductor layer SEM2 of the light emitting element LE, the width of the recess LE-R may mean the width of the recess LER on the second semiconductor layer SEM2.

[0183] like Fig. 9 As shown in , when the light emitting element LE is circular, the recess LE-R may also be formed in a circular shape. In this case, the light emitting element LE and the recess LE-R may be concentric circles.

[0184] In with Fig. 9 In one or more corresponding other embodiments, it is shown that two light emitting elements LE are located on the first pixel electrode PE1, but it is not limited thereto, and one light emitting element LE or three or more light emitting elements LE may be matched.

[0185] The light emitting element LE may further include an element reflective layer RF0 and an insulating layer INS.

[0186] The element reflection layer RF0 is located on the lower surface of the first semiconductor layer SEM1 (eg, below the first semiconductor layer SEM1), and may include a metal material having high reflectivity. For example, the element reflection layer RF0 may include aluminum or silver or an alloy thereof. The element reflection layer RF0 may be omitted.

[0187] The insulating layer INS may surround the side surface (e.g., the peripheral surface) of the light emitting element LE. The insulating layer INS may insulate the light emitting element LE from other layers. The insulating layer INS may be directly located on the peripheral surfaces of the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3 to surround them (e.g., in a plan view). In one or more embodiments, the insulating layer INS may surround the entire peripheral surface of the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3. The insulating layer INS may be formed to cover the element reflective layer RF0 of the light emitting element LE, but may include / define an opening. The element reflective layer RF0 and the connection electrode 150 may be in contact through an opening in the insulating layer INS formed above / below the element reflective layer RF0.

[0188] In another modified example, the light emitting element LE may include a plurality of insulating layers INS. In addition, the element reflective layer RF0 may be located between the plurality of insulating layers INS, and may be formed to surround the light emitting element LE.

[0189] like Fig.10 and Fig.11 As shown in , the light emitting element LE may have a hexahedral shape. For example, the light emitting element LE may have a size of about 10 μm×25 μm. When the planar shape of the light emitting element LE is a rectangle, the planar shape of the recess LE-R may also be a rectangle. The length of the recess LE-R in the plan view may be proportional to the length of the light emitting element LE in the plan view, but is not limited thereto. The planar shape of the recess LE-R may be similar to the planar shape of the light emitting element LE, but is not limited thereto. As Fig.11 As shown in , the planar shape of the light emitting element LE and the planar shape of the recess LE-R may be different from each other.

[0190] Fig.12 is a cross-sectional view schematically illustrating a display device according to one or more other embodiments. Fig.13 is schematically shown with reference to Fig.12 An enlarged view of the first light emitting region is depicted.

[0191] Reference Fig.12 and Fig.13 , Fig.12 and Fig.13 The embodiment and the above Figures 6 to 10The embodiment of FIG. 1 is different in that the bank BNL is located on the second planarization layer 130 to define the first light emitting area EA1. Hereinafter, descriptions repeated with the above-described embodiment will be omitted, and differences will be described.

[0192] The bank BNL may be formed on the second planarization layer 130 to divide the pixel electrodes PE1, PE2, and PE3 to define the emission areas EA1, EA2, and EA3. The bank BNL may cover the edges of the pixel electrodes PE1, PE2, and PE3. The bank BNL may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0193] The via layer VIA may be located on the bank BNL and the pixel electrodes PE1, PE2, and PE3. The via layer VIA covers the bank BNL and the pixel electrodes PE1, PE2, and PE3, and may planarize a step below so that a common electrode CE described later may be formed.

[0194] Fig.14 is a cross-sectional view schematically illustrating a display device according to one or more other embodiments. Fig.15 is schematically shown with reference to Fig.14 An enlarged view of the first light emitting region is depicted.

[0195] Fig.14 and Fig.15 The embodiments and corresponding Figures 6 to 10 One or more other embodiments of the present invention are different in that the display device 10 further includes a scattering layer QBANK. Hereinafter, descriptions repeated with the above-described embodiments will be omitted, and differences will be described.

[0196] Reference Fig.14 and Fig.15 , the wavelength control unit 200 may include a partition wall unit PW, a scattering layer QBANK, a wavelength conversion layer QDL, and a reflective layer RF.

[0197] The partition wall unit PW is located on the cover layer CAP and may divide the plurality of light emitting areas EA1, EA2, and EA3. The partition wall unit PW is arranged to extend in the first direction DR1 and the second direction DR2 and may be formed in a grid-like pattern throughout the display area DA. In addition, the partition wall unit PW may not overlap the plurality of light emitting areas EA1, EA2, and EA3 and may overlap the non-emission area NEA.

[0198] The reflective layer RF may reflect light emitted from the light emitting element LE and traveling laterally upward (eg, in the third direction DR3). The reflective layer RF may include a metal material having high light reflectivity. For example, the reflective layer RF may include aluminum or silver or an alloy thereof.

[0199] The scattering layer QBANK and the wavelength conversion layer QDL may be sequentially located in a space formed by the partition wall unit PW. The scattering layer QBANK may scatter the light of the light emitting element LE, and may reduce or prevent the heat generated by the light emitting element LE from being directly transferred to the wavelength conversion layer QDL. The scattering layer QBANK may be located on the cover layer CAP. The scattering layer QBANK may be located between the light emitting element LE and the wavelength conversion layer QDL, and may reduce or prevent the degradation of the wavelength conversion layer QDL due to the heat generated from the light emitting element LE.

[0200] The scattering layer QBANK may include a base resin BRSO and a scatterer SCP dispersed in the base resin BRSO. The base resin BRSO may include a light-transmitting organic material. For example, the base resin BRSO may include epoxy resin, acrylic resin, cardo resin, or imide resin.

[0201] The scatterer SCP may scatter the light of the light emitting element LE in random directions. The scatterer SCP may have a refractive index different from that of the base resin BRSO and may form an optical interface with the base resin BRSO. For example, the scatterer SCP may be light scattering particles. The scatterer SCP is not specifically limited to any material capable of scattering at least a portion of the transmitted light, but may be, for example, metal oxide particles or organic particles. Examples of metal oxides include titanium oxide (TiO 2 )、ZrO 2 )、Alumina(Al 2 O 3 )、Indium oxide(In 2 O 3 ), zinc oxide (ZnO) or tin oxide (SnO 2 ), examples of the organic particle material include acrylic resin or urethane resin. The scatterer SCP can scatter light in random directions without substantially converting the wavelength of the light, regardless of the incident direction of the incident light.

[0202] The scattering layer QBANK may be located in the recess LE-R of the light emitting element LE. The wavelength conversion layer QDL may be located on the scattering layer QBANK. The wavelength conversion layer QDL may convert or shift the peak wavelength of the incident light into light of another corresponding peak wavelength, and may emit the light. The wavelength conversion layer QDL may convert the blue first light emitted from the light emitting element LE into the red second light, may convert the blue first light into the green third light, or may transmit the blue first light as is.

[0203] Fig.16 is a cross-sectional view schematically illustrating a display device according to one or more other embodiments. Fig.17 is schematically shown with reference to Fig.16 An enlarged view of the first light emitting region is depicted.

[0204] Fig.16 and Fig.17 Examples and Fig.14 and Fig.15 The embodiment of the present invention is different in that the partition wall unit PW includes a first partition wall PW1 and a second partition wall PW2. Hereinafter, descriptions repeated with the above-described embodiment will be omitted, and differences will be described.

[0205] The partition wall unit PW may be used to provide a space for a wavelength conversion layer QDL to be formed. The partition wall unit PW may be arranged to extend in the first direction DR1 and the second direction DR2, and may have a grid-like pattern throughout the display area DA. In addition, the partition wall unit PW may not overlap with the plurality of light emitting areas EA1, EA2, and EA3, and may overlap with the non-emission area NEA.

[0206] The partition wall unit PW of the double-layered structure including the first partition wall PW1 and the second partition wall PW2 may be relatively thick to provide a space in which the wavelength conversion layer QDL is formed. To this end, the partition wall unit PW may include a first partition wall PW1 and a second partition wall PW2 located on the first partition wall PW1.

[0207] The second partition wall PW2 may be located on the first partition wall PW1 while overlapping the first partition wall PW1.

[0208] The first partition wall PW1 and the second partition wall PW2 may include a negative photosensitive material and may have an inverted tapered shape. The first partition wall PW1 and the second partition wall PW2 may include a thick organic insulating material. The organic insulating material may include, for example, epoxy resin, acrylic resin, cardo resin, or imide resin. The second partition wall PW2 may be located on the first partition wall PW1 while overlapping the first partition wall PW1.

[0209] The first partition wall PW1 and the second partition wall PW2 may block the transmission of light in the non-emitting area NEA. The first partition wall PW1 and the second partition wall PW2 may also include a shading material, and may include a dye or pigment having a shading property. For example, the first partition wall PW1 and the second partition wall PW2 may be a black matrix. External light incident from the outside of the display device 10 may cause the problem of color gamut distortion of the wavelength control unit 200. According to one or more embodiments, the first partition wall PW1 and the second partition wall PW2 including the shading material are located in the wavelength control unit 200 so that at least a portion of the external light is absorbed by the shading member. Therefore, the color distortion caused by the reflection of external light can be reduced. In addition, the first partition wall PW1 and the second partition wall PW2 including the shading material can reduce or prevent color mixing due to light intrusion between adjacent light-emitting areas, thereby further improving the color reproduction rate.

[0210] The height of the partition wall unit PW may be about 10 μm to about 15 μm. The height of the first partition wall PW1 may be about 7 μm to about 9 μm. In addition, the height of the second partition wall PW2 may be about 5 μm to about 7 μm. For example, the height of the first partition wall PW1 may be about 8 μm, and the height of the second partition wall PW2 may be about 6 μm.

[0211] The reflective layer RF may be located on the inner surface of the space formed by the partition wall unit PW. The reflective layer RF may not overlap with the light emitting areas EA1, EA2, and EA3, and may overlap with the non-emission area NEA. The reflective layer RF may include a first reflective layer RF1 and a second reflective layer RF2. The first reflective layer RF1 may surround the side of the first partition wall PW1, and the second reflective layer RF2 may surround the side of the second partition wall PW2.

[0212] The reflective layer RF may reflect light emitted from the light emitting element LE and traveling laterally upward (eg, in the third direction DR3). The reflective layer RF may include a metal material having high light reflectivity. For example, the reflective layer RF may include aluminum or silver or an alloy thereof.

[0213] The scattering layer QBANK may be located in a space formed by the first partition wall PW1. The thickness of the scattering layer QBANK may be smaller than the thickness of the first partition wall PW1.

[0214] The wavelength conversion layer QDL may also be located on the scattering layer QBANK. The wavelength conversion layer QDL may be surrounded by the first partition wall PW1 and the second partition wall PW2. The thickness of the wavelength conversion layer QDL may be thicker than the thickness of the scattering layer QBANK. The thickness of the wavelength conversion layer QDL may be thicker than the thickness of the second partition wall PW2.

[0215] The scattering layer QBANK may be located in the recess LE-R of the light emitting element LE.

[0216] Fig.18 is a cross-sectional view schematically illustrating a display device according to one or more other embodiments. Fig.19 is schematically shown with reference to Fig.18 An enlarged view of the first light emitting region is depicted.

[0217] Fig.18 and Fig.19 The embodiments and corresponding Fig.14 and Fig.15 The embodiment of the present invention is different in that the light emitting element LE is bonded to the sides of the pixel electrodes PE1, PE2, and PE3. Hereinafter, the description repeated with the above-mentioned embodiment will not be repeated, and the differences will be described.

[0218] Reference Fig.18 and Fig.19 The light emitting element unit LEP may include a plurality of pixel electrodes PE1, PE2 and PE3, an organic pattern layer BOL, a plurality of light emitting elements LE, a sub-connection electrode SCE, a via layer VIA and a common electrode CE. In addition, the light emitting element unit LEP may further include a cover layer CAP covering the common electrode CE.

[0219] The organic pattern layer BOL is located on the pixel electrodes PE1, PE2, and PE3. The organic pattern layer BOL may expose at least a portion of the pixel electrodes PE1, PE2, and PE3.

[0220] The organic pattern layer BOL may overlap the light emitting element LE. The light emitting element LE may be located on the organic pattern layer BOL. The connection electrode 150 may also be located between the organic pattern layer BOL and the light emitting element LE. The connection electrode 150 directly contacts the lower portion of the element reflection layer RF0 of the light emitting element LE.

[0221] The organic pattern layer BOL, the connection electrode 150 and the light emitting element LE may be sequentially located on the pixel electrodes PE1, PE2 and PE3. The sub-connection electrode SCE is formed by a deposition method such as sputtering along the side of the light emitting element LE to the side of the connection electrode 150, to the side of the organic pattern layer BOL and to the top surface (or side) of the pixel electrodes PE1, PE2 and PE3. The connection electrode 150 and the pixel electrodes PE1, PE2 and PE3 are electrically connected through the sub-connection electrode SCE.

[0222] like Fig.18 and Fig.19 As shown in FIG. 1 , the pixel electrodes PE1 , PE2 , and PE3 , the organic pattern layer BOL, the connection electrode 150 , and the side surfaces of the light emitting element LE are formed to have step differences with each other, but are not limited thereto.

[0223] In another modified example, at least two of the sides of the organic pattern layer BOL, the connecting electrode 150, and the light emitting element LE may be aligned with each other. For example, the side of the organic pattern layer BOL and the side of the connecting electrode 150 may be aligned with each other. In another example, the side surface of the connecting electrode 150 and the side surface of the light emitting element LE may be aligned with each other. In another example, the side of the organic pattern layer BOL, the side of the connecting electrode 150, and the side of the light emitting element LE may be aligned with each other.

[0224] Fig. 20 is a cross-sectional view schematically illustrating a display device according to one or more other embodiments. Fig.21 is schematically shown with reference to Fig. 20 An enlarged view of the first light emitting region is depicted.

[0225] Fig. 20 and Fig.21 Examples and Fig.18 and Fig.19 The embodiment of the present invention is different in that the partition wall unit PW includes a first partition wall PW1 and a second partition wall PW2. Hereinafter, descriptions repeated with the above-described embodiment will be omitted, and differences will be described.

[0226] Reference Fig. 20 and Fig.21 , the partition wall unit PW may include a first partition wall PW1 and a second partition wall PW2 located on the first partition wall PW1. Fig.16 and Fig.17 The structure of the partition wall unit PW of two layers is described, and thus a detailed description will be omitted.

[0227] Figures 22 to 38 is a diagram for illustrating a method of manufacturing a display device according to one or more embodiments.

[0228] Figure 22 to Figure 26 The structures of the layers of the light emitting element LE are shown in the cross-sectional views in the order of formation. Figures 27 to 38 The manufacturing process of the light emitting element unit LEP is shown, which can be roughly the same as Figures 6 to 8 In addition, the first light emitting area EA1 of the display device 10 is emphasized below.

[0229] Reference Figure 22 to Figure 26 , a plurality of light emitting elements LE are formed on the base substrate BSUB.

[0230] For example, Fig. 22 As shown in FIG. 1 , a plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L are formed on a base substrate BSUB.

[0231] The base substrate BSUB can be a sapphire substrate (Al 2 O 3 ) or a silicon wafer including silicon. However, the base substrate BSUB is not limited thereto, and in one or more embodiments, a case where the base substrate BSUB is a sapphire substrate will be described as an example.

[0232] A plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L are formed on the base substrate BSUB. A plurality of semiconductor material layers grown by an epitaxial method may be formed by growing a seed crystal. Methods for forming semiconductor material layers include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD) and plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), etc., and are preferably formed by metal organic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0233] The precursor material used to form the plurality of semiconductor material layers is not specifically limited to a range that can be conventionally selected for forming the target material. In one example, the precursor material can be a metal precursor including an alkyl group such as a methyl group or an ethyl group. For example, the precursor material can be a metal precursor such as trimethylgallium (Ga(CH 3 ) 3 ), trimethylaluminum (Al(CH 3 ) 3 ), triethyl phosphate ((C 2 H 5 ) 3 PO 4 ) compounds, but not limited thereto.

[0234] For example, a third semiconductor material layer SEM3L is formed on the base substrate BSUB. Although the drawings show a further stacked third semiconductor material layer SEM3L, it is not limited thereto, and a plurality of layers may be formed. The third semiconductor material layer SEM3L may reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. For example, the third semiconductor material layer SEM3L may include an undoped semiconductor that may be an n-type or p-type undoped material. In one or more embodiments, the third semiconductor material layer SEM3L may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0235] By using the above method, the second semiconductor material layer SEM2L, the active material layer MQWL, and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer SEM3L.

[0236] Next, a reflective material layer RFOL is formed on the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L. The reflective material layer RFOL may be formed to cover all of the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L. The reflective material layer RFOL may include aluminum (Al) or silver (Ag), or may be an alloy thereof.

[0237] Then, the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the reflective material layer RFOL may be etched.

[0238] For example, a plurality of first mask patterns MP1 are formed on the reflective material layer RFOL. The first mask patterns MP1 may be a hard mask including an inorganic material or a photoresist mask including an organic material. The first mask patterns MP1 reduce or prevent the possibility that the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the reflective material layer RFOL below are etched. Next, the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, SEM1L and a portion of the reflective material layer RFOL are etched (first etching) using the plurality of first mask patterns MP1 as masks.

[0239] The plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the reflective material layer RFOL not overlapping the first mask pattern MP1 are etched and removed, and portions overlapping the first mask pattern MP1 without being etched may be formed as a plurality of light emitting elements LE on the base substrate BSUB.

[0240] The plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the reflective material layer RFOL may be etched by conventional methods. For example, the process of etching the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the reflective material layer RFOL may be performed by dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of the dry etching method, anisotropic etching is feasible, which may be suitable for vertical etching. When the above etching method is used, the etchant may be Cl 2 or 2 However, it is not limited thereto.

[0241] like Fig.23As shown in the figure, the plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L and the reflective material layer RFOL overlapping the first mask pattern MP1 are not etched and formed into a plurality of light emitting elements LE. Therefore, a plurality of light emitting elements LE including the third semiconductor layer SEM3, the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1 and the element reflective layer RF0 are formed.

[0242] Reference Fig.24 and Fig.25 An element insulating layer INSL having / defining an opening OP is formed on a base substrate BSUB (hereinafter, for convenience of description, may also be referred to as a growth substrate BSUB) on which the light emitting element LE is formed.

[0243] For example, an element insulating layer INSL is formed on the outer surface of the plurality of light emitting elements LE. The element insulating layer INSL may be formed on the entire surface of the base substrate BSUB, and may be formed not only on the light emitting elements LE but also on the top surface of the base substrate BSUB exposed by the light emitting elements LE.

[0244] Then, a second etching is performed to partially remove the element insulating layer INSL to form a first insulating layer INS1 having an opening on the top surface of the light emitting element LE.

[0245] For example, a second etching may be performed in which the element insulating layer INSL is partially removed so that the element insulating layer INSL exposes the top surface of the light emitting element LE while surrounding the side of the light emitting element LE. For example, in this process, the element insulating layer INSL may be removed to expose at least a portion of the top surface of the element reflective layer RF0 of the light emitting element LE. The process of partially removing the element insulating layer INSL may be performed by a mask process.

[0246] Reference Fig.26 , the light emitting element LE can be formed by forming the connection electrode 150 in the opening OP.

[0247] For example, the connection electrode 150 may be formed by stacking a connection electrode material layer on the base substrate BSUB and then etching the connection electrode material layer by an etching process to form the connection electrode 150 located in the opening OP of the light emitting element LE. The connection electrode 150 may be formed to protrude above the foot and the light emitting element LE. The connection electrode material layer is formed of a conductive material and may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the connection electrode material layer may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy (SAC305) of copper, silver, and tin.

[0248] Reference Fig. 27 and Fig.28 , the growth substrate BSUB is bonded to the substrate 110, and the light emitting element LE is bonded to the first pixel electrode PE1. In one or more embodiments, the growth substrate BSUB is shown as being bonded to the substrate 110, but the light emitting element LE grown on the growth substrate BSUB may be bonded to the substrate 110 after being transferred to a temporary substrate, a relay substrate, a transfer film, etc. one or more times.

[0249] First, refer to Fig. 27 , a substrate 110 including a second planarization layer 130 and a first pixel electrode PE1 is prepared.

[0250] A growth substrate BSUB is aligned on the substrate 110. The light emitting element LE grown on the growth substrate BSUB is aligned to be placed on the first pixel electrode PE1 of the substrate 110. The width of the first pixel electrode PE1 may be wider than the width of the light emitting element LE (eg, in a plan view). In this case, the light emitting element LE may be located within the first pixel electrode PE1.

[0251] Next, the substrate 110 and the growth substrate BSUB are bonded. For example, the connection electrode 150 of the light emitting element LE formed on the growth substrate BSUB is brought into contact with the first pixel electrode PE1 of the substrate 110. In this case, the connection electrode 150 of the light emitting element LE is brought into contact with the first pixel electrode PE1. Then, the substrate 110 and the growth substrate BSUB are bonded by melting the connection electrode 150 of the light emitting element LE and the first pixel electrode PE1. At this time, a plurality of light emitting elements LE are attached to the top surface of the first pixel electrode PE1.

[0252] Regarding the fusion bonding, a laser may be irradiated from the top of the growth substrate BSUB toward the first pixel electrode PE1. The first pixel electrode PE1 irradiated with the laser may conduct relatively high heat from the laser to bond the interface of the connection electrode 150 of the light emitting element LE and the first pixel electrode PE1. For example, the first pixel electrode PE1 may include copper (Cu) having suitable thermal conductivity and may have suitable adhesion properties with the connection electrode 150 of the light emitting element LE. YAG may be used as a laser source for the fusion bonding.

[0253] Next, refer to Fig.29 , separating the growth substrate BSUB from the plurality of light emitting elements LE.

[0254] For example, the growth substrate BSUB is separated from the light emitting element LE. The growth substrate BSUB may be separated by a laser lift-off (LLO) process. The growth substrate BSUB may be separated from the light emitting element LE by irradiating the growth substrate BSUB with laser.

[0255] A via layer VIA is formed on the substrate 110 on which the light emitting element LE is formed.

[0256] For example, a via layer VIA may be formed on the first pixel electrode PE1. The via layer VIA may be applied using a solution process such as spin coating, inkjet printing, etc. The via layer VIA may be lower than the height of the light emitting element LE. For example, the top surface of the light emitting element LE may be exposed through the via layer VIA.

[0257] Next, refer to Fig.30 and Fig.31 , using the photoresist pattern PR surrounding the boundary of the light emitting element LE and the via layer VIA, a depression LE-R protruding downward is formed on the top surface of the light emitting element LE. Here, protruding downward means that the center is located further downward.

[0258] For example, the third semiconductor layer SEM3 is etched using the photoresist pattern PR as a mask. The recess LE-R has a surface inclined at about 90 degrees toward the top, and the second semiconductor layer SEM2 may be exposed through the recess LE-R.

[0259] Next, refer to Fig.32 and Fig.33 , a common electrode CE and a capping layer CAP are formed on the light emitting element LE.

[0260] The common electrode CE is continuously formed in the entire display area. The common electrode CE covers the via layer VIA, the insulating layer INS, and the light emitting element LE, and is in direct contact with the via layer VIA, the insulating layer INS, and the light emitting element LE. The common electrode CE is formed along the recess LE-R by directly contacting the top surface of the third semiconductor layer SEM3 and the second semiconductor layer SEM2 of the light emitting element LE. The cover layer CAP may be formed on the entire surface of the substrate 110 to cover the common electrode CE. Therefore, the cover layer CAP may be formed on the common electrode CE along the side surface and the bottom surface of the recess LE-R of the light emitting element LE.

[0261] Next, refer to Fig.34 , a partition wall unit PW is formed on the cover layer CAP.

[0262] For example, the partition wall unit PW is formed on the capping layer CAP using a negative photoresist. Since a portion of the negative photoresist that does not receive light is dissolved, the partition wall unit PW may be formed in an inverted tapered shape having a width that narrows downward.

[0263] Next, refer to Fig.35, a reflective material layer RFL is deposited on the entire surface of the substrate 110 on which the partition wall unit PW is formed. The reflective material layer RFL may be formed to cover the entire partition wall unit PW. The reflective material layer RFL may be formed on the top surface and the side surface of the partition wall unit PW. The reflective material layer RFL may include, for example, aluminum (Al) or silver (Ag), or may be an alloy thereof.

[0264] Reference Fig.36 , the reflective material layer RFL is partially etched to form a reflective layer RF on the side of the partition wall unit PW.

[0265] For example, a large voltage difference is formed in the third direction DR3, and the reflective material layer RFL is etched using an etching material. In this case, the etching material moves in the third direction DR3 (for example, from top to bottom), and the reflective layer RF may be etched. As a result, the reflective material layer RFL located on the horizontal plane defined by the first direction DR1 and the second direction DR2 is removed, while the reflective material layer RFL located on the vertical plane defined by the third direction DR3 may not be removed. Therefore, the reflective material layer RFL located on the top surface of the partition wall unit PW is removed, and only the reflective material layer RFL remains on the side of the partition wall unit PW to form the reflective layer RF.

[0266] Reference Fig.37 , a wavelength conversion layer QDL is formed in a space formed by the partition wall unit PW.

[0267] The wavelength conversion layer QDL may be formed through a solution process such as imprinting, but is not limited thereto. The wavelength conversion layer QDL may be formed to fill a space formed by the partition wall unit PW.

[0268] Next, if Fig.38 As shown in and referenced Figure 6 , the display device 10 according to one or more embodiments is manufactured by forming a color filter layer CFL on a substrate 110. The color filter layer CFL may form a first overcoat layer OC1, a first color filter CF1, and a second overcoat layer OC2.

[0269] The first color filter CF1 may be formed by a photolithography process. For example, the color filter layer CFL is formed by applying a color filter material layer on the wavelength conversion layer QDL and the partition wall unit PW and patterning the color filter material layer by a photolithography process to form the first color filter CF1 overlapped with the wavelength conversion layer QDL. The thickness of the first color filter CF1 may be about 1 μm or less, but is not limited thereto.

[0270] According to one or more embodiments, the second semiconductor layer SEM2 and the common electrode CE are in direct contact through the recess LE-R formed on the top surface of the light emitting element LE to reduce the contact resistance of the common electrode CE. This can improve power consumption.

[0271] Fig.39 is a view illustrating a virtual reality device including a display device according to one or more embodiments. Fig.39 A virtual reality device 1 is shown in which a display device 10 according to one or more embodiments is used.

[0272] Reference Fig.39 The virtual reality device 1 according to one or more embodiments may be a device in the form of glasses. The virtual reality device 1 according to one or more embodiments may include a display device 10, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, left and right legs 30a and 30b, a reflective member 40, and a display device housing 50.

[0273] Fig.39 The virtual reality device 1 including two legs 30a and 30b is shown. However, the disclosure is not limited thereto. The virtual reality device 1 according to one or more embodiments may be used in a head-mounted display including a head-mounted band that can be worn on the head instead of the legs 30a and 30b. For example, the virtual reality device 1 according to one or more embodiments may not be limited to Fig.39 The examples shown in and can be applied in various electronic devices in various forms.

[0274] The display device housing 50 can accommodate the display device 10 and the reflective member 40. The image displayed on the display device 10 can be reflected from the reflective member 40 and can be provided to the right eye of the user through the right eye lens 10b. Therefore, the user can watch the virtual reality image displayed on the display device 10 through the right eye.

[0275] Fig.39 The display device housing 50 is shown to be located at the right end of the support frame 20. However, one or more disclosed embodiments are not limited thereto. For example, the display device housing 50 may be located at the left end of the support frame 20. In this case, the image displayed on the display device 10 may be reflected from the reflective member 40 and may be provided to the user's left eye via the left eye lens 10a. Therefore, the user may view the virtual reality image displayed on the display device 10 via the left eye. As another example, the display device housing 50 may be located at each of the left and right ends of the support frame 20. In this case, the user may view the virtual reality image displayed on the display device 10 via both the left eye and the right eye.

[0276] Fig.40is a view illustrating a smart device including a display device according to one or more embodiments.

[0277] Reference Fig.40 , the display device 10 according to one or more embodiments may be applied to a smart watch 2 which is one of the smart devices.

[0278] Fig.41 is a view illustrating a vehicle including a display device according to one or more embodiments. Fig.41 A vehicle in which a display device according to one or more embodiments is used is shown.

[0279] Reference Fig.41 The display devices 10_a, 10_b, and 10_c according to one or more embodiments may be applied to a dashboard of a vehicle, to a central instrument panel of a vehicle, or to a central information display (CID) located on a dashboard of a vehicle. In addition, each of the display devices 10_d and 10_e according to one or more embodiments may be applied to each interior mirror display that replaces each of the side mirrors of a vehicle.

[0280] Fig.42 is a view illustrating a transparent display device including the display device according to one or more embodiments.

[0281] Reference Fig.42 , the display device 10 according to one or more embodiments may be applied to a transparent display device. The transparent display device may transmit light therethrough while displaying an image IM thereon. Therefore, a user located in front of the transparent display device may not only view the image IM displayed on the display device 10, but may also view an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to a transparent display device, Figure 7 The substrate 110 of the display device 10 shown in FIG. 1 may include a light-transmitting portion through which light is transmitted, or may be made of a material through which light is transmitted.

[0282] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the aspects of the disclosure. Therefore, the disclosed embodiments disclosed are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A display device, comprising: A pixel electrode, on top of the substrate; a light emitting element, which is above the pixel electrode and includes, in sequence, a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer, wherein the third semiconductor layer defines a recess exposing a portion of the second semiconductor layer; a via layer, which is above the substrate and surrounds at least a portion of the light emitting element; as well as A common electrode is above the light emitting element and the via layer and directly contacts the second semiconductor layer through the recess.

2. The display device according to claim 1, further comprising: a partition wall unit, which is above the common electrode and defines a light emitting area; as well as The wavelength conversion layer is in the space formed by the partition wall unit and fills the recess.

3. The display device according to claim 2, wherein: The wavelength conversion layer includes a wavelength conversion pattern including a matrix resin and wavelength conversion particles, or includes a light transmission pattern including a matrix resin and a scatterer.

4. The display device according to claim 3, wherein: The wavelength conversion layer further includes a scattering layer under the wavelength conversion pattern, the scattering layer including the base resin and the scatterer.

5. The display device according to claim 3, wherein: The width of the recess is between 40% and 90% of the width of the light emitting element.

6. The display device according to claim 2, further comprising: an element insulating layer surrounding the light emitting element in a plan view; as well as A connecting electrode is between the first semiconductor layer and the pixel electrode. 7 . The display device according to claim 2 , further comprising a covering layer over and covering the common electrode.

8. The display device according to claim 2, wherein: The height of the via layer is lower than the height of the light emitting element.

9. The display device according to claim 2, wherein: The partition wall unit includes: a first partition wall having an inverted tapered shape having a width that narrows in a downward direction; and a first reflective layer surrounding the first partition wall in a plan view.

10. The display device according to claim 9, wherein: The partition wall unit comprises: a second partition wall above the first partition wall and having an inverted tapered shape having a width narrowing in the downward direction; and The second reflective layer surrounds the second partition wall in a plan view.

11. The display device according to claim 6, further comprising: An organic pattern layer, between the connecting electrode and the pixel electrode; as well as A sub-connecting electrode extends along a side surface of the connecting electrode to a side surface of the pixel electrode and electrically connects the connecting electrode and the pixel electrode.

12. The display device according to claim 11, wherein: The pixel electrode protrudes outward from a side surface of the organic pattern layer.

13. The display device according to claim 11, wherein: The partition wall unit comprises: a first partition wall having an inverted tapered shape having a width that narrows in a downward direction; and The first reflective layer surrounds the first partition wall in a plan view.

14. The display device according to claim 13, wherein: The partition wall unit comprises: a second partition wall above the first partition wall and having an inverted tapered shape having a width narrowing in the downward direction; and The second reflective layer surrounds the second partition wall in a plan view. 15 . The display device of claim 9 , further comprising an overcoat layer and a color filter layer sequentially over the wavelength conversion layer and the partition wall unit.

16. A method for manufacturing a display device, the method comprising: bonding a light emitting element to a pixel electrode above a substrate, the light emitting element comprising a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer; forming a via layer above the substrate, the via layer having a height lower than that of the light emitting element; forming a photoresist pattern over the via layer, the photoresist pattern surrounding the light emitting element in a plan view; forming a recess in the third semiconductor layer to expose a portion of the second semiconductor layer by etching using the photoresist pattern as a mask; as well as A common electrode is formed, the common electrode covers the via layer and the light emitting element and directly contacts the second semiconductor layer through the recess.

17. The method according to claim 16, further comprising: forming a partition wall unit defining a light emitting area above the common electrode; forming a reflective layer surrounding the partition wall unit in a plan view; as well as A wavelength conversion layer is formed in a space formed by the partition wall unit.

18. The method according to claim 17, further comprising: A scattering layer is formed in the light emitting region over the common electrode, the scattering layer including a base resin and a scatterer.

19. The method according to claim 17, wherein: The light emitting element further includes a connection electrode below the first semiconductor layer, and The step of bonding the light emitting element to the pixel electrode includes: performing melting bonding on the pixel electrode using the connection electrode.

20. The method according to claim 17, wherein: The light emitting element further includes a connection electrode below the first semiconductor layer, and The step of bonding the light emitting element to the pixel electrode comprises: forming an organic pattern layer between the pixel electrode and the connecting electrode; and A sub connection electrode is formed to contact the pixel electrode and the connection electrode.

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