Resistor structure and forming method thereof

Abstract

The invention provides a thin film resistor structure for a semiconductor package. The thin film resistor structure comprises a resistor sheet; and two landing pads at opposite ends of the resistor sheet, each landing pad being surrounded by a sidewall divider. The thin film resistor structure may be fabricated in a back-of-line (BEOL) process. The sidewall partitions enhance process control by reducing landing pad undercuts that may occur during fabrication and that may damage the resistor die in subsequent processing steps.

Description

Technical Field

[0001] The present invention relates to a resistor structure and a method for forming the same. Background Art

[0002] Integrated circuits are formed on semiconductor wafers. A photolithography patterning process uses ultraviolet light to transfer the desired mask pattern to a photoresist on the semiconductor wafer. An etching process can then be used to transfer the pattern to the layer beneath the photoresist. This process is repeated multiple times with different patterns to build up different layers on the wafer substrate and create useful devices. Thin-film resistors can be manufactured as part of such integrated circuits. Summary of the Invention

[0003] The present invention is directed to a method for forming a resistor structure. The method includes receiving a resistor stack comprising a resistor sheet, two landing pads at opposite ends of the resistor sheet, and an exposed portion of a metal barrier layer between the two landing pads. The method also includes applying a spacer film layer over the resistor stack. The method also includes etching the spacer film layer to form sidewall spacers around the two landing pads. The method also includes etching away the exposed portion of the metal barrier layer between the two landing pads to form the resistor structure.

[0004] The present invention is also directed to a resistor structure comprising: a resistor sheet; and two landing pads located at opposite ends of the resistor sheet, with sidewall spacers disposed around each landing pad.

[0005] The present invention is also directed to a method for forming a resistor structure in a back-end process of a production line. The method includes: forming a first dielectric layer on a substrate; forming a buffer layer on the first dielectric layer; forming a resistor material layer on the buffer layer; forming a metal barrier layer on the resistor material layer; forming a hard mask layer on the metal barrier layer; performing etching to form a resistor stack from the resistor material layer, the metal barrier layer, and the hard mask layer; etching the hard mask layer to expose a portion of the metal barrier layer located between two ends of the resistor stack; partially etching the exposed portion of the metal barrier layer to form two landing pads at two ends of the resistor stack; applying a spacer film layer on the resistor stack; etching the spacer film layer to form sidewall spacers around the two landing pads; completely etching away the exposed portion of the metal barrier layer between the two landing pads to form a resistor structure; applying a cap layer on the resistor structure; forming a second dielectric layer on the substrate and on the resistor structure; performing etching to form a through hole reaching the two landing pads; filling the through hole with a conductive material; and forming a metal contact on the through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1Ais a cross-sectional view illustrating a first exemplary embodiment of a resistor structure according to some embodiments. The resistor includes sidewall spacers surrounding two landing pads of the resistor structure.

[0007] Figure 1B is a cross-sectional view illustrating a second exemplary embodiment of a resistor structure according to some embodiments. In this embodiment, a peripheral portion of the sidewall spacer extends below the resistor plate of the resistor structure.

[0008] Figure 2A and Figure 2B Together is a flow chart illustrating a method of forming a resistor structure according to some embodiments. The various steps of this method are shown in Figures 3 to 17 .

[0009] Figure 3 is a cross-sectional view after forming selective metal contacts and then forming a first dielectric layer.

[0010] Figure 4 is a cross-sectional view after the first dielectric layer is planarized to obtain a flat surface.

[0011] Figure 5 is a cross-sectional view after a buffer layer is formed on the first dielectric layer.

[0012] Figure 6 It is a cross-sectional view after a resistor material layer, a metal barrier layer, and a hard mask layer are formed on the buffer layer.

[0013] Figure 7 is a cross-sectional view after patterning to form a resistor stack.

[0014] Figure 8 is a cross-sectional view after etching is performed to expose a portion of the metal barrier layer.

[0015] Figure 9 is a cross-sectional view after partially etching the exposed portion of the metal barrier layer.

[0016] Figure 10 is a cross-sectional view after applying a spacer film layer over the resistor stack.

[0017] Figure 11A is a cross-sectional view after the processing step of forming sidewall spacers by etching the spacer film layer.

[0018] Figure 11B yes Figure 11A floor plan of the structure.

[0019] Figure 11C is a cross-sectional view of the second embodiment. Here, the sidewall spacers extend below the resistor material layer or resistor sheet.

[0020] Figure 12 is a cross-sectional view after completely etching away the exposed portion of the metal barrier layer to form a resistor structure.

[0021] Figure 13 is a cross-sectional view after applying a cap layer over the resistor structure.

[0022] Figure 14 is a cross-sectional view after forming the second dielectric layer.

[0023] Figure 15 is a cross-sectional view after the second dielectric layer is planarized to obtain a flat surface.

[0024] Figure 16 is a cross-sectional view after forming through holes reaching the two landing pads of the resistor structure.

[0025] Figure 17 is a cross-sectional view after the via is filled with conductive material. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for implementing the different features of the provided objects. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or on a second component may include embodiments in which the first component and the second component are formed to be in direct contact, and may also include embodiments in which an additional component may be formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the purposes of brevity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0028] The numerical values ​​in the specification and patent claims of this application should be understood to include the same numerical values ​​after being reduced to the same number of significant figures and the numerical values ​​whose difference from the numerical values ​​is less than the experimental error of the conventional measurement technology of the type described in this application for determining the numerical values. All ranges disclosed herein include the listed endpoints.

[0029] The term "about" can be used to include any value that can be varied without changing the basic function of the value. When used in conjunction with a range, "about" also discloses the range defined by the absolute values ​​of the two endpoints, for example, "about 2 to about 4" also discloses a range of "from 2 to 4". The term "about" can mean plus or minus 10% of the specified number.

[0030] The present disclosure relates to structures made from different layers. When the terms "on," "upon," or "over" are used to refer to two different layers (including a substrate), they simply mean that one layer is on or above another layer. These terms do not require that the two layers be in direct contact with each other and allow for other layers to be between the two layers. For example, all layers of a structure can be considered to be "on" a substrate even if they are not all in direct contact with the substrate. The term "directly" can be used to mean that two layers are in direct contact with each other, without any intervening layers.

[0031] The terms "semiconductor die," or "chip," or "microchip" are used interchangeably in this disclosure to refer to the combination of a substrate and multiple layers forming one or more integrated circuits on the substrate.

[0032] As used in this disclosure, the term "semiconductor package" refers to the combination of a semiconductor die and an interconnect layer that allows the semiconductor die to communicate with one or more other packages. Examples of interconnect layers may include a redistribution layer (RDL) or an interposer with bond pads or C4 bumps or pillars. Thus, a semiconductor package may have interconnect layers on only one side or on both sides, as will be seen further herein. It is important to note that in the art, the term "package" is used to refer to many different structures and does not have a single, fixed definition.

[0033] The present disclosure relates to various methods for improving the performance of thin film resistors and corresponding resistor structures, particularly in back-end-of-line (BEOL) processes. Thin film resistors (TFRs) are useful components in high-precision analog and mixed-signal applications, such as radio frequency (RF) circuits, such as oscillators, phase shift networks, filters, or converters; memories, such as dynamic random access memory (DRAM) or static random access memory (SRAM) circuits; or other analog or mixed-signal circuits. TFRs can be part of an individual device or part of a complex hybrid circuit or integrated circuit. The resistance of a TFR depends on the volume of material used in the resistive portion of the resistor. In the present disclosure, sidewall spacers are added to the resistor structure. This reduces / prevents undercutting and provides greater ability to control the final resistance of the TFR.

[0034] Figure 1A is a cross-sectional view illustrating a first exemplary embodiment of a resistor structure according to some embodiments. The resistor structure is part of an overall semiconductor package and is discussed herein as being manufactured during back-end-of-line (BEOL) processing, after integrated circuit formation, when the individual semiconductor dies are interconnected to form the desired circuitry. However, the various process steps described herein are also applicable to manufacturing the resistor structure during front-end-of-line (FEOL) processing.

[0035] Initially, semiconductor package 100 includes a semiconductor die 102 on which a resistor structure will be constructed. The die includes a substrate 104 and a plurality of layers, shown here as one layer 106, forming an integrated circuit on the substrate.

[0036] In some embodiments, the substrate is a wafer made of a semiconductor material. Such a semiconductor material may include silicon, for example, in the form of crystalline Si. In alternative embodiments, the substrate may be made of other elemental semiconductors such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In a specific embodiment, the wafer substrate is silicon.

[0037] Integrated circuits are constructed from conductive and electrically insulating materials with different patterns to fabricate useful components. Suitable examples of integrated circuit components can include (e.g., and without limitation) active components (e.g., transistors), passive components (e.g., capacitors, inductors, resistors, etc.), or combinations thereof. These components can be made of conductive materials such as metals, like copper, aluminum, gold, tungsten, iron, ruthenium, iridium, and their alloys. Suitable examples of electrically insulating materials (i.e., dielectric materials) can include oxides, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), zirconium dioxide (ZrO2), or hafnium dioxide (HfO2); nitrides, such as silicon carbonitride (SiCN), silicon nitride (SiN), hafnium oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), or silicon oxynitride (SiO x N y ), where 0 < x, y ≤ 1; silicates, like hafnium silicate (HfSi x O y ), or zirconium silicate (ZrSi x O y ), where 0 < x, y ≤ 1; polysilicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), borosilicate glass (BSG), high-k dielectric materials, or low-k dielectric materials.

[0038] Continuing, a resistor structure 120 is formed between a first dielectric layer 110 and a second dielectric layer 112. These two layers can be independently regarded as intermetal dielectric (IMD) layers or interlayer dielectric (ILD) layers. The first dielectric layer 110 can also be regarded as a pre-metal dielectric (PMD) layer. These two dielectric layers can be at any level of the interconnect layer above the semiconductor die 102. Metal contacts 114 are illustrated as being present within the first dielectric layer 110.

[0039] The resistor structure 120 itself includes a resistor sheet 140 and two landing pads 122. Each landing pad 122 includes a metal barrier layer 150 and a hard mask layer 160. Sidewall spacers 170 are present around each landing pad. Each sidewall spacer can be regarded as having an inner portion 172 and a peripheral portion 174. The inner portion is above the resistor sheet, and the peripheral portion is not above the resistor sheet. The resistor structure is embedded within a buffer capping layer 130, which is also formed of a dielectric material.

[0040] A pair of vias 116 are shown extending through the second dielectric layer 112 and the buffer cap layer 130 to each landing pad 122. A via 118 is shown extending through the second dielectric layer 112, the buffer cap layer 130, and the first dielectric layer 110 to the metal contact 114. Finally, metal contacts 180, 182 are present above the second dielectric layer 112. This allows a circuit to be formed through the resistor structure 120. The vias 118 allow current to flow to the first dielectric layer and any other components formed in the first dielectric layer or in layers below the first dielectric layer, while bypassing the resistor structure 120.

[0041] Figure 1B is a cross-sectional view illustrating a second exemplary embodiment of a resistor structure according to some embodiments. In this second embodiment, a peripheral portion 174 of the sidewall spacer 170 extends below the resistor sheet 140.

[0042] Figure 2A and Figure 2B Together they form a flow chart illustrating a method 200 for manufacturing a resistor structure in a back-end-of-line process according to some embodiments. Some steps of this method are also illustrated in Figures 3 to 17 These figures provide different views for better understanding. Although the method steps are discussed below with respect to forming a single resistor in a BEOL process, such discussion should also be broadly interpreted as applying to forming multiple resistors simultaneously and / or forming multiple resistors in a FEOL process.

[0043] It should be noted that certain conventional steps are not explicitly described in the following discussion. For example, a pattern / structure may be formed in a given layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer, and then etching.

[0044] Generally speaking, the photoresist layer can be applied, for example, by spin coating or by spraying, roller coating, dip coating or extrusion coating. Usually, in spin coating, substrate is placed on a rotating platen, which may include a vacuum chuck that fixes the substrate on the platen. The photoresist composition is then applied to the center of the substrate. The speed of the rotating platen is then increased so that the resist is evenly spread to the periphery of the substrate from the center of the substrate. The rotating speed of the fixed platen is then used to control the thickness of the final photoresist layer.

[0045] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking is performed at a temperature of about 90°C to about 110°C. Baking can be performed using a hot plate, an oven, or similar equipment. This forms a photoresist layer on the substrate.

[0046] The photoresist layer is then patterned by exposure to radiation. The radiation can be any wavelength of light that carries the desired mask pattern. In a particular embodiment, EUV light with a wavelength of approximately 13.5 nm is used for patterning because this allows for smaller feature sizes. This results in some portions of the photoresist layer being exposed to the radiation, while some portions of the photoresist layer are not. This exposure causes some portions of the photoresist to become soluble in the developer, while other portions of the photoresist remain insoluble in the developer.

[0047] After exposure to radiation, an additional photoresist baking step (post-exposure bake, or PEB) may be performed. This may, for example, help release acid leaving groups (ALGs) or other molecules of interest in chemical amplification photoresists.

[0048] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solution. The soluble portion of the photoresist layer is dissolved and washed away during the development step, leaving behind the photoresist pattern. An example of a common developer is an aqueous solution of tetramethylammonium hydroxide (TMAH). Other developers can include 2-heptanone, n-butyl acetate, isoamyl acetate, cyclohexanone, 5-methyl-2-hexanone, methyl 2-hydroxyisobutyrate, ethyl lactate, or propylene glycol monomethyl ether acetate, n-amyl acetate, n-butyl propionate, n-hexyl acetate, n-butyl butyrate, isobutyl butyrate, 2,5-dimethyl-4-hexanone, 2,6-dimethyl-4-heptanone, propyl isobutyrate, or isobutyl propionate. In general, any suitable developer can be used. Sometimes, a post develop bake or "hard bake" may be performed to stabilize the developed photoresist pattern for optimal performance in subsequent steps.

[0049] Continuing, portions of the layer below the patterned photoresist layer are now exposed. Etching transfers the photoresist pattern to the layer below the patterned photoresist layer. After use, the patterned photoresist layer can be removed, for example, at elevated temperatures using various solvents (e.g., N-methyl-pyrrolidone (NMP) or alkaline media or other strippers) or by dry etching using oxygen plasma.

[0050] Generally speaking, any etching step used herein may be performed using a wet etch, a dry etch, or a plasma etch process (e.g., reactive ion etching (RIE) or inductively coupled plasma (ICP)), or a combination thereof, as appropriate. The etching may be anisotropic. Depending on the material, the etchant may include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), carbon fluoride, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), oxygen (O2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), nitrogen trifluoride (NF3), etc., or combinations thereof in various proportions. For example, hydrofluoric acid and ammonium fluoride can be used to wet etch silicon dioxide. Alternatively, silicon dioxide can be dry etched using various mixtures of CHF3, O2, CF4 and / or H2.

[0051] Then, continue to refer to Figure 2A Optional step 202 and as Figure 3 As shown, one or more metal contacts 114 are formed on the substrate 104 or on the semiconductor die 102. Then, in step 205, a first dielectric layer 110 is formed on the substrate 104. The first dielectric layer also covers the metal contacts 114. (For convenience, the semiconductor die 102 is omitted in other figures.)

[0052] Next, in Figure 2A In step 210, Figure 4 As shown, the first dielectric layer 110 is planarized to obtain a flat surface. For example, a chemical mechanical polishing (CMP) process may be used to perform the planarization.

[0053] Typically, CMP is performed using a rotating platen with a polishing pad attached. The substrate is attached to a rotating carrier. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pad or wafer substrate. During the polishing process, both the polishing pad and carrier rotate, inducing mechanical and chemical action on the surface of the wafer substrate and / or the top layer on the wafer substrate, removing unwanted material and creating a highly level surface. A post-CMP cleaning step is then performed using a rotating brush and a rinse solution to clean one or both sides of the wafer substrate.

[0054] Next, in Figure 2A In step 215, Figure 5 As shown, a buffer layer 132 is formed on the first dielectric layer 110. This buffer layer may also be referred to as a first buffer cap oxide layer. The buffer layer is also formed of a dielectric material and is typically formed of a suitable oxide, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium dioxide (HfO2), or zirconium dioxide (ZrO2). The buffer layer may be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD) or other suitable processes. For example, a silicon-containing source gas may serve as a silicon precursor that reacts with an oxygen-containing source gas. Examples of such silicon precursors include, but are not limited to, tetraethyl orthosilicate (TEOS), trimethylsilane, tetramethylsilane, and hexachlorodisilane (HCDS). Ozone (O3) may be used to provide oxygen atoms for the reaction. At a temperature of about 300°C to about 500°C or higher, these gases will react to deposit silicon dioxide. The buffer layer 132 can have a thickness 133 of about 800 angstroms to about 1200 angstroms, and in some embodiments, about 1000 angstroms, although other values ​​and ranges are within the scope of the present disclosure.

[0055] Now refer to Figure 6 ,exist Figure 2AIn step 220, a resistor material layer 142 is formed on the buffer layer 132. This layer will eventually be formed into a resistor sheet that provides the resistance of the resistor structure. The resistor material layer can be formed by PVD, CVD, sputtering or other suitable processes. The resistor material layer can be formed from a suitable material, such as SiCr, NiCr, TaN, RuO2, PbO, Bi2Ru2O7 or Bi2Ir2O7. In a specific embodiment, the resistor material layer is formed from SiCr. The resistor material layer 142 can have a thickness 143 of about 30 angstroms to about 100 angstroms, and in some specific embodiments has a thickness of about 50 angstroms, but other values ​​and ranges are also within the scope of the present disclosure.

[0056] exist Figure 2A In step 225, a metal barrier layer 150 is formed over the resistor material layer 142. The metal barrier layer can be formed by PVD, CVD, sputtering, or other suitable processes. The barrier metal can be any suitable material, such as titanium nitride (TiN), indium oxide (In2O3), tantalum nitride (TaN), tungsten nitride, tungsten silicide, cobalt, ruthenium, or tantalum. It should be noted that some of these materials are actually ceramics but are considered "barrier metals" by those skilled in the art because they have the common functional property of chemically isolating two materials on opposite sides while still maintaining an electrical connection between the two materials. In a specific embodiment, the metal barrier layer is formed of TiN. The metal barrier layer 150 can have a thickness 153 of about 600 angstroms to about 900 angstroms, and in some specific embodiments, a thickness of about 750 angstroms, although other values ​​and ranges are also within the scope of the present disclosure.

[0057] Then, in Figure 2A In step 230, a hard mask layer 160 is formed on the metal barrier layer 150. Similarly, the hard mask layer can be formed by PVD, CVD, sputtering or other suitable processes. The hard mask material can be any suitable material, and in a specific embodiment is silicon oxynitride (SiO x N y ). The hard mask layer 160 may have a thickness 163 of about 200 angstroms to about 500 angstroms, and in some specific embodiments, about 320 angstroms, although other values ​​and ranges are within the scope of the present disclosure. The structure generated after step 230 is shown in FIG. Figure 6 .

[0058] In some specific embodiments, the metal barrier layer thickness 153 and the hard mask layer thickness 163 together have a total thickness of about 1000 angstroms to about 1200 angstroms, although other values ​​and ranges are within the scope of the present disclosure.

[0059] A photoresist layer is applied and patterned using a first mask (M0). Figure 2A In step 235, etching is performed to form the resistor stack 124 from the resistor material layer 142, the metal barrier layer 150, and the hard mask layer 160. The photoresist layer is then removed. The resulting structure is shown in FIG. Figure 7 It is worth noting that the resistor material can now be considered as a resistor sheet 140. The thickness of the resistor sheet is the same as the thickness of the resistor material layer.

[0060] Another photoresist layer is applied and patterned using a second mask (MR). Figure 2A In step 240, the hard mask layer 160 is then etched to expose the portion 154 of the metal barrier layer located between the two ends of the resistor stack; the photoresist layer is then removed. The resulting structure is shown in FIG. Figure 8 .

[0061] Next, in Figure 2A In step 245, the exposed portion 154 of the metal barrier layer is partially etched. In certain embodiments, the partial etching is performed using dry etching. The resulting structure is shown in FIG. Figure 9 As seen here, this partial etching forms two landing pads 122 at the ends of the resistor stack, or at opposite ends or sides of the resistor chip 140. Each landing pad 122 includes a metal barrier layer 150 and a hard mask layer 160. Note that a thin layer 156 of the metal barrier layer still exists above the resistor chip, which has not yet been exposed from the top. In a more general embodiment of method 200, a resistor stack 124 having the structure thus described is received.

[0062] Next, in Figure 2A In step 250, a spacer film layer 176 is applied over the resistor stack, or in other words, over the substrate (not shown). The resulting structure is shown in FIG. Figure 10 . The spacer film layer is formed of a dielectric material and is different from the hard mask material and the barrier metal. The spacer film layer can be formed by CVD, atomic layer deposition (ALD), or other suitable processes. The spacer film layer 176 can have a thickness 177 of about 20 angstroms to about 100 angstroms, but other values ​​and ranges are also within the scope of the present disclosure. The spacer film layer can generally be described as being adhered to the exposed surfaces of the layers below it. It should also be noted that the spacer film layer extends below the upper surface 152 of the metal barrier layer 150.

[0063] Then, in Figure 2AIn step 255, the spacer film layer is etched to form sidewall spacers 170 around the two landing pads 122. The etching process removes horizontal portions of the spacer film layer, leaving vertical portions. Figure 11A A cross-sectional view showing the resulting structure, Figure 11B A plan view is provided. Note that the thin layer 156 of the metal barrier 150 protects the resistor plate 140 from being damaged during this etching step.

[0064] Reference first Figure 11A , an inner portion 172 of the sidewall spacer 170 is located above the resistor chip 140 and contacts the upper surface of the metal barrier layer 150. However, the inner portion 172 of the sidewall spacer does not contact the buffer layer 132. A peripheral portion 174 of the sidewall spacer 170 contacts the side surfaces of the resistor chip 140 and the metal barrier layer 150. The peripheral portion 174 of the sidewall spacer 170 also contacts the upper surface of the buffer layer 132. In some embodiments, the thickness 175 of the peripheral portion 174 of the sidewall spacer 170 can be equal to or greater than the thickness 173 of the inner portion 172 of the sidewall spacer 170. In some embodiments, the thicknesses 173 and 175 of the sidewall spacer portions can independently be between about 800 angstroms and about 1500 angstroms, although other values ​​and ranges are also within the scope of the present disclosure.

[0065] Now refer to Figure 11B , sidewall spacers 170 are shown as having a four-sided square shape. More generally, sidewall spacers can have any desired shape, such as a circle, triangle, rectangle, or other polygonal shape. As shown, an inner portion 172 of the sidewall spacer forms one side of the square, while a peripheral portion 174 of the sidewall spacer forms the other three sides of the square. A thin layer of metal barrier layer 156 can be seen between the two inner portions 172 of the sidewall spacer. The hard mask layer 160 of each landing pad can also be seen.

[0066] It should be noted that during step 245 of partially etching the exposed portion 154 of the metal barrier layer, the exposed buffer layer 132 may also be partially etched. As a result, the thickness of the exposed buffer layer may be reduced. Therefore, in some embodiments, when the spacer film layer 176 is deposited and then etched to form the sidewall spacers 170, the peripheral portion 174 of the sidewall spacers may extend below the resistor material layer 142 / resistor sheet 140. This structure is shown in FIG. Figure 11C In this embodiment, the thickness 175 of the peripheral portion of the sidewall spacer is greater than the sum of the thickness of the resistor sheet 143 , the thickness of the metal barrier layer 153 , and the thickness of the hard mask layer 163 .

[0067] Next, in Figure 2AIn step 260, the exposed portion of the metal barrier layer between the two landing pads is completely etched away to form a resistor structure. The resulting structure is shown in FIG. Figure 12 . In certain embodiments, this step is performed by wet etching, which can provide better selectivity for the barrier metal than the resistor sheet so that the resistor sheet is not damaged. As shown here, the presence of the sidewall spacers 170 reduces or prevents undercutting of the metal barrier layer that may occur, particularly on the peripheral portion of the metal barrier layer. If any undercutting does occur, it occurs under the inner portion 172 of the sidewall spacers, which is much less exposed than from under the hard mask layer 160. The resistor length 145 is the distance between the two landing pads 122. In some specific embodiments, the resistor length is about 1 micron to about 100 microns, but other values ​​and ranges are also within the scope of the present disclosure.

[0068] Next, in Figure 2A In step 265 and as Figure 13 As shown, a cap layer 134 is applied over the resistor structure. The cap layer 134 may also be applied over the exposed buffer layer 132. The cap layer is formed of a dielectric material. The cap layer may be formed by PVD, CVD, ALD, or other suitable processes. In certain embodiments, the dielectric material of the cap layer 134 is the same as that used for the buffer layer 132, and the two layers are formed together. Figure 1A The buffer cap layer 130 is formed of a dielectric material that is typically different from the material used to form the hard mask layer 160, the metal barrier layer 150, and the sidewall spacers 170. The cap layer 134 can have a thickness 135 of about 300 angstroms to about 700 angstroms, and in some embodiments, about 500 angstroms, although other values ​​and ranges are within the scope of the present disclosure.

[0069] Then, in Figure 2A In step 270, a second dielectric layer 112 is formed on the substrate and over the resistor structure 120. The resulting structure is shown in FIG. Figure 14 .

[0070] Next, in Figure 2B In step 275 and as Figure 15 As shown, the second dielectric layer 112 is planarized to obtain a planar surface. Again, the planarization can be performed using, for example, a CMP process.

[0071] exist Figure 2B In step 280 and as Figure 16 As shown, a through hole 116 is formed to reach the two landing pads 122. More specifically, the through hole passes through the hard mask layer 160 and terminates at the metal barrier layer 150. This can be done by etching, or it can be done by laser drilling. Figure 16 As shown, in this step, a through hole 118 reaching the metal contact 114 may also be formed in the first dielectric layer 110 .

[0072] Next, in Figure 2B In step 285, and as Figure 17 As shown, via 116 is filled with a conductive material. Via 118 is also filled.

[0073] Then, in Figure 2B In step 290, and as Figure 1A As shown, metal contacts 180 are formed over vias 116. These metal contacts may also be described as being located over landing pads 122 of the resistor structure or over second dielectric layer 112. Metal contacts 182 are also formed over vias 118.

[0074] The method and system disclosed herein are advantageous. Figure 2A and Figure 8 If no sidewall spacers are formed in steps 245 to 255, then etching of the metal barrier layer 150 is performed in step 260. If no sidewall spacers are present, all exposed surfaces of the metal barrier layer 150 will be etched, and it will be difficult to prevent undercutting under the hard mask layer 160. This will result in the formation of voids in the metal barrier layer. Then, in the step 260, Figure 13 During the deposition of the cap layer as shown, the deposited material will most readily adhere to the exposed surfaces of the various layers. The presence of pores will result in little or no material being present to build up the cap layer on the vertical sides of the metal barrier layer, which results in pores also extending through the cap layer 134, particularly along the perimeter of the resistor sheet 140. Finally, as described above, after CMP, a post-CMP cleaning step is then performed, for example using a fluid such as dilute hydrofluoric acid (DHF). Referring now to Figure 15 , it should be remembered that these figures are illustrative of structures having layers with thicknesses measured in angstroms. The second dielectric layer 112 may include seams connected to the pores, which may form when the sidewall spacers are not present. When this occurs, the DHF used in the post-CMP cleaning step can penetrate into the pores through the seams, which can cause damage to the resistor strip 140. The use of sidewall spacers 170 as in the present disclosure reduces or prevents undercutting of the metal barrier layer, which can affect control of the resistance present in the resistor structure by damaging the resistor strip 140. This improves process control and increases device quality, reproducibility, and overall device yield.

[0075] Additional processing steps may be performed to obtain a device having a semiconductor package including a resistor structure. These semiconductor packages may be used in various applications, such as BCD (bipolar-CMOS-DMOS) circuits for driving discrete high-voltage components; drivers for liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), active-matrix organic light-emitting diodes (AMOLEDs), or quantum dot light-emitting diodes (QLEDs); image sensors for systems such as mobile phones, facial recognition systems, or as mobile sensors for automotive applications, security applications, energy efficiency, etc.; power management devices for controlling the flow of power; and / or image signal processors (ISPs).

[0076] Therefore, some aspects of the present disclosure relate to a method for forming a resistor structure. A resistor stack is received, comprising a resistor sheet, two landing pads at opposite ends of the resistor sheet, and an exposed portion of a metal barrier layer between the two landing pads. A spacer film layer is applied over the resistor stack, and the spacer film layer is then etched to form sidewall spacers around the two landing pads. The exposed portion of the metal barrier layer between the two landing pads is then etched away to form a resistor structure.

[0077] In some embodiments, the resistor sheet comprises SiCr, NiCr, TaN, RuO2, PbO, Bi2Ru2O7, or Bi2Ir2O7. In some embodiments, the metal barrier layer comprises titanium nitride (TiN), indium oxide (In2O3), tantalum nitride (TaN), tungsten nitride, tungsten silicide, cobalt, ruthenium, or tantalum. In some embodiments, the separator film layer comprises a dielectric material. In some embodiments, the peripheral portion of the sidewall separator extends below the resistor sheet. In some embodiments, the length of the resistor sheet between the two landing pads is about 1 micron to about 100 microns. In some embodiments, the resistor sheet has a thickness of about 30 angstroms to about 100 angstroms. In some embodiments, each landing pad has a thickness of about 1000 angstroms to about 1200 angstroms. In some embodiments, each of the two landing pads comprises a metal barrier layer and a hard mask layer. In some embodiments, the method further comprises: applying a cap layer over the resistor structure; forming a second dielectric layer over the resistor structure; etching to form a through hole that reaches the two landing pads; filling the through hole with a conductive material; and forming a metal contact over the through hole. In some embodiments, the resistor stack is formed by: forming a resistor material layer; forming a metal barrier layer on the resistor material layer; forming a hard mask layer on the metal barrier layer; etching the resistor material layer, the metal barrier layer, and the hard mask layer to form a resistor stack; etching the hard mask layer to expose a portion of the metal barrier layer between the two ends of the resistor stack; and partially etching the exposed portion of the metal barrier layer to form two landing pads at the two ends of the resistor stack. In some embodiments, the hard mask layer comprises silicon oxynitride (SiON). In some embodiments, the resistor material layer is formed on a buffer layer over the semiconductor die. In some embodiments, the buffer layer is formed on the first dielectric layer.

[0078] Also disclosed herein, in various embodiments, is a method for forming a resistor structure in a back-end process. A first dielectric layer is formed on a substrate. A buffer layer is formed on the first dielectric layer. A resistor material layer is formed on the buffer layer. A metal barrier layer is formed on the resistor material layer. A hard mask layer is formed on the metal barrier layer. Etching is performed to form a resistor stack from the resistor material layer, the metal barrier layer, and the hard mask layer. The hard mask layer is then etched to expose a portion of the metal barrier layer between the ends of the resistor stack. The exposed portion of the metal barrier layer is then partially etched to form two landing pads at the ends of the resistor stack. A spacer film layer is applied over the resistor stack. The spacer film layer is then etched to form sidewall spacers around the two landing pads. The exposed portion of the metal barrier layer between the two landing pads is then completely etched away to form the resistor structure. A cap layer is applied over the resistor structure. A second dielectric layer is then formed over the substrate and over the resistor structure. Vias are formed by etching to reach the two landing pads. The through-holes are filled with conductive material and metal contacts are then formed over the through-holes.

[0079] In some embodiments, peripheral portions of the sidewall spacers extend below the resistor material layer.

[0080] Also disclosed herein in various embodiments is a resistor structure comprising a resistor sheet and two landing pads at opposite ends of the resistor sheet, each landing pad being surrounded by a sidewall spacer.

[0081] In some embodiments, a peripheral portion of the sidewall spacer extends below the resistor chip. In some embodiments, each landing pad includes a metal barrier layer and a hard mask layer. In some embodiments, the resistor structure further includes a buffer layer below the resistor chip and a cap layer covering the resistor chip and the two landing pads.

[0082] Also disclosed herein is a semiconductor package including a resistor structure. Such a package typically also includes an integrated circuit (IC). Also contemplated are devices including such a semiconductor package, such as display panel drivers, image sensors, mobile phones, facial recognition systems, motion sensors, power management devices, and / or image signal processors.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for forming a resistor structure, characterized in that: include: receiving a resistor stack comprising a resistor sheet, two landing pads at opposite ends of the resistor sheet, and an exposed portion of a metal barrier layer between the two landing pads; applying a separator film layer over the resistor stack; etching the spacer film layer to form sidewall spacers around the two landing pads; as well as The exposed portion of the metal barrier layer between the two landing pads is etched away to form the resistor structure.

2. The method according to claim 1, characterized in that The length of the resistor sheet between the two landing pads is about 1 micrometer to about 100 micrometers.

3. The method according to claim 1, characterized in that The resistor sheet has a thickness of about 30 angstroms to about 100 angstroms.

4. The method according to claim 1, characterized in that: The landing pads each have a thickness of about 1000 angstroms to about 1200 angstroms.

5. A resistor structure, characterized in that: include: Resistor chips; as well as Two landing pads are located at opposite ends of the resistor sheet, and a side wall spacer is arranged around each landing pad.

6. The resistor structure according to claim 5, characterized in that A peripheral portion of the sidewall spacer extends below the resistor sheet.

7. The resistor structure according to claim 5, characterized in that Each of the landing pads includes a metal barrier layer and a hard mask layer.

8. The resistor structure according to claim 5, characterized in that The invention also includes a buffer layer located under the resistor sheet and a top cover layer covering the resistor sheet and the two landing pads.

9. A method for forming a resistor structure in a back-end process of a production line, characterized in that: include: forming a first dielectric layer on the substrate; forming a buffer layer on the first dielectric layer; forming a resistor material layer on the buffer layer; forming a metal barrier layer on the resistor material layer; forming a hard mask layer on the metal barrier layer; performing etching to form a resistor stack from the resistor material layer, the metal barrier layer, and the hard mask layer; etching the hard mask layer to expose a portion of the metal barrier layer between two ends of the resistor stack; partially etching the exposed portion of the metal barrier layer to form two landing pads at the two ends of the resistor stack; applying a separator film layer over the resistor stack; etching the spacer film layer to form sidewall spacers around the two landing pads; completely etching away the exposed portion of the metal barrier layer between the two landing pads to form the resistor structure; applying a cap layer over the resistor structure; forming a second dielectric layer on the substrate and on the resistor structure; etching to form through holes reaching the two landing pads; filling the through-hole with a conductive material; and A metal contact is formed on the through hole.

10. The method according to claim 9, characterized in that A peripheral portion of the sidewall spacer extends below the resistor material layer.

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