Multi-chain measurement circuit

Abstract

A multi-chain measurement circuit is disclosed. The measurement circuit includes a first chain and a second chain of series snubber circuits coupled in parallel, each series snubber circuit propagating an input signal. The set of storage circuits is configured to store logic values generated by the first set of buffer circuits and the second set of buffer circuits in response to a transition of the clock signal. The logic value stored in the storage circuit produces a digital value indicating a total number of series storage circuits through which the input signal has propagated when operating the transition of the clock signal.

Description

Background Art Technical Field

[0001] The present disclosure relates to electronic circuits, and more particularly to electronic circuits for performing measurements.

[0002] Related technical description

[0003] Measurement circuits, such as time-to-digital converters (TDCs), are used in a number of different applications. A TDC can measure the amount of time that has passed since a particular event occurred, and can convert that time into a digital value. One example application of a TDC is voltage sag detection, where it is detected that the supply voltage has dropped below a certain specified level.

[0004] A TDC typically includes a chain of delay elements with corresponding storage elements. An input signal indicating the start of an event may propagate through the chain of delay elements, and the storage elements may capture corresponding output values ​​from the delay elements in response to a clock signal. The output word indicated by the aggregate value stored in the various storage elements may include multiple consecutive logic values ​​(e.g., logic ones) followed by multiple consecutive complementary logic values ​​(e.g., logic zeros). The resulting output word may indicate the amount of time a particular event has occurred. Summary of the invention

[0005] A multi-chain measurement circuit is disclosed. In one embodiment, a measurement circuit includes a first delay circuit having a first set of series buffer circuits, wherein the first set of buffer circuits is configured to propagate an input signal; and a second delay circuit, the second delay circuit being connected in parallel with the first delay circuit, the second delay circuit including a second set of series buffer circuits configured to propagate the input signal. The measurement circuit also includes a storage circuit set, the storage circuit set being configured to store logic values ​​generated by the first set of buffer circuits and the second set of buffer circuits in response to a transition of an operating clock signal. The measurement circuit is configured to use the logic values ​​stored in the storage circuit set to output a digital value indicating the total number of series buffer circuits in the first set of buffer circuits and the second set of buffer circuits through which the input signal has propagated at the transition of the operating clock signal.

[0006] In one embodiment, the measurement circuit is a time-to-digital converter (TDC). The TDC may include a first delay chain and a second delay chain, the first delay chain and the second delay chain coupled to various storage elements in a plurality of storage elements, such as a trigger circuit. The trigger circuit may capture a digital value in response to a clock signal, wherein the digital value indicates the number of serially coupled buffer circuits in the first delay chain and the second delay chain through which the input signal has propagated. The use of multiple delay chains may make the dynamic range wider and increase the granularity of the measurements performed by the circuit. Additionally, the use of multiple delay chains may also make the measurement delay smaller and the measurement throughput higher. In one embodiment, the TDC may be used in a voltage drop detection circuit to detect a drop in the supply voltage, thereby allowing the power management circuit to take corrective action. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0008] Figure 1 is a block diagram of one embodiment of a measurement circuit.

[0009] Figure 2 is a diagram of one embodiment of a time-to-digital converter (TDC) having multiple delay chains.

[0010] Figure 3 is a diagram of another embodiment of a TDC having multiple delay chains.

[0011] Figure 4 is a diagram of one embodiment of a system utilizing a TDC to detect voltage drops.

[0012] Figure 5 is a flow chart of one embodiment of a method for operating a measurement circuit.

[0013] Figure 6 is a flow chart of one embodiment of a method for operating a voltage sag detection circuit.

[0014] Figure 7 is a block diagram illustrating one embodiment of an example system. DETAILED DESCRIPTION

[0015] The present disclosure relates to a measurement circuit, such as a time-to-digital converter (TDC). Measurement circuits, such as TDCs, are used in a number of different applications, such as voltage sag detection. In such circuits, it is often desirable to have a wider dynamic range and better measurement granularity. This can be achieved by using longer delay chains. However, longer delay chains have greater propagation delays, which limits the dynamic range and measurement granularity that can be achieved, and therefore limits the systems that utilize these circuits.

[0016] The present invention takes advantage of the recognition that multiple chains operating in parallel can allow an input signal to propagate through more delay elements in a given amount of time relative to a single chain implementation. For example, the present disclosure contemplates a dual-chain TDC as a measurement circuit. The delay chain includes delay circuits, each of which has multiple serially coupled buffers (e.g., inverters) that receive a common input signal. The signals propagating through the delay chains can be complementary to each other, but aligned in time. After receiving an input signal, a version of the input signal is propagated concurrently through the delay chains. After a clock signal transition, a storage circuit coupled to the delay chain can capture and hold the output states of various serially coupled buffers in the serially coupled buffers. The output states can be provided to, for example, a register, and a digital word corresponding to a measured value can be formed.

[0017] Different configurations (such as odd-even configurations and true-complementary configurations) are possible and contemplated. Additionally, embodiments using flip-flop circuits with multiple clock inputs are also possible and contemplated. In such embodiments, the flip-flops may be operated according to a clock received via a clock node, wherein all flip-flops are clocked at approximately the same time, or may be operated based on a clock signal received from a fine-tuning clock circuit. When operating using a fine-tuning clock signal, the effective stage delay is the difference between the stage delay of the delay chain through which the input signal propagates and the stage delay of the delay chain through which the fine-tuning clock signal propagates. The delay chain of the fine-tuning clock circuit is designed to make the propagation of the fine-tuning clock signal faster than the delay chain through which the input signal propagates. However, since the fine-tuning clock delay chain is made faster, the effective stage delay is faster than the gate delay of the data chain. Therefore, a higher resolution can be obtained.

[0018] Thus, a multi-chain measurement circuit as disclosed herein can provide higher resolution than a single-chain circuit (eg, such as a single-chain TDC). Higher resolution can in turn enable higher sampling rates, and thus more frequent measurements.

[0019] The dual chain design of the present disclosure can also reduce dead time. In a single chain design, only rising signal propagation is used, so it is necessary to reset the chain before the next measurement. In contrast, the dual chain design disclosed herein can use both rising propagation and falling propagation to operate alternately, for example, rising during the first operation and falling during the next operation, and so on, so as not to cause the dead time of the single chain design. The single chain design may have rising-falling asymmetry because the rising propagation distance may be different from the falling propagation distance due to circuit changes, PMOS / NMOS asymmetry, etc. In the dual chain design, the two chains are designed to be symmetrical and complementary to each other. Therefore, in the dual chain design, the rising transition and falling transition between the two chains occur in a symmetrical and complementary manner, for example, the signal rises at the output of one inverter in the first chain and falls in the corresponding inverter in the second chain at substantially the same time. Therefore, there is no rising / falling asymmetry in the dual chain design.

[0020] A more detailed discussion of the present disclosure is provided in Figure 1 The present invention begins with a general embodiment of a multi-chain measurement circuit in a embodiment of a multi-chain measurement circuit, followed by a discussion of an odd / even embodiment and a true / complementary embodiment. A block diagram of a system using an embodiment of a measurement circuit as disclosed herein in a voltage sag detection circuit is then described. Subsequently, various method embodiments for operating the measurement circuit are described with reference to a flow chart. The discussion concludes with a description of an example system that may include an example of a measurement circuit as disclosed herein.

[0021] Multi-chain measurement circuit implementation :

[0022] Figure 1 1 is a diagram of one embodiment of a multi-chain measurement circuit. In the illustrated embodiment, the measurement circuit 100 includes a first delay chain 101-A having a first plurality of serially coupled buffer circuits 115 and a second delay chain 101-B having a second plurality of serially coupled buffer circuits 115. Although not explicitly shown here, one of the delay chains 101 may be offset in delay (e.g., by one gate delay) relative to the other delay chain to generate complementary but aligned signals in the delay chains.

[0023] The output of each buffer circuit in the buffer circuit 115 is coupled to the input of the corresponding storage circuit 117, which can be implemented using a flip-flop, a latch, or other suitable storage circuit types. Figure 2 As shown, some storage circuits 117 are coupled to only one of the delay chains, while other storage circuits 117 are coupled to another delay chain. Figure 3As shown, each storage circuit 117 includes a real input terminal coupled to one of the delay chains and a complementary input terminal coupled to the other delay chain. When a signal is input into the delay chain 101, the corresponding first signal propagates from one buffer circuit 115 to the next buffer circuit through the delay chain 101-A and the second signal through the delay chain 101-B. As noted above, one of the signals may be a delayed version of the other signal. When the clock signal (Clk) switches to an active state, the output states of the various buffer circuits 115 are captured in the corresponding coupled storage circuits in the storage circuits 117. The output terminal (D_out) of the storage circuit 117 may be coupled to a register or other type of memory that may receive the captured value. The captured value forms a data word corresponding to the measurement performed by the measurement circuit.

[0024] The measurement circuit 100 can be used in a variety of applications. In one embodiment, discussed in further detail below, the measurement circuit 100 can operate as a TDC that detects a voltage drop from a supply voltage. The power management circuit can use the indication of the voltage drop to take corrective action to return the supply voltage to within specified limits.

[0025] Other applications of the measurement circuit 100 are possible and contemplated. For example, it is possible and contemplated to use the circuit to measure clock deviation. A first clock signal may be provided as an input signal, and a second clock signal may be provided as a capture signal to a storage circuit. This may enable measurement of the deviation between the first clock signal and the second clock signal based on the number of buffer circuits through which the first clock signal propagates. Measurement of duty cycle distortion is another possible application of the circuit. The input signal may come from the falling edge of the clock signal, and the storage element may be triggered by the rising edge of the same clock signal, wherein the circuit measures the width of the low phase of the clock signal based on the number of buffer circuits through which the clock signal propagates. It should be noted that these two examples are not intended to be limiting, and other applications are possible.

[0026] Figure 22 is a block diagram of another embodiment of a measurement circuit. In the illustrated embodiment, the measurement circuit 200 is arranged in an odd / even configuration and includes two delay chains. In this embodiment, the delay circuit 203-E is an even chain, and the delay circuit 203-O is an odd chain. In this particular embodiment, the buffer is implemented as an inverter 210. The measurement circuit 200 also includes a plurality of storage circuits 205, which are implemented here as flip-flops with differential inputs. The input of the storage circuit 205-A is coupled to the delay circuit 203-E, and the input of the storage circuit 205-B is coupled to the delay circuit 203-O. Each of the storage circuits 205-A and 205-B in this embodiment includes two different clock inputs and can be operated according to one of the clocks depending on the specific operating mode. In the normal operating mode, the first clock signal Clk_M can be provided to the clock inputs of the storage circuits 205-A and 205-B, respectively. In the fine-tuning mode of operation, the clock signal Clk_V may be received from the fine-tuning clock circuit 215 by the storage circuit 205-A and the storage circuit 205-B. In the illustrated embodiment, the fine-tuning clock circuit 215 is divided into a branch 215-E (for the even portion of the circuit) and a branch 215-O (for the odd portion of the circuit). The measurement circuit 200 in the illustrated embodiment also includes an edge aligner 211 that is coupled to receive an input signal and is configured to generate two complementary and aligned signals. Additionally, one or more inverter pairs may be coupled between the delay circuit 203-E and the delay circuit 203-O (and between the delay circuit 215-E and the delay circuit 215-O).

[0027] As noted above, the storage circuits 205 in the illustrated embodiment are implemented as differential flip-flops, each having a true input and a complementary input. With respect to a given inverter in the inverter 210 in the corresponding delay circuit 203, each of the storage circuits 205 has a true input coupled to the input of the buffer circuit 210 and a complementary signal coupled to the output of the same buffer circuit 210. Thus, each of the storage circuits 205 is arranged to capture both the input state and the output state of the corresponding coupled inverter 210. The storage circuits in the storage circuits 205 in the illustrated embodiment include an output D_out that can be coupled to a register.

[0028] Delay circuit 203-E and delay circuit 203-O are arranged to propagate signals through their buffers, wherein a certain delay is applied to the former relative to the latter. In this embodiment, the delay is completed by edge aligner circuit 211, which includes an instance of inverter 210 and channel gate PG1. The input signal can be propagated to the first inverter 210 of delay circuit 203-O through the channel gate. In the even chain, edge aligner circuit 211 includes an inverter coupled to delay circuit 203-E, which results in generating a signal complementary to the signal in the odd chain but aligned in time. The odd chain includes inverter 210-D, which causes the odd chain to start one inverter delay later than the even chain.

[0029] Because there may be circuit mismatches between the two delay chains, one or more instances of an inverter pair 217 are coupled between delay circuit 203-E and delay circuit 203-O (this also applies to delay chain 215-E and delay chain 215-O of the fine-tuning clock circuit). The actual number of inverter pairs 217 coupled between delay circuit 203-E and delay circuit 203-O may vary from implementation to implementation. While it is possible for an inverter pair 217 to be coupled between each of the input / output terminals of a corresponding inverter 210 in the delay circuit, various implementations with fewer inverter pairs 217 are possible and contemplated, including Figure 2 The exact number of inverter pairs 217 may be implemented to be a number sufficient to reduce mismatch between delay chains to negligible amounts across process, voltage, and temperature variations, and to enforce that signals in one delay chain are complementary and aligned with respect to signals in another delay chain.

[0030] In the first mode of operation, the measurement circuit 200 operates according to the clock signal transmitted on the clock node Clk_M. When the clock signal transitions from an inactive state to an active state, each of the storage circuit 205-A and the storage circuit 205-B receives the transition substantially simultaneously. Therefore, the values ​​of the inverter output terminals in the two delay circuits 203-E and 203-O are captured substantially simultaneously.

[0031] The output values ​​captured by storage circuit 205-A and storage circuit 205-B form a data word that can indicate how far the input signal has propagated. For example, a data word can include a string of logic ones followed by a string of logic zeros (e.g., 1111100000, which is a thermometer code). Thus, the point in the word where the last logic one meets the first logic zero indicates how far the input signal has propagated through delay circuit 203-E and delay circuit 203-O. The value can also indicate the amount of time since the start of the event. For example, when measurement circuit 200 is used in a voltage sag detection circuit, a large number of logic ones followed by a small number of logic zeros may indicate that a voltage sag has not occurred, while a small number of logic ones followed by a large number of logic zeros may indicate that a voltage sag has occurred and some corrective action is needed.

[0032] By using two different delay circuits 203-E and 203-O in the illustrated implementation, the resolution of the measurements performed can be effectively doubled when the delays are the same compared to a similar circuit using only a single delay chain / circuit. Thus, in the example of using measurement circuit 200 as a TDC, the accuracy of the measurements can be twice that of a single delay chain implementation.

[0033] When operating in a fine-tuning clock mode, the resolution can be further improved. In this fine-tuning mode, the clock signal Clk_V is provided to the corresponding input of the storage circuit 205 via the fine-tuning circuit 215, which is shown here as a branch 215-E and a branch 215-O, but it should be understood that these branches are part of the same circuit. It should be noted that the Clk_M signal is suppressed during this operating mode, just as Clk_V is suppressed when operating in the first mode (when Clk_M is operating). The fine-tuning circuit 215 includes an additional inverter and a channel gate PG2 to form an edge aligner circuit, the function of which is similar to the function of the edge aligner circuit 211 described above. Additionally, one or more inverter pairs are coupled between the individual branches of the fine-tuning circuit 215. The use of edge alignment circuitry may ensure that the fine clock signals are complementary and aligned between chain 215 -E and chain 215 -O, while the use of inverter pair 217 coupled between the delay chains may help maintain alignment between the two chains of fine clock circuitry 215 .

[0034] Operation in the trimming mode causes the various storage elements to capture the respective states of the correspondingly coupled inverters 210 in the delay chains 203-E and 203-O at different times compared to operation based on the Clk_M clock signal. Since the delay chain of the trimming clock circuit 215 includes the inverters 210 to provide delays, in the illustrated embodiment, each successive storage circuit 205 receives a transition to the active clock state two inverter delays later than the previous storage circuit 205. Thus, the storage circuits 205 are triggered one by one by the clock transitions. In one embodiment, the delay chain of the trimming circuit 215 is arranged so that the propagation of the trimming clock signal is faster than the propagation of the input signal through the delay chain of the delay circuit 203. Due to this difference in propagation speed, the effective stage delay between the inverters 210 may be faster than the normal gate delay because the effective stage delay is the difference between the stage delay of the delay chain in the delay circuit 203 and the stage delay of the inverter 210 in the delay chain of the trimming clock circuit 215. Therefore, a higher resolution may be obtained when operating in the fine tuning mode because the resolution when operating according to the clock signal Clk_M is based only on the stage element delays of the inverters in the delay circuit 203 .

[0035] It should be noted that fine-tuning clock circuit 215 is optional and may be omitted in implementations where sufficient resolution can be provided by the stage delays of the inverters in the delay circuit to meet design goals.

[0036] Figure 3 300 is a diagram of another embodiment of a measurement circuit. In the illustrated embodiment, the measurement circuit 300 is implemented in what can be called a true / complementary embodiment. The measurement circuit 300 includes a delay circuit 303 divided into a delay circuit 303-T and a delay circuit 303-C. A plurality of storage circuits 305 have differential inputs, one of which is a true input and one is a complementary input. Each of the storage circuits 305 includes an input coupled to the delay circuit 303-T and another input coupled to the delay circuit 303-C. The storage circuit 305 is connected to the delay circuit 303 in a manner alternating between the illustrated Class A connection and the Class B connection. In the Class A connection, the storage circuit 305 has a true input (In_T) coupled to the delay circuit 303-T and a complementary input (In_C) coupled to the delay circuit 303-C. In the Class B connection, the storage circuit 305 has a true input coupled to the delay circuit 303-C and a complementary input coupled to the delay circuit 303-T.

[0037] Each of the storage circuits 305 includes a first clock input and a second clock input for receiving a Clk_M signal or a Clk_V signal, respectively. Depending on the current operating mode, only one of these clocks is operating at any given time. When the Clk_M signal is provided as an operating clock, each of the storage circuits 305 is triggered to capture a data value substantially simultaneously. When operating in the fine-tuning clock mode, the storage circuits 305 are triggered one by one in an alternating manner, for example, a storage circuit 305 of type A connection is triggered first, followed by a storage circuit 305 of type B connection, then another storage circuit 305 of type A connection, and so on.

[0038] In an embodiment including a trimming clock circuit, the true / complementary topology of the measurement circuit 300 can also be defined by the way the trimming clock circuit is connected. In the illustrated embodiment, the trimming clock circuit 315 includes a first delay circuit 330 and a second delay circuit 331. The trimming clock input of the storage circuit 305 having a class A connection is coupled to receive the trimming clock signal from the delay circuit 330. The trimming clock input of the storage circuit 305 having a class B connection is coupled to receive the trimming clock signal from the delay circuit 331.

[0039] Both the delay circuit 303 and the fine-tuning clock circuit 315 include respective edge aligner circuits 311 at their respective front ends. These edge aligner circuits 311-D and 311-V may perform the same functions as described above with reference to Figure 2 Specifically, edge aligner circuit 311 -D and edge aligner circuit 311 -V can ensure that complementary and aligned signals propagate through the respectively coupled delay chains.

[0040] Additionally, both the delay circuit 303 and the fine-tuning clock circuit 315 in the illustrated embodiment include one or more inverter pairs 317 to compensate for mismatches between their respective delay chains. In providing such compensation, these inverter pairs can force the signals to remain complementary and aligned between the delay chains.

[0041] System for voltage drop detection using measurement circuit as TDC :

[0042] Figure 44 is a block diagram of an embodiment of a system including a voltage drop detection circuit that detects a voltage drop using an embodiment of a measurement circuit disclosed herein as a TDC. In the illustrated embodiment, the system 400 includes a power supply 409 that provides a supply voltage Vdd to a load circuit 411. The load circuit 411 may include analog circuits, digital circuits, and / or mixed signal circuits. The power supply 409 in the illustrated embodiment may be a type of power converter among a variety of different types of power converters, including various types of linear voltage regulators or switching regulators. For example, the power supply 409 may be a buck regulator that generates Vdd based on an input voltage and performs switching in a pulse frequency modulation (PFM) and pulse width modulation (PWM) mode to match the output current with the current required by the load circuit 411. Additionally, embodiments in which the supply voltage Vdd can be changed according to the performance state of the load circuit operation are possible and contemplated.

[0043] In the illustrated embodiment, the load circuit 411 is coupled to receive a clock signal Clk_C from a clock generator 425, which can be implemented using any suitable clock generation circuit. In some embodiments, the frequency of the Clk_C signal can be variable to, for example, conform to a specific operating state, similar to the supply voltage Vdd. For example, when higher performance is required, the voltage and frequency of Vdd and Clk_C can be increased, respectively. When performance requirements are lower or energy saving is a priority, these values ​​can be reduced. The specific voltage of Vdd and the specific frequency of Clk_C can be controlled using a V_ctrl signal and a F_ctrl signal, respectively, as generated by the power management circuit 421.

[0044] The system 400 in the illustrated embodiment includes a voltage drop monitor 410, which includes an embodiment of a measurement circuit implemented as a TDC 401 as disclosed herein. In the illustrated embodiment, the TDC 401 is coupled to receive a supply voltage Vdd that is the same as the supply voltage provided to the load circuit 411 so as to be able to detect a voltage drop caused by the latter. The clock generator 423 in the illustrated embodiment is configured to generate both a Clk_M signal and a Clk_V signal provided to the TDC 401, and an operating mode may also be selected by providing one of these signals at a time. In some embodiments, the clock generator 423 may be coupled to the clock generator 425, so that the clock signal generated by the former may be dependent on Clk_C. In some embodiments, the power management circuit 421 may communicate with the clock generator 423 to request or select a specific operating mode.

[0045] The TDC 401 in the illustrated embodiment is coupled to monitor the supply voltage Vdd. One of the two clock signals is provided from the clock generator 423, causing the TDC 401 to periodically capture values, as described above for various embodiments. These values ​​are provided to the register 403 to form a data word, which is then forwarded to the power management circuit 421. If the supply voltage Vdd remains within the specified limits, the data word may remain substantially or completely unchanged between different cycles. However, if a voltage drop occurs, the value of the data word may change significantly relative to the value generated when Vdd is within the specified limits. When this occurs, the power management circuit 421 can detect the change in the value of the data word, and various actions can be performed to correct the drop. For example, the power management circuit 421 can use the F_ctrl signal to reduce the frequency of Clk_C, or can completely suppress the clock signal for a certain amount of time. This can reduce the current consumption of the load circuit 411, thereby allowing the voltage Vdd to recover to within the specified limits. The power management circuit 421 may also or alternatively change the operating mode of the power supply 409 to increase its output current. For example, the power management circuit 421 may cause the power supply 409 to increase the switching frequency of the buck converter when operating in the PFM mode, or to increase the pulse width when operating in the PWM mode. In general, in response to receiving an indication of a voltage sag from the voltage sag detection circuit 410, the power management circuit 421 may take any suitable action that causes the supply voltage Vdd to return to its expected value.

[0046] Because the TDC 401 in the illustrated embodiment is based on an embodiment of a measurement circuit as disclosed herein, it may be able to perform measurements at a higher resolution than, for example, an embodiment of a TDC that relies on a single delay chain. Due to the multiple delay chains, the input signal may propagate through a greater number of buffer circuits (e.g., inverters) than would result from using a single delay chain. This may enable faster detection of voltage drops, and therefore faster response in initiating corrective action to restore the supply voltage to its nominal value.

[0047] Method flow chart :

[0048] Figure 5 is a flow chart of one embodiment of a method for operating a measurement circuit. Method 500 may be performed by any of the various embodiments of the measurement circuit as discussed above. Embodiments of the measurement circuit that are capable of performing method 500 but are not disclosed herein also fall within the scope of the present disclosure.

[0049] The method 500 includes providing an input signal to a first delay circuit having a first plurality of series buffer circuits and a second delay circuit having a second plurality of series buffer circuits (block 505). The method also includes propagating a first signal based on the input signal in the first plurality of series buffer circuits (block 510), and propagating a second signal based on the input signal in parallel in the second plurality of series buffer circuits (block 515). After the signals have propagated in the first plurality of series buffer circuits and the second plurality of series buffer circuits, the method 500 also includes capturing logic values ​​generated by the first set of buffer circuits and the second set of buffer circuits in some of the set of storage circuits in response to a transition of an operating clock signal (block 520). After capturing the logic values, the method continues to output a digital value from the set of storage circuits, wherein the digital value indicates a total number of the first plurality of series buffer circuits and the second plurality of series buffer circuits through which the input signal has propagated at the time of the transition of the operating clock signal (block 525).

[0050] In some embodiments, the method involves operating an odd / even implementation of the measurement circuit. The method in such embodiments includes providing corresponding input signals from the first plurality of series buffer circuits to some storage circuits in a first subset of the set of storage circuits, and providing corresponding input signals from the second plurality of series buffer circuits to some storage circuits in a second subset of the set of storage circuits. When operating the odd / even implementation of the measurement circuit, the method also includes propagating the input signal through the first plurality of series buffer circuits with a delay relative to the second plurality of series buffer circuits.

[0051] Embodiments in which the method involves operating a true / complementary embodiment of the measurement circuit are also possible and contemplated. In the true / complementary embodiment, the set of storage circuits is a differential storage circuit having corresponding true inputs and complementary inputs. The method of operating the true / complementary embodiment includes providing corresponding input signals from some of the first plurality of series buffer circuits to the true inputs of some of the storage circuits in a first subset of the set of storage circuits, and providing corresponding input signals from some of the second plurality of series buffer circuits to the complementary inputs of some of the storage circuits in the first subset of the set of storage circuits. The method also includes providing corresponding input signals from some of the first plurality of series buffer circuits to the complementary inputs of some of the buffer circuits in a second subset of the set of storage circuits, and providing corresponding input signals from some of the second plurality of series buffer circuits to the true inputs of some of the buffer circuits in the second subset of the set of storage circuits.

[0052] In various embodiments of the measurement circuit, some of the storage circuits in the set of storage circuits include a first clock input and a second clock input and are operable in a first mode or a second mode. In such embodiments, the method includes providing a first clock signal from a clock node to corresponding first clock inputs of some of the storage circuits in the set of storage circuits as the operational clock signal during operation in the first mode. During operation in the second mode, the method includes providing a second clock signal from a fine-tuning clock circuit to corresponding second clock inputs of some of the storage circuits in a first subset of storage circuits, and providing a third clock signal from the fine-tuning clock circuit to corresponding second clock inputs of some of the storage circuits in a second subset of storage circuits during operation in the second mode, wherein the second clock signal and the third clock signal are in antiphase relative to each other.

[0053] In various embodiments, the first signal is an input signal. In such embodiments, the method further comprises generating the second signal based on the input signal using an edge alignment circuit, wherein generating the second input signal comprises delaying the input signal such that the first signal and the second signal are in anti-phase relative to each other.

[0054] Figure 6 is a flow chart of one embodiment of a method for operating a measurement circuit as a time-to-digital converter (TDC) in a voltage sag detection circuit. The method may be performed using any of the embodiments of the measurement circuit as disclosed herein.

[0055] Method 600 includes using a TDC to monitor a supply voltage, which includes propagating an input signal through a first delay chain and a second delay chain of a dual-chain TDC (block 605). At some time thereafter, an active state of a clock signal is provided to the TDC, specifically, to a flip-flop thereof (block 610). In response to the clock signal transitioning to the active state (e.g., from low to high), the flip-flop in the TDC captures the output value of the buffer circuit and provides the values ​​to a register (block 615). The captured value (which forms a data word indicating whether a voltage drop has occurred) is provided to a power management circuit (block 620).

[0056] Based on the data word, the power management circuit can determine whether a voltage drop has occurred. If a voltage drop has not occurred (block 625, no), the method continues from block 605. If a voltage drop has occurred (block 625, yes), the power management circuit can take corrective action to return the supply voltage to a value within specified limits (block 630). Such actions may include, for example, changing the switching frequency of a switching power converter that provides the supply voltage, reducing the frequency of a clock signal provided to a circuit of a load of the power converter, temporarily gating a load clock signal, etc. Such actions may increase the ability of the power converter to provide current according to the needs of the load and / or reduce the current required by the load. Method 600 also returns to block 605 from block 630 to provide continuous monitoring of the supply voltage.

[0057] Example System :

[0058] Next turn Figure 7 , a block diagram of one embodiment of a system 700 is shown, which can incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 700 includes at least one instance of a system on a chip (SoC) 706, which can include multiple types of processing units (such as a central processing unit (CPU), a graphics processing unit (GPU) or other), a communication structure, and interfaces to memory and input / output devices. In some embodiments, one or more processors in the SoC 706 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 706 is coupled to an external memory 702, a peripheral device 704, and a power supply 708.

[0059] A power supply 708 is also provided that supplies a supply voltage to the SoC 706 and one or more supply voltages to the memory 702 and / or peripherals 704. In various embodiments, the power supply 708 represents a battery (e.g., a rechargeable battery in a smartphone, laptop or tablet computer, or other device). In some embodiments, more than one instance of the SoC 706 is included (and more than one external memory 702 is also included).

[0060] The memory 702 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to the circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the device can be mounted together with the SoC or integrated circuit in a chip stacking configuration, a package stacking configuration, or a multi-chip module configuration.

[0061] The SoC 706 in the illustrated embodiment and other integrated circuits implemented in the system 700 may include one or more instances of a measurement circuit as disclosed herein. The measurement circuit may be implemented in various applications, such as in a similar manner to the reference Figure 4 The voltage monitoring system described is implemented in the embodiment of the present invention.

[0062] Peripheral devices 704 include any desired circuitry, depending on the type of system 700. For example, in one embodiment, peripheral devices 704 include devices for various types of wireless communications such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, peripheral devices 704 also include additional storage, including RAM storage, solid-state storage, or disk storage. Peripheral devices 704 include user interface devices such as display screens, including touch screens or multi-touch screens, keyboards or other input devices, microphones, speakers, etc.

[0063] As illustrated, system 700 is shown as having applications in a wide range of fields. For example, system 700 can be used as a part of a chip, circuit, component, etc. of a desktop computer 710, a laptop computer 720, a tablet computer 730, a cellular or mobile phone 740, or a TV 750 (or a set-top box coupled to a TV). Smart watches and health monitoring devices 760 are also illustrated. In some embodiments, smart watches 760 may include various general computing related functions. For example, smart watches 760 may provide access to email, mobile phone services, user calendars, etc. In various embodiments, health monitoring devices may be dedicated medical devices or otherwise include dedicated health-related functionality. For example, health monitoring devices may monitor the vital signs of users, track the proximity of users to other users for the purpose of epidemiological social distance, contact tracking, provide communications to emergency services in the event of a health crisis, etc. In various embodiments, the above-mentioned smart watches may or may not include some or any health monitoring related functions. Other wearable devices are also envisioned, such as devices worn around the neck, devices that can be implanted in the human body, glasses designed to provide enhanced and / or virtual reality experiences, etc.

[0064] The system 700 may also be used as part of a cloud-based service 770. For example, the previously mentioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Still further, the system 700 may be used in one or more devices in a home other than those previously mentioned. For example, a home appliance may monitor and detect situations that warrant attention. For example, various devices in a home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device, and an alert may be provided to the homeowner (or, for example, a maintenance agency) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in a home, and may automatically adjust the heating / cooling system based on a history of responses by the homeowner to various situations. Figure 7 The application of system 700 to various modes of transportation is also illustrated. For example, system 700 may be used for control and / or entertainment systems for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, scooters (for rental or private use), etc. In various cases, system 700 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc. Any of these and many other embodiments are possible and contemplated. Note that Figure 7 The illustrated devices and applications are merely illustrative and are not intended to be limiting. Other devices are possible and contemplated.

[0065] ***

[0066] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. are not necessarily to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0067] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure that, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0068] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0069] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0070] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent claims consistent with the present disclosure is contemplated and may be claimed in this or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0071] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0072] ***

[0073] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0074] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" of an item refers to a collection of two or more of the items.

[0075] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0076] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0077] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0078] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0079] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0080] The phrase "based on" is used to describe one or more factors that influence a determination. The term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on specified factors or on specified factors and other unspecified factors. Consider the phrase "A is determined based on B." The phrase specifies that B is a factor used to determine A or that B influences the determination of A. The phrase does not exclude that the determination of A may also be based on some other factor such as C. The phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0081] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. The phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0082] ***

[0083] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. The expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. The phrase is not used herein to refer to an intangible thing.

[0084] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0085] The term "configured to" is not intended to mean "capable of being configured to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform a particular function.

[0086] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0087] Different "circuits" may be described in the present disclosure. These circuits or "circuits" constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuits.

[0088] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0089] In various embodiments, as described in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement relative to each other and such circuits / units / components and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by coding a description of a circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without excessive experimentation and using the application of ordinary technicians. HDL descriptions are often expressed in a way that can be displayed as functional. However, for those skilled in the art, the HDL description is a way to transform the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a particular set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0090] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of identical structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0091] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

[0092] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to include all such variations and modifications.

Claims

1. A device, comprising: A measuring circuit, wherein the measuring circuit comprises: a first delay circuit, the first delay circuit comprising a first set of series buffer circuits, wherein the first set of series buffer circuits is configured to propagate an input signal; a second delay circuit connected in parallel with the first delay circuit, wherein the second delay circuit comprises a second set of series buffer circuits configured to propagate the input signal; and a set of storage circuits configured to store logic values ​​generated by the first set of buffer circuits and the second set of buffer circuits in response to transitions of an operational clock signal; and wherein the measurement circuit is configured to use the logic value stored in the set of storage circuits to output a digital value indicating a total number of series buffer circuits in the first set of buffer circuits and the second set of buffer circuits through which the input signal has propagated at the time of the transition of the operating clock signal.

2. The apparatus of claim 1 , wherein a first subset of the set of storage circuits is coupled to selected series buffer circuits in the first set of series buffer circuits, and wherein a second subset of the set of storage circuits is coupled to selected series buffer circuits in the second set of series buffer circuits, and wherein the first set of series buffer circuits is configured to propagate the input signal with a delay relative to the second set of series buffer circuits.

3. The apparatus of claim 2 , wherein some of the storage circuits are differential trigger circuits, wherein some of the storage circuits in the first subset of storage circuits have a first input terminal coupled to an input terminal of a corresponding series buffer circuit in the first set of series buffer circuits and a second input terminal coupled to an output terminal of the corresponding series buffer circuit in the first set of series buffer circuits, and wherein some of the storage circuits in the second subset of storage circuits have a first input terminal coupled to an input terminal of a corresponding series buffer circuit in the second set of series buffer circuits and a second input terminal coupled to an output terminal of the corresponding series buffer circuit in the second set of series buffer circuits.

4. The apparatus of claim 1 , wherein some of the storage circuits in the set of storage circuits are differential storage circuits, and wherein some of the differential storage circuits in a first subset of the differential storage circuits include a true input terminal coupled to the first delay circuit and a complementary input terminal coupled to the second delay circuit, and wherein some of the differential storage circuits in a second subset of the differential storage circuits include a true input terminal coupled to the second delay circuit and a complementary input terminal coupled to the first delay circuit.

5. The apparatus of claim 1 , wherein some of the set of storage circuits comprise a first clock input and a second clock input, and wherein: During operation in the first mode, some of the set of memory circuits are configured to receive a first clock signal on their respective first clock inputs as the operational clock signal; as well as During operation in the second mode, some of the storage circuits in the first subset of the storage circuits are configured to receive the second clock signal as the operating clock signal at their corresponding second clock input terminals, and some of the storage circuits in the second subset of the storage circuits are configured to receive the third clock signal as the operating clock signal at their second clock input terminals.

6. The apparatus of claim 5 , further comprising a fine-tuning clock circuit having a third delay circuit and a fourth delay circuit, wherein the fine-tuning clock circuit is coupled to receive the second clock signal and is configured to generate a third clock that is complementary to and aligned with the second clock signal.

7. The apparatus of claim 6 , wherein the third delay circuit and the fourth delay circuit comprise a third set of series buffer circuits and a fourth set of series buffer circuits, respectively, and wherein delays provided by some of the third set of series buffer circuits and the fourth set of series buffer circuits are less than delays provided by some of the first set of series buffer circuits and the second set of series buffer circuits. 8 . The apparatus of claim 5 , further comprising a control circuit configured to cause the measurement circuit to operate in the first mode or the second mode.

9. The apparatus of claim 1, further comprising a plurality of pairs of cross-coupled inverter circuits coupled between the first set of series buffer circuits and the second set of series buffer circuits.

10. The apparatus of claim 1 , further comprising an edge alignment circuit coupled to the first set of series buffer circuits and the second set of series buffer circuits, wherein the edge alignment circuit is configured to receive the input signal and is further configured to: A first version of the input signal and a second version of the input signal are generated based on the input signal, wherein the second version of the input signal is complementary to and aligned with the first version of the input signal.

11. A method comprising: providing an input signal to a first delay circuit having a first plurality of series buffer circuits and a second delay circuit having a second plurality of series buffer circuits; propagating a first signal based on the input signal among the first plurality of series buffer circuits; propagating a second signal based on the input signal through the second plurality of series buffer circuits; capturing logic values ​​produced by the first plurality of series buffer circuits and the second plurality of series buffer circuits in some of the set of memory circuits in response to transitions of an operational clock signal; as well as A digital value is output from the set of storage circuits, wherein the digital value indicates a total number of the first plurality of series buffer circuits and the second plurality of series buffer circuits through which the input signal has propagated at the transition of the operational clock signal.

12. The method according to claim 11, further comprising: providing corresponding input signals from the first plurality of series buffer circuits to some memory circuits in a first subset of the set of memory circuits; as well as providing corresponding input signals from the second plurality of series buffer circuits to some of the memory circuits in a second subset of the set of memory circuits; The method further includes propagating the input signal through the first plurality of series buffer circuits with a delay relative to the second plurality of series buffer circuits.

13. The method of claim 11, wherein some of the memory circuits in the set of memory circuits are differential memory circuits having respective true and complementary inputs, and wherein the method further comprises: providing corresponding input signals from some of the first plurality of series buffer circuits to the real input terminals of some of the storage circuits in a first subset of the set of storage circuits; providing respective input signals from some of the second plurality of series buffer circuits to the complementary input terminals of some of the storage circuits in the first subset of the set of storage circuits; providing corresponding input signals from some of the first plurality of series buffer circuits to the complementary input terminals of some of the storage circuits in a second subset of the set of storage circuits; and Respective input signals are provided from ones of the second plurality of series buffer circuits to the real inputs of ones of the second subset of the set of memory circuits.

14. The method of claim 11, wherein some of the memory circuits in the set of memory circuits include a first clock input and a second clock input, and wherein the method further comprises: During operation in the first mode, providing a first clock signal from a clock node to corresponding first clock input terminals of some of the memory circuits in the set of memory circuits as the operational clock signal; providing a second clock signal from the fine-tuned clock circuit to respective second clock inputs of some of the memory circuits in the first subset of memory circuits during operation in the second mode; as well as During operation in the second mode, a third clock signal is provided from the fine clock circuit to respective second clock inputs of some of the second subset of memory circuits, wherein the second clock signal and the third clock signal are in antiphase relative to each other.

15. The method of claim 11, wherein the first signal is an input signal, and wherein the method further comprises generating the second signal based on the input signal using an edge alignment circuit, wherein the second signal is complementary to and aligned with the first signal.

16. A system, comprising: A voltage drop detection circuit, wherein the voltage drop detection circuit comprises a time-to-digital converter (TDC) circuit, the TDC circuit being coupled to receive a supply voltage provided to one or more functional circuits as an input signal, wherein the TDC circuit comprises: a first delay circuit having a first set of series buffer circuits configured to propagate a first signal based on the input signal; a second delay circuit having a second set of series buffer circuits, the second set of series buffer circuits configured to propagate a second signal based on the input signal; a set of storage circuits configured to store logic values ​​generated by the first set of series buffer circuits and the second set of series buffer circuits in response to transitions of an operating clock signal, wherein some of the storage circuits in the set of storage circuits are differential flip-flops having true and complementary inputs; and a register circuit coupled to receive the logic value from the set of storage circuits; wherein the voltage drop detection circuit is configured to detect a drop in the power supply voltage based on a value stored in the register circuit at a transition of the operation clock signal.

17. A system according to claim 16, wherein the set of storage circuits includes a first subset of storage circuits and a second set of storage circuits, wherein the real input terminals and complementary input terminals of some storage circuits in the first subset of storage circuits are coupled to the input terminals and output terminals of corresponding series buffer circuits in the first set of series buffer circuits, and wherein the real input terminals and complementary input terminals of some storage circuits in the second subset of storage circuits are coupled to the input terminals and output terminals of corresponding series buffer circuits in the second set of series buffer circuits.

18. The system of claim 16, wherein the set of storage circuits comprises a first subset of storage circuits and a second set of storage circuits, wherein one of the first subset of differential storage circuits comprises a true input terminal coupled to an output terminal of a first series buffer circuit in the first set of series buffer circuits and a complementary input terminal coupled to an output terminal of a first series buffer circuit in the second set of series buffer circuits, and wherein one of the second subset of storage circuits comprises a true input terminal coupled to an output terminal of a second series buffer circuit in the first set of series buffer circuits and a complementary input terminal coupled to an output terminal of a second series buffer circuit in the second set of series buffer circuits.

19. The system of claim 16, wherein some of the storage circuits in the storage circuit set comprise a first clock input and a second clock input, and wherein during operation in a first mode, some of the storage circuits in the storage circuit set are configured to receive an instance of the operating clock signal at the first clock input, and wherein during operation in a second mode, some of the storage circuits in the storage circuit set are configured to receive an instance of the operating clock signal at the second clock input via a fine-tuning clock circuit.

20. The system of claim 16, further comprising one or more inverter pairs coupled between the first set of series buffer circuits and the second set of series buffer circuits.

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