Closed-loop high-accuracy Hall effect sensor AFE with automatic return-to-zero switched capacitor analog accumulator

Abstract

The invention relates to a closed loop high accuracy Hall effect sensor (AFE) with an auto-zero switched capacitor analog accumulator. Disclosed herein is a system for measuring current comprising an input inductor and a self-test inductor through which respective input current and self-test current flow. A Hall effect sensor circuit senses a magnetic field around the inductors, thereby producing a differential voltage output. These outputs are received by an input and a self-test extraction circuit that alternately outputs a differential voltage representative of the magnetic field around the inductor. The amplification of these differential voltages is performed by an amplifier. The sampling of the amplified differential voltage is performed by two sample / hold circuits, each sample / hold circuit being specified for the magnetic field of a particular inductor. The integrator circuit adjusts the voltage of the Hall effect sensor circuit such that the gain applied to the sampled differential voltage remains consistent and unaffected by the sensitivity of the Hall effect sensor circuit.

Description

Technical Field

[0001] The present disclosure is directed to an analog front end for sensing current through a Hall effect sensor, which can compensate for changes in sensitivity of the Hall effect sensor due to temperature and stress. Background Art

[0002] A Hall Effect sensor is a transducer that responds to a magnetic field by changing its output voltage. This sensor operates by exciting a thin strip of conductive material with an electric current. When subjected to a magnetic field perpendicular to the direction of current flow, the field deflects the path of the charge carriers to one side of the material. This deflection results in a voltage difference between the opposite edges of the strip, known in the art as the Hall voltage, which is proportional to the strength of the magnetic field. This voltage is then measured, amplified, and output in analog or digital form.

[0003] The sensitivity of Hall Effect sensors can be variable, which can cause inconsistencies and inaccuracies in their output. Causes of this variability can include temperature changes, manufacturing variations, aging, and supply voltage instability. Compensation techniques have been developed to account for this.

[0004] For example, the temperature and strain on the sensor can be measured and digitized, and the sensitivity of the sensor can then be compensated in an open-loop manner by a digital signal processor; however, the efficiency of the compensation depends on the accuracy of the temperature and strain measurements, which can be questionable. As another example, an analog front end with continuous gain calibration with current bias is used, which requires a complex and space-consuming design that includes two high-accuracy analog-to-digital converters (ADCs) and a digital-to-analog converter (DAC). Digital feedback for gain and offset correction can lead to accuracy challenges. In addition, separating the signal, offset, and reference via frequency domain modulation and demodulation with such methods leads to a trade-off between the reference amplitude and the system output dynamics, and can cause accuracy issues, especially for nonlinear or high-bandwidth input signals.

[0005] Further development is needed to overcome these challenges. Summary of the invention

[0006] A system for measuring current is disclosed herein. The system combines an input inductor for inputting current and a self-test inductor for self-testing current. The magnetic field generated around these inductors is sensed by a Hall effect sensor circuit, which produces a differential voltage output.

[0007] The sensor circuit incorporates four Hall effect sensors. The physical orientation of these sensors is different, allowing them to respond to different magnetic field orientations of the input and self-test inductors. In addition, these sensors also respond to the earth's magnetic field in different directions (i.e., in-plane and out-of-plane).

[0008] The input and self-test extraction circuit is coupled to receive these voltage outputs from the Hall effect sensor circuit. This circuit alternates its output to provide a differential voltage indicating the magnetic field around either the input inductor or the self-test inductor based on a combination of the outputs from the four Hall effect sensors.

[0009] The amplifier amplifies these differential voltages. Two sample / hold circuits then sample these amplified differential voltages. The first sample / hold circuit samples when the differential voltage indicates a magnetic field around the self-test inductor, while the second sample / hold circuit does so for the input inductor.

[0010] The integrator circuit adjusts the voltage at the power input of the Hall effect sensor circuit. The adjustment is determined based on the error between the sampled differential voltage of the first sample / hold circuit and a given reference differential voltage. This allows the gain of the sampled differential voltage applied to the second sample / hold circuit to be unaffected by the sensitivity of the Hall effect sensor circuit.

[0011] The low pass filter filters the differential voltage from the second sample / hold circuit, whose output voltage is determined by a specific proportional formula. Furthermore, the signal accumulator and the reference accumulator are integrated to accumulate sampled voltages indicating the magnetic field around the input inductor and the self-test inductor, respectively. Both accumulators have specific configurations involving amplifiers, capacitors, and switches, which function in designated reset and accumulation phases to collect and process voltage data.

[0012] A method for measuring current is also disclosed herein. This method involves passing an input current through an input inductor and passing a self-test current through a self-test inductor. A Hall effect sensor circuit is used to sense the magnetic field around these inductors, thereby generating a differential voltage output. These outputs are received by input and self-test extraction circuits, which alternate output voltages representing the magnetic field around either the input inductor or the self-test inductor. These voltages are amplified using an amplifier.

[0013] The amplified voltages are sampled differently based on the magnetic field they indicate. The first sample / hold circuit samples the voltage when directed to the magnetic field around the self-test inductor, while the second sample / hold circuit samples when directed to the magnetic field around the input inductor. The integrator circuit adjusts the voltage applied to the power supply input of the Hall effect sensor circuit based on an error based on a comparison between the sampled differential voltage of the first sample / hold circuit and a reference differential voltage. This adjustment is such that the gain of the voltage applied to the second sample / hold circuit is not affected by any changes in the sensitivity of the Hall effect sensor circuit.

[0014] In addition, the method utilizes four Hall effect sensors to detect magnetic fields. Each sensor is oriented differently to receive various orientations of the magnetic field around the inductor and the earth's magnetic field. The outputs from these sensors are combined in a specific configuration to alternately represent the magnetic field around the self-test inductor and the input inductor. In addition, there is a specific combination of the outputs of these sensors to determine the magnetic field around each inductor and derive a differential voltage indicating these fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of a first embodiment of an analog front end for a Hall effect sensor circuit.

[0016] Figure 2 It is shown Figure 1 A diagram of the relationship between the physical orientation of each Hall effect sensor within a Hall effect sensor circuit and the magnetic fields surrounding the input inductor and the self-test inductor and the earth's magnetic field.

[0017] Figure 3 is a block diagram of a second embodiment of an analog front end for a Hall effect sensor circuit.

[0018] Figure 4A yes Figure 3 Schematic diagram of the signal accumulator.

[0019] Figure 4B It is shown Figure 4A Timing diagram of the operation of the switches of the signal accumulator.

[0020] Figure 5 yes Figure 3 Schematic diagram of the reference accumulator. DETAILED DESCRIPTION

[0021] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure can be applied to embodiments and applications other than those described above without departing from the spirit and scope of the disclosure. It is not intended to limit the disclosure to the embodiments shown, but rather to conform it to the widest scope consistent with the principles and features disclosed or suggested herein.

[0022] Note that in the following description, unless otherwise specified, any resistor or resistance mentioned is a discrete device, not just an electrical lead between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than the lead between the two points, and such a resistor or resistance cannot be interpreted as a lead. Similarly, unless otherwise specified, any capacitor or capacitance mentioned is a discrete device, not a parasitic element, unless otherwise specified. Furthermore, unless otherwise specified, any inductor or inductance mentioned is a discrete device, not a parasitic element, unless otherwise specified.

[0023] Reference now Figure 1 An analog front end 10 for a Hall effect sensor circuit 11 is described.

[0024] An input current Iin to be measured flows through the inductor Lin, and a self-test current Iist flows through the inductor Lst. The Hall effect sensor circuit 11 generates differential voltages V+, V- based on a magnetic field B around the inductors Lin and Lst.

[0025] The input and self-test extraction circuit 12 is connected to receive the output from the Hall effect sensor circuit 11. As will be explained in detail below, the input and self-test extraction circuit 12 alternates the output of its differential voltage to represent either the magnetic field Bin around the inductor Lin or the magnetic field Bst around the inductor Lst. This differential voltage is amplified by the amplifier 13 with a gain G. When the voltage output by the amplifier 13 represents the magnetic field Bst around the inductor Lst (in this example, the voltage is represented as VBst+, VBst-), ​​the sample / hold circuit 14 samples and holds the amplified differential voltage; when the voltage output by the amplifier 13 represents the magnetic field Bin around the inductor Lin (in this example, the voltage is represented as VBin+, VBin-), the sample / hold circuit 16 samples and holds the amplified differential voltage.

[0026] Referring back to the case where the voltage VBst+, VBst- representing the magnetic field Bst around the inductor Lst is output by the amplifier 13 and sampled by the sample / hold circuit 14, the integrator 15 integrates this sampled voltage after subtracting a reference voltage (given as Vref+, Vref-). This integration effectively produces a differential voltage V+, V- proportional to the difference between the sampled voltage VBst+, VBst- and the reference voltage Vref+, Vref-. This differential voltage V+, V- is connected to the Hall effect sensor circuit 11 so that the input and output of the sample / hold circuit 14 are matched to the reference voltage Vref+, Vref- via this feedback mechanism. This mechanism enables the circuit 10 to be calibrated by compensating for the sensitivity of the Hall effect sensor circuit 11.

[0027] In other words, the integrator 15 generates an error voltage by subtracting Vref+, Vref- from the sampled voltage. This error voltage is used to adjust the Hall effect sensor circuit 11 to reach a point where the error is substantially reduced to zero, which means that the input / output of the sample / hold circuit 14 is equal to Vref+, Vref-.

[0028] As explained, when the voltages VBin+, VBin- representing the magnetic field Bin around the inductor Lin are output by the amplifier 13, the sample / hold circuit 16 samples the differential voltage. Subsequently, the sampled voltages VBin+, VBin- are low-pass filtered via the filter 17, thereby generating an output voltage VOUT indicative of the input current Iin. Due to the operation of the feedback loop, the output VOUT of the LPF 17 (assuming that the gain of the amplifier 13 is unity) is equal to the ratio of the voltage VBin to the voltage VBst multiplied by the reference voltage Vref. Mathematically, this is expressed as:

[0029]

[0030] Therefore, the gain applied to the output voltage VOUT is simply the gain applied by amplifier 13 and is independent of the sensitivity of the Hall effect sensor circuit 11 .

[0031] Now go to Figure 2 , the operation of the input and self-test extraction circuit 12 is now described. The Hall effect sensor circuit 11 is composed of four independent Hall effect sensors, labeled H1, H2, H3 and H4. The physical placement of each Hall effect sensor H1-H4 provides a specific orientation relative to the magnetic field, as shown below:

[0032] As can be seen from H1, the magnetic field Bin around the inductor Lin points out of the page, the magnetic field Bst around the inductor Lst points into the page, and the magnetic field Bext of the environment (e.g., the earth's magnetic field) points into the page. Mathematically, this can be expressed as:

[0033] (1) BH1 = Bin-Bst-Bext

[0034] As can be seen from H2, the magnetic field Bin points out of the page, the magnetic field Bst points out of the page, and the magnetic field Bext points into the page. Mathematically, this can be expressed as:

[0035] (2) BH2 = Bin + Bst - Best

[0036] As can be seen from H3, the magnetic field Bin points into the page, the magnetic field Bst points into the page, and the magnetic field Bext points into the page. Mathematically, this can be expressed as:

[0037] (3) BH3=-Bin-Bst-Bext

[0038] As can be seen from H4, the magnetic field Bin points into the page, the magnetic field Bst points out of the page, and the magnetic field Bext points into the page. Mathematically, this can be expressed as:

[0039] (4) BH4 = -Bin + Bst - Bext

[0040] Equations (1), (2), (3), and (4) can be combined to solve for the magnetic fields Bin and Bst and form the following two equations:

[0041] (5)Bin=BH1+BH2-BH3-BH4

[0042] (6) Bst = BH2 + BH4 - BH1 - BH3

[0043] Thus, the function of the input and self-test extraction circuit 12 is to interconnect the Hall effect sensors H1, H2, H3 and H4 so that the resulting output from the Hall effect sensor circuit 11 alternates between representing the magnetic field Bin of the inductor Lin and the magnetic field Bst of the inductor Lst. Each of these Hall effect sensors H1-H4 has a first power supply input terminal and a second power supply input terminal (connected to the output terminal of the integrator 15), and a positive output terminal and a negative output terminal.

[0044] To add the outputs of the two Hall effect sensors, their positive outputs are connected to each other and their negative outputs are connected to each other within the input and self-test extraction circuit 12. Similarly, to subtract the output of one Hall effect sensor from the output of another Hall effect sensor, the positive output of the first Hall effect sensor is connected to the negative output of the second Hall effect sensor, and the negative output of the first Hall effect sensor is connected to the positive output of the second Hall effect sensor.

[0045] Accordingly, in order for the input and self-test extraction circuit 12 to output Bin, the output terminals of the Hall effect sensors H1, H2, H3, and H4 are connected as described above to produce equation (5), and in order for the input and self-test extraction circuit 12 to output Bst, the output terminals of the Hall effect sensors H1, H2, H3, and H4 are connected as described above to produce equation (6).

[0046] Thus, in order for the input and self-test extraction circuit 12 to output differential voltages VBst+, VBst- representing the magnetic field Bst surrounding the self-test inductor Lst, the Hall effect sensors H1-H4 are connected as described above to produce equation (6), and in order for the input and self-test extraction circuit 12 to output differential voltages VBin+, VBin- representing the magnetic field Bin surrounding the input inductor Lin (and thus representing the input current Iin), the Hall effect sensors H1-H4 are connected as described above to produce equation (5).

[0047] Reference now Figure 3Another embodiment of an analog front end 10' is described for the Hall effect sensor circuit 11. Note that in this embodiment, a reference accumulator 21 is coupled between the output of the amplifier 13 and the input of the sample / hold circuit 14, and a signal accumulator 22 is coupled between the output of the amplifier 13 and the input of the sample / hold circuit 16.

[0048] Now go to Figure 4A , specific details of the signal accumulator 22 are now given, where the signal accumulator 22 is represented in single-ended form in this example, so in this example, the voltage representing the magnetic field Bin around the inductor Lin is represented as VBin. The signal accumulator 22 includes an amplifier 31, whose non-inverting input terminal is connected to the bias voltage Vbias and whose inverting input terminal is connected to the node Nd. The switch S1 responds to the control signal! The voltage VBin representing the magnetic field Bin around the inductor Lin is selectively coupled to the node Nd1. The capacitor C1 is connected between the node Nd1 and the first terminal of the switch S2. The switch S2 is responsive to the control signal The capacitor C1 is selectively coupled to the node Nd. The switch S3 is responsive to the control signal The switch S4 is responsive to the control signal !. The voltage VBin representing the magnetic field Bin around the inductor Lin is selectively coupled to the node Nd2. The capacitor C2 is connected between the node Nd2 and the first terminal of the switch S5. The switch S5 is responsive to the control signal The capacitor C2 is selectively coupled to the node Nd. The switch S6 is responsive to the control signal The node Nd2 is selectively coupled to Vbias.

[0049] Capacitor Cf is connected between nodes Nd and Nd3. Switch S7 selectively couples node Nd3 to the output terminal of amplifier 31 in response to control signal !res. Switch S8 selectively couples node Nd3 to Vbias in response to control signal res. Switch S9 selectively couples node Nd to the output terminal of amplifier 31 in response to control signal res. Output voltage VOUT is generated at the output terminal of amplifier 31.

[0050] The operation of the signal accumulator 22 will now be described, which is used to automatically zero the amplifier offset and remove the delay caused by sampling. Figure 4B , where it can be seen that the operation goes through a reset phase, a first accumulation phase, and a second accumulation phase.

[0051] First, the reset phase is performed. Figure 4B As shown in FIG. 1 , during the reset phase, the control signal res is asserted, thereby closing switches S8 and S9, and the control signal and is asserted, thereby closing switches S2, S3, S5 and S6, and the remaining switches are open. This discharges capacitors C1, C2 and Cf and shorts the inverting input and output of amplifier 31 to each other.

[0052] After the reset phase, the first accumulation phase begins. During this phase, the control signal is deasserted (hence its inversion! is asserted), thereby closing switch S1 and transferring voltage VBin to node Nd1. At the same time, control signal Keeps asserted (hence its inversion! is deasserted), causing switches S2 and S6 to continue to close. This causes capacitor C1 to accumulate the voltage difference between VBin and Vbias via node Nd1. Since the voltage VBin fed to switch S4 has no effect in this first accumulation phase, switch S4 remains open, thereby ensuring that the voltage VBin is not connected to node Nd2. At the end of the first accumulation phase, the output voltage VOUT can be derived from the following relationship:

[0053] (C1+Cf)·Voffset=C1·(Voffset-Vin,n-1)+Cf·(Voffset-VOUT,n-1)

[0054] Wherein, Voffset is the offset of the amplifier 31 , and Vin,n is the voltage at the inverting input terminal of the amplifier 31 .

[0055] This can be arranged to produce:

[0056]

[0057] Next, the second accumulation phase begins. During this phase, the control signal is deasserted (thus controlling the signal! is asserted), thereby closing switch S4 and coupling voltage VBin to node Nd2. At the same time, control signal is asserted (thus controlling the signal! is deasserted), thereby closing switches S3 and S5. This causes capacitor C2 to accumulate the voltage difference between VBin and ground via node Nd2. The voltage VBin at switch S1 is not connected at this stage because switch S1 is disconnected due to the control signal ! Opened by deassertion.

[0058] At the end of the second accumulation phase, the output voltage VOUT can be obtained according to the following relationship:

[0059] Cf·(Voffset-VOUT,n-1)+C2·Voffset=C2·(Voffset-Vin,n)+Cf·(Voffset-VOUT,n)

[0060] This can be rearranged to produce:

[0061]

[0062] Substituting the value VOUT,n-1 from the previous stage yields:

[0063]

[0064] Therefore, note that the result is that the offset Voffset has been removed from VOUT by the accumulation phase.

[0065] Thus, this design for the signal accumulator 22 eliminates the offset inherent in the switched capacitor accumulator stage without introducing complexity. Furthermore, this design eliminates the need to sample the input signal, thereby eliminating latency issues and providing instant response time. Also, this design avoids introducing additional components into the virtual ground of the amplifier 31. Note that this design can be adapted to use a fully differential amplifier 31.

[0066] Now turn to Figure 5 , now specific details of the reference accumulator 21 are given, where the reference accumulator 21 is represented in single-ended form in this example, so in this example, the voltage representing the magnetic field Bin around the inductor Lst is represented as VBst. The signal accumulator 21 includes an amplifier 311, whose non-inverting input terminal is connected to the bias voltage Vbias and whose inverting input terminal is connected to the node N1d. The switch S11 responds to the control signal ! The voltage VBst representing the magnetic field Bst around the inductor Lst is selectively coupled to the node Nd11. The capacitor C11 is connected between the node Nd11 and the first terminal of the switch S12. The switch S12 is responsive to the control signal The capacitor C11 is selectively coupled to the node Nd. The switch S13 is responsive to the control signal The node Nd11 is selectively coupled to Vbias. The switch S14 is responsive to the control signal ! The voltage VBst representing the magnetic field Bst around the inductor Lst is selectively coupled to the node Nd12. The capacitor C12 is connected between the node Nd12 and a first terminal of the switch S15. The switch S15 is responsive to the control signal The capacitor C12 is selectively coupled to the node N1d. The switch S16 is responsive to the control signal The node Nd12 is selectively coupled to Vbias.

[0067] Capacitor C1f is connected between nodes N1d and Nd13. Switch S17 selectively couples node Nd13 to the output terminal of amplifier 311 in response to control signal !res. Switch S18 selectively couples node Nd13 to Vbias in response to control signal res. Switch S19 selectively couples node N1d to the output terminal of amplifier 311 in response to control signal res. Output voltage VOUT1 is generated at the output terminal of amplifier 311.

[0068] The operation of the reference accumulator 21 is the same as that of the signal accumulator 22, which is used to automatically zero the amplifier offset and remove the delay caused by sampling. Figure 4B , it can be seen that the operation goes through the reset stage, the first accumulation stage and the second accumulation stage.

[0069] During the reset phase, the control signal res is asserted, closing switches S18 and S19, and the control signal and is asserted, thereby closing switches S12, S13, S15 and S16, and the remaining switches are open. This discharges capacitors C11, C12 and C1f and shorts the inverting input and output of amplifier 311 to each other.

[0070] After the reset phase, the first accumulation phase begins. During this phase, the control signal is deasserted (hence its inversion! is asserted), thereby closing the switch S11 and directing the voltage VBst to the node Nd11. At the same time, the control signal Keep asserting (hence its inversion! is deasserted), causing switches S12 and S16 to continue to close. This causes capacitor C11 to accumulate the voltage difference between VBst and Vbias via node Nd11. Since the voltage VBst at switch S14 has no effect in this first accumulation phase, switch S14 remains open, thereby ensuring that the voltage VBst is not connected to node Nd12. At the end of this first accumulation phase, the output voltage VOUT1 can be derived from the following relationship:

[0071] (C1+Cf)·Voffset=C1·(Voffset-Vin,n-1)+Cf·(Voffset-VOUT1,n-1)

[0072] Wherein, Voffset is the offset of the amplifier 311 , and Vin,n is the voltage at the inverting input terminal of the amplifier 311 .

[0073] This can be arranged to produce:

[0074]

[0075] Next, the second accumulation phase begins. During this phase, the control signal is deasserted (thus controlling the signal! is asserted), closing switch S14 and coupling voltage VBst to node Nd12. At the same time, control signal is asserted (thus controlling the signal! is deasserted), thereby closing switches S13 and S15. This causes capacitor C12 to accumulate the voltage difference between VBst and Vbias via node Nd12. The voltage VBst at switch S11 is not connected at this stage because switch S11 is disconnected due to the control signal ! Opened by deassertion.

[0076] At the end of the second accumulation phase, the output voltage VOUT1 can be obtained according to the following relationship:

[0077] Cf·(Voffset-VOUT1,n-1)+C2·Voffset=C2·(Voffset-Vin,n)+Cf·(Voffset-VOUT1,n)

[0078] This can be rearranged to produce:

[0079]

[0080] Substituting the value VOUT,n-1 from the previous stage yields:

[0081]

[0082] Therefore, note that the result is that the offset Voffset has been removed from VOUT1 by the summation stage. This design can be adapted to use a fully differential amplifier 311 .

[0083] Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present disclosure.

[0084] Although the present disclosure has been described using a limited number of embodiments, those skilled in the art may, after benefiting from this disclosure, conceive of other embodiments that do not depart from the scope of the disclosure. In addition, those skilled in the art may conceive of embodiments that represent various combinations of the embodiments disclosed herein in various ways.

Claims

1. A system for measuring current, comprising: an input inductor through which the input current flows; a self-test inductor through which a self-test current flows; a Hall effect sensor circuit configured to sense magnetic fields around the input inductor and the self-test inductor and to generate a differential voltage output based thereon; an input and self-test extraction circuit coupled to receive the differential voltage output from the Hall effect sensor circuit and configured to alternately output a differential voltage indicative of a magnetic field around the input inductor and a magnetic field around the self-test inductor; an amplifier configured to amplify a differential voltage output by the input and the self-test extraction circuit; a first sample / hold circuit configured to sample the differential voltage output by the amplifier when the differential voltage indicates a magnetic field around the self-test inductor; a second sample / hold circuit configured to sample the differential voltage output by the amplifier when the differential voltage indicates a magnetic field around the input inductor; as well as an integrator circuit configured to adjust a voltage applied to a power supply input of the Hall effect sensor circuit based on an error between a differential voltage sampled by the first sample / hold circuit and a reference differential voltage such that a gain applied to the differential voltage sampled by the second sample / hold circuit is independent of the sensitivity of the Hall effect sensor circuit.

2. The system of claim 1, wherein: the Hall effect sensor circuit comprising a first Hall effect sensor, a second Hall effect sensor, a third Hall effect sensor, and a fourth Hall effect sensor, each Hall effect sensor being physically oriented differently so as to respond to different orientations of a magnetic field around the self-test inductor and a magnetic field around the input inductor; as well as The input and self-test extraction circuit is configured to combine the outputs of the first, second, third, and fourth Hall effect sensors in a particular configuration to alternately represent the magnetic field around the self-test inductor and the magnetic field around the input inductor.

3. The system of claim 2, wherein: The first Hall effect sensor is physically oriented so that it is affected by the magnetic field around the input inductor pointing out of the plane, the magnetic field around the self-test inductor pointing into the plane, and the earth's magnetic field pointing into the plane; The second Hall effect sensor is physically oriented so that it is affected by the magnetic field around the input inductor pointing out of the plane, the magnetic field around the self-test inductor pointing out of the plane, and the earth's magnetic field pointing in to the plane; a third Hall effect sensor physically oriented such that it is affected by the magnetic field around the input inductor in the pointing plane, the magnetic field around the self-test inductor in the pointing plane, and the earth's magnetic field in the pointing plane; as well as The fourth Hall effect sensor is physically oriented so that it is affected by the magnetic field around the input inductor pointing into the plane, the magnetic field around the self-test inductor pointing into the plane, and the earth's magnetic field pointing out of the plane.

4. The system of claim 2, wherein: To add outputs of two selected Hall effect sensors among the first Hall effect sensor, the second Hall effect sensor, the third Hall effect sensor, and the fourth Hall effect sensor, connecting positive output terminals of the selected two Hall effect sensors to each other and connecting negative output terminals of the two Hall effect sensors to each other; as well as To subtract the output of a first selected Hall effect sensor from among the first, second, third, and fourth Hall effect sensors from a second selected Hall effect sensor from among the first, second, third, and fourth Hall effect sensors, the positive output terminal of the first selected Hall effect sensor is connected to the negative output terminal of the second selected Hall effect sensor and the negative output terminal of the first selected Hall effect sensor is connected to the positive output terminal of the second selected Hall effect sensor.

5. The system of claim 4, wherein: To output a differential voltage representing the magnetic field surrounding the self-test inductor, the input and self-test extraction circuits are configured as: Connect the positive output of the second Hall effect sensor to the positive output of the fourth Hall effect sensor, Connect the negative output of the second Hall effect sensor to the negative output of the fourth Hall effect sensor, connecting the positive output of the first Hall effect sensor to the negative output of the third Hall effect sensor, and connecting the negative output terminal of the first Hall effect sensor to the positive output terminal of the third Hall effect sensor; as well as To output a differential voltage representing the magnetic field surrounding the input inductor, the input and self-test extraction circuits are configured as: Connect the positive output of the first Hall effect sensor to the positive output of the second Hall effect sensor, Connect the negative output of the first Hall effect sensor to the negative output of the second Hall effect sensor. connecting the positive output of the third Hall effect sensor to the negative output of the fourth Hall effect sensor, and Connect the negative output of the third Hall effect sensor to the positive output of the fourth Hall effect sensor. 6 . The system of claim 1 , further comprising a low pass filter configured to filter the differential voltage sampled by the second sample / hold circuit.

7. The system of claim 6, wherein a filter output voltage generated by the low pass filter is defined by a ratio between a differential voltage sampled at the second sample / hold circuit and a differential voltage sampled at the first sample / hold circuit and is scaled by a reference differential voltage.

8. The system of claim 1, further comprising a signal accumulator coupled between an output of the amplifier and an input of the second sample / hold circuit, the signal accumulator configured to accumulate a sampled voltage indicative of a magnetic field around the input inductor.

9. The system of claim 8, wherein the signal accumulator comprises: an amplifier having a non-inverting input terminal connected to a bias voltage and an inverting input terminal connected to a node; a first switch connected between a voltage representative of a magnetic field around the input inductor and the first node, the first switch being controlled by a complement of the second control signal; a first capacitor having a first terminal connected to a first node; a second switch connected between the second terminal of the first capacitor and the node, the second switch being controlled by the first control signal; a third switch connected between the first node and the bias voltage, the third switch being controlled by a second control signal; a fourth switch connected between a voltage representing a magnetic field Bin around the input inductor and the second node, the fourth switch being controlled by a complement of the first control signal; a second capacitor having a first terminal connected to the second node; a fifth switch connected between the second terminal of the second capacitor and the node, the fifth switch being controlled by a second control signal; a sixth switch connected between the second node and the bias voltage, the sixth switch being controlled by the first control signal; a feedback capacitor connected between the node and a third node; a seventh switch connected between the third node and the output terminal of the amplifier, the seventh switch being controlled by the complement of the reset signal; an eighth switch connected between the third node and the bias voltage, the eighth switch being controlled by a reset signal; A ninth switch is connected between the node and the output terminal of the amplifier.

10. The system of claim 9, wherein during a reset phase, a reset signal is asserted, the first control signal is asserted, and the second control signal is asserted, such that: Close the second and third switches to discharge the first capacitor: closing the fifth switch and the sixth switch to discharge the second capacitor; closing the eighth switch to discharge the feedback capacitor; as well as Connect the inverting input of the amplifier to the output of the amplifier to zero the amplifier.

11. The system of claim 10, wherein during the first accumulation phase, the reset signal is de-asserted, the first control signal is asserted, and the second control signal is de-asserted, such that: closing the seventh switch to connect the feedback capacitor between the inverting input and the output of the amplifier; and The first switch and the second switch are closed to charge the first capacitor to a difference between a voltage representative of a magnetic field around the input inductor and the bias voltage.

12. The system of claim 11 , wherein during the second accumulation phase, the reset signal is de-asserted, the first control signal is de-asserted, and the second control signal is asserted, such that: closing the seventh switch to connect the feedback capacitor between the inverting input and the output of the amplifier; and The fourth switch and the fifth switch are closed to charge the second capacitor to a difference between a voltage representative of a magnetic field around the input inductor and the bias voltage.

13. The system of claim 1, further comprising a reference accumulator coupled between an output of the amplifier and an input of the first sample / hold circuit, the reference accumulator configured to accumulate a sampled voltage indicative of a magnetic field surrounding the self-test inductor.

14. The system of claim 8, wherein the reference accumulator comprises: an amplifier having a non-inverting input terminal connected to a bias voltage and an inverting input terminal connected to a node; a first switch connected between a voltage representative of a magnetic field around the self-test inductor and the first node, the first switch being controlled by the complement of the second control signal; a first capacitor having a first terminal connected to a first node; a second switch connected between the second terminal of the first capacitor and the node, the second switch being controlled by the first control signal; a third switch connected between the first node and the bias voltage, the third switch being controlled by a second control signal; a fourth switch connected between a voltage representing a magnetic field Bst around the input inductor and the second node, the fourth switch being controlled by the complement of the first control signal; a second capacitor having a first terminal connected to the second node; a fifth switch connected between the second terminal of the second capacitor and the node, the fifth switch being controlled by a second control signal; a sixth switch connected between the second node and the bias voltage, the sixth switch being controlled by the first control signal; a feedback capacitor connected between the node and a third node; a seventh switch connected between the third node and the output terminal of the amplifier, the seventh switch being controlled by the complement of the reset signal; an eighth switch connected between the third node and the bias voltage, the eighth switch being controlled by a reset signal; A ninth switch is connected between the node and the output terminal of the amplifier.

15. The system of claim 14, wherein during a reset phase, a reset signal is asserted, the first control signal is asserted, and the second control signal is asserted, such that: Close the second and third switches to discharge the first capacitor: closing the fifth switch and the sixth switch to discharge the second capacitor; closing the eighth switch to discharge the feedback capacitor; as well as Connect the inverting input of the amplifier to the output of the amplifier to zero the amplifier.

16. The system of claim 15, wherein during the first accumulation phase, the reset signal is de-asserted, the first control signal is asserted, and the second control signal is de-asserted, such that: closing the seventh switch to connect the feedback capacitor between the inverting input and the output of the amplifier; and The first switch and the second switch are closed to charge the first capacitor to a difference between a voltage representative of a magnetic field around the self-test inductor and the bias voltage.

17. The system of claim 16, wherein during the second accumulation phase, the reset signal is de-asserted, the first control signal is de-asserted, and the second control signal is asserted, such that: closing the seventh switch to connect the feedback capacitor between the inverting input and the output of the amplifier; and The fourth switch and the fifth switch are closed to charge the second capacitor to a difference between a voltage representative of a magnetic field around the self-test inductor and the bias voltage.

18. A method for measuring current using a system, the method comprising: Pass the input current through the input inductor; passing a self-test current through the self-test inductor; sensing a magnetic field around an input inductor and a self-test inductor using a Hall effect sensor circuit and generating a differential voltage output based on the sensed magnetic field; receiving the differential voltage output of the Hall effect sensor circuit with an input and self-test extraction circuit and alternately outputting a differential voltage representative of either the magnetic field around the input inductor or the magnetic field around the self-test inductor; amplifying a differential voltage output by the input and the self-test extraction circuit using an amplifier; sampling the amplified differential voltage with a first sample / hold circuit when the differential voltage indicates a magnetic field around the self-test inductor; sampling the amplified differential voltage with a second sample / hold circuit when the differential voltage indicates a magnetic field around the input inductor; as well as Based on the error between the differential voltage sampled by the first sample / hold circuit and the reference differential voltage, the voltage applied to the power supply input terminal of the Hall effect sensor circuit is adjusted by the integrator circuit so that the gain applied to the differential voltage sampled by the second sample / hold circuit is independent of the sensitivity of the Hall effect sensor circuit.

19. The method of claim 18, wherein: Sensing the magnetic field includes using a first Hall effect sensor, a second Hall effect sensor, a third Hall effect sensor, and a fourth Hall effect sensor, each Hall effect sensor being physically oriented so as to respond to a different orientation of a magnetic field around the self-test inductor and a magnetic field around the input inductor; as well as Receiving the differential voltage output and alternately outputting the differential voltage includes combining the outputs of the first Hall effect sensor, the second Hall effect sensor, the third Hall effect sensor, and the fourth Hall effect sensor in a particular configuration to alternately represent the magnetic field around the self-test inductor and the magnetic field around the input inductor.

20. The method of claim 19, wherein: The first Hall effect sensor is oriented so that it senses a magnetic field around an input inductor pointing out of the plane, a magnetic field around a self-test inductor pointing into the plane, and an earth magnetic field pointing into the plane; a second Hall effect sensor oriented so that it senses the magnetic field around the input inductor pointing out of the plane, the magnetic field around the self-test inductor pointing out of the plane, and the earth's magnetic field pointing in to the plane; a third Hall effect sensor oriented so that it senses a magnetic field around the input inductor in the pointing plane, a magnetic field around the self-test inductor in the pointing plane, and an earth magnetic field in the pointing plane; as well as The fourth Hall effect sensor is oriented so that it senses the magnetic field around the input inductor pointing into the plane, the magnetic field around the self-test inductor pointing into the plane, and the earth's magnetic field pointing out of the plane.

21. The method of claim 19, wherein: combining the positive outputs of the selected two Hall effect sensors and combining the negative outputs of the selected two Hall effect sensors in order to add the outputs of the selected two Hall effect sensors among the first Hall effect sensor, the second Hall effect sensor, the third Hall effect sensor, and the fourth Hall effect sensor; and To determine a difference between an output of a first selected Hall effect sensor among the first, second, third, and fourth Hall effect sensors and a second selected Hall effect sensor among the first, second, third, and fourth Hall effect sensors, the positive output of the first selected Hall effect sensor is combined with a negative output of the second selected Hall effect sensor and the negative output of the first selected Hall effect sensor is combined with a positive output of the second selected Hall effect sensor.

22. The method of claim 21, wherein: To generate a differential voltage indicative of a magnetic field surrounding the self-test inductor, the method includes: combining a positive output of a second Hall effect sensor with a positive output of a fourth Hall effect sensor, combining a negative output of the second Hall effect sensor with a negative output of the fourth Hall effect sensor, combining a positive output of the first Hall effect sensor with a negative output of the third Hall effect sensor, and combining the negative output of the first Hall effect sensor with a positive output of the third Hall effect sensor; To generate a differential voltage indicative of a magnetic field surrounding an input inductor, the method includes combining a positive output of a first Hall effect sensor with a positive output of a second Hall effect sensor, combining a negative output of the first Hall effect sensor with a negative output of the second Hall effect sensor, combining a positive output of a third Hall effect sensor with a negative output of a fourth Hall effect sensor, and combining the negative output of the third Hall effect sensor with a positive output of a fourth Hall effect sensor.

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